TW201318077A - 替換源極／汲極鰭片式場效電晶體（ｆｉｎｆｅｔ）之製造方法 - Google Patents

替換源極／汲極鰭片式場效電晶體（ｆｉｎｆｅｔ）之製造方法 Download PDF

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TW201318077A
TW201318077A TW101123719A TW101123719A TW201318077A TW 201318077 A TW201318077 A TW 201318077A TW 101123719 A TW101123719 A TW 101123719A TW 101123719 A TW101123719 A TW 101123719A TW 201318077 A TW201318077 A TW 201318077A
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Daniel Tang
Tzu-Shih Yen
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Advanced Ion Beam Tech Inc
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Abstract

形成一種具有一鰭片之鰭片式場效電晶體，該鰭片包括源極區、汲極區和介於該些源極與汲極區之間的通道區。該鰭片被蝕刻於一半導體晶圓上。一閘極堆疊被形成為具有一直接接觸與該通道區之絕緣層及一直接接觸與該絕緣層之導電閘極材料。該些源極和汲極區被蝕刻而留下該鰭片之通道區。外延半導體被生長於其鄰接該些源極和汲極區之該通道區的側邊上，以形成源極外延區和汲極外延區。該些源極和汲極外延區被原位摻雜而同時生長外延半導體。

Description

替換源極/汲極鰭片式場效電晶體(FINFET)之製造方法
本發明一般而言係有關鰭片式場效電晶體(finFETs)之製造方法，及更明確地，有關具有替換源極和汲極之鰭片式場效電晶體的製造方法。
鰭片式場效電晶體是一種非平面的多閘極電晶體，其係依據如傳統金氧半導體場效電晶體(MOSFET)之相同原理而操作。矽之島狀物或鰭片被首先圖案化至晶圓上。在形成鰭片之後，一閘極堆疊被沈積並圖案化，以致圖案化的閘極材料係垂直於鰭片而流動。在圖案化的閘極材料覆蓋鰭片之處，形成鰭片式場效電晶體之閘極。鰭片式場效電晶體將具有一閘極於鰭片之兩垂直側壁上。根據鰭片之頂部表面的尺寸，鰭片式場效電晶體亦可具有一閘極於鰭片之頂部上。
例如，圖1描繪形成於絕緣體上矽(SOI)上之鰭片式場效電晶體100。鰭片結構102係從氧化物層108突出且升高至淺溝槽隔離(STI)106之上。閘極堆疊104係接觸鰭片結構102於其形成多個閘極之三個側邊上。一通道區係由鰭片結構102中之閘極堆疊104底下的區所界定。源極和汲極區係鄰接鰭片結構102中之相反端上的通道區。
圖2描繪形成於一SOI晶圓之氧化物層208上的傳統MOSFET 200。相對於鰭片式場效電晶體100(圖1)，矽 區202係由於STI 206而為平面的，其造成閘極堆疊204僅接觸矽區202之單一側並僅形成單一閘極。
鰭片式場效電晶體之多個閘極可提供超越傳統MOSFET之許多增進。例如，鰭片式場效電晶體更能抵抗短通道效應並可提供較高的電流驅動而同時增進次臨限擺動。
然而，鰭片式場效電晶體之非平面本質可能導致製造期間之數種困難。例如，傳統的植入器需要視線以將離子植入表面。為了摻雜鰭片式場效電晶體之源極或汲極的垂直側壁，晶圓必須被傾角地植入。為了克服來自近處鰭片式場效電晶體之陰影效應，該植入可能需被執行以數個角度或定向，其可能增加植入器工具複雜度、植入成本、及處理時間。另一方面，可實施設計規則以將非平面結構夠遠地隔開，來將陰影效應減至最小。然而，使用增加結構間隔之設計規則將導致較不稠密的電路。
傾角植入之一替代方式是電漿摻雜。然而，電漿摻雜可能具有其本身的缺點，諸如摻雜控制及對於摻雜濃度之限制。
於一範例實施例中，鰭片式場效電晶體被形成為具有一鰭片，該鰭片包括源極區、汲極區和介於該些源極與汲極區之間的通道區。該鰭片被蝕刻於一半導體晶圓上。一閘極堆疊被形成為具有一直接接觸與該通道區之絕緣層及 一直接接觸與該絕緣層之導電閘極材料。該些源極和汲極區被蝕刻而留下該鰭片之通道區。外延半導體被生長於其鄰接該些源極和汲極區之該通道區的側邊上，以形成源極外延區和汲極外延區。該些源極和汲極外延區被原位摻雜而同時生長外延半導體。該些源極和汲極外延區可對該通道區施加應變以增進該通道區中之電子或電洞的移動率。
下列描述被提呈以致能熟悉本項技術人士進行及使用各個實施例。特定裝置、技術、及應用之描述僅被提供為範例。對於此處所述之範例的各個修改將是那些熟悉本項技術人士所能輕易理解的，且此處所界定之一般性原理可被應用於其他範例及應用而不背離各個實施例之精神及範圍。因此，各個實施例不應被限制於此處所描述及顯示之範例，而應是符合與申請專利範圍一致的範圍。
圖3描繪一用以製造鰭片式場效電晶體之範例程序300。相應的圖4A-4C；5A-5C；6A-6C；7A-7C；8A-8C；9A-9C；及10A-10C係描繪依據範例程序300(圖3)之各個製造階段的鰭片式場效電晶體。
特別地，圖4A-4C描繪基底400，其為半導體晶圓之一部分。於本範例實施例中，基底400為大塊矽晶圓之一部分。然而，亦可使用其他型式的晶圓或基底，諸如SOI晶圓。同時，可使用矽之外的半導體材料，包括(但不限定於)Ge，SiGe，SiC，Gep，GeN，InGaAs，GaAs，InSb ，InAs，GaSb，及InP。
參考圖3，於操作302，一鰭片結構被蝕刻於基底上。圖5A-5C描繪在鰭片結構500之形成後的基底400，鰭片結構500係直接連接至晶圓之矽。此操作可使用標準半導體製作及蝕刻技術以形成鰭片結構500。
雖非必要，亦可在鰭片結構500之形成後形成一STI區。圖5A-5C描繪在STI 502之形成後的基底400。在形成鰭片結構500之後，STI絕緣材料可被沈積於基底之上。可使用諸如化學機械拋光(CMP)或蝕刻回等平坦化技術以移除STI絕緣材料直到STI 502之頂部504接近為具有鰭片結構500之頂部506的平坦。雖然圖5A-5C係顯示STI 502為具有鰭片結構500之完美的平坦，但實際上可能有小間距介於這些區之間。即使具有小間距，該些區仍被視為接近平坦的。於其他範例程序中，STI形成可能在稍後之處理中發生。例如，STI形成可發生在源極/汲極區已被蝕刻並再填入之後，如稍後參考圖14A-14C及15A-15C所討論者。
假如形成了STI區，則亦可使用蝕刻回以暴露鰭片結構之一部分。圖6A-6C描繪用以暴露鰭片結構500之頂部部分600的STI 502之蝕刻回以後的基底400。鰭片結構500之底部部分602保持由STI 502所覆蓋。於一範例中，STI絕緣材料係由二氧化矽所製。於此範例中，可使用對於晶圓之矽上方的氧化物具有選擇性的蝕刻，以蝕刻STI 502而不會蝕刻鰭片結構500之顯著的量。另一方面 ，可使用光抗蝕劑遮罩或硬遮罩以保護鰭片結構500於蝕刻回期間。於其他形成STI區之範例程序中，例如稍後參考圖12A-12C所討論者，蝕刻回可被稍後執行於程序中，在源極/汲極區已被蝕刻並再填入之後。
回來參考圖3，於操作304中，鰭片式場效電晶體之閘極係藉由沈積並圖案化一閘極堆疊而形成。圖7A-7C描繪在一閘極堆疊已被沈積並圖案化以形成閘極之後的基底400。閘極堆疊之沈積係從將閘極電介質700生長或沈積於基底400之上開始。圖7A-7C描繪閘極電介質700出現於鰭片結構500及STI 502之上。因此，於圖7A-7C之情況下，閘極電介質700不是已沈積材料就是一種可被生長在矽之上的材料以及STI 502之絕緣材料。假如閘極電介質700為熱氧化物，則STI 502之上的閘極電介質700之部分將不存在。
接下來，導電閘極材料702被沈積。於一範例中，導電閘極材料702為多或非晶矽，其可被實施以減少電阻並設定閘極工作函數。亦可使用其他的導電閘極材料，諸如金屬。
於其他範例實施例中，閘極堆疊亦可為高k、金屬閘極(HKMG)堆疊。例如，可使用諸如氮化鈦之金屬閘極，其具有高k閘極電介質，諸如二氧化鉿(HfO2)、二氧化鋯(ZrO2)、或二氧化鈦(TiO2)。HKMG堆疊可被形成以一種電介質先、閘極先、電介質後、或閘極後程序。
例如，於電介質後HKMG程序中，閘極堆疊可被初始 地形成如傳統的二氧化矽與多晶矽堆疊，其被使用為直線處理之前端期間的犧牲堆疊。接著，在進行至直線處理的後端之前，此犧牲堆疊之一部分可被移除並取代以一包括高k電介質和金屬閘極之閘極堆疊。此亦為閘極後HKMG程序之範例。
於閘極後HKMG程序之另一範例中，閘極電介質可被形成以高k材料(具有或沒有傳統電介質)及用於閘極材料之多晶矽。接著，在進行至直線處理的後端之前，多晶矽閘極將被移除並取代以金屬閘極。先前在直線處理之前端所沈積的閘極電介質將保留。此亦為電介質先HKMG程序之範例。
於閘極先、電介質先HKMG程序中，高k閘極電介質和金屬閘極兩者均被形成於直線處理之前端期間。
在閘極堆疊被沈積之後，硬遮罩層704被沈積並圖案化。圖案化的硬遮罩可被用以蝕刻導電閘極材料702及選擇性地閘極電介質700。剩餘的閘極堆疊材料形成閘極706。通道708為幾乎由閘極706所覆蓋之鰭片結構500中的區。源極和汲極710係位於鄰接通道708之鰭片結構500的任一端。於一種如所描述之離散裝置中，源極和汲極係由於其為可互換而被一起描述。
於其他程序中，假如使用光抗蝕劑遮罩以圖案化閘極706則可省略硬遮罩。閘極電介質亦可於整個晶圓上被保留為未蝕刻。其可被移除(例如)於參考圖8A-8C所描述之間隔物蝕刻步驟中。
參考圖3，於操作306中，源極/汲極區之部分或全部被蝕刻而保留鰭片結構之閘極底下的通道區。於此操作之一範例中，閘極硬遮罩(連同一間隔物)可被使用為用於源極/汲極蝕刻之遮罩。圖8A-8C描繪在間隔物800之形成以及源極和汲極710(圖7A)之蝕刻以移除那些區中之鰭片結構500後的基底400。間隔物800之形成可從一絕緣間隔物材料之沈積於基底400上開始。可接著執行一包覆層(blanket)間隔物蝕刻。閘極706之側壁上的間隔物絕緣材料將被保護不被蝕刻。在蝕刻已完成(例如)一設定的時間或結束點之後，間隔物800將保留。此外，留存在閘極圖案化後之晶圓上的硬遮罩層704仍可在蝕刻掉間隔物絕緣材料之後保留。硬遮罩層704和間隔物800可接著被使用為遮罩以蝕刻源極和汲極710(圖7A)。在源極和汲極蝕刻之後，來自源極和汲極710(圖7A)之大部分或全部的矽被移除，留下鰭片結構500之通道708。
操作306亦可省略間隔物相關的操作。操作306之此版本僅可使用硬遮罩來蝕刻源極和汲極區。於操作306之其他範例中，可使用光抗蝕劑遮罩以取代硬遮罩。
參考圖3，於操作308中，操作306中所蝕刻之源極和汲極的部分被再填入以矽。圖10A-10C描繪在已蝕刻的源極和汲極710(圖7A)已被再填入以矽1000之後的基底400。此可(例如)藉由沈積多晶矽或生長外延矽來完成。假如通道708之側壁已於源極和汲極蝕刻期間受損，則側壁可選擇性地被準備以接收新的矽，藉由(例如)熱 氧化側壁以消耗受損的矽。即使源極和汲極710(圖7A)為矽，亦可使用其他的半導體來再填入該些區。於此情況下，通道區以及源極和汲極區將由不同的材料所製。
參考圖3，於操作310，其係與操作308同時地發生，源極和汲極被原位摻雜而同時被再填入矽。參考圖10A-10C，藉由在沈積或生長矽1000之同時執行摻雜，則可避免傾角及電漿植入。此外，因為原位摻雜容許橫越矽1000之恆定厚摻雜，所以相較於單獨的摻雜可減少源極和汲極電阻。亦可避免與啟動任何源極和汲極植入相關的熱步驟。
假如使用包覆層沈積或生長，則可能需要一額外的步驟以從非源極和非汲極區域移除矽。可使用CMP或蝕刻回(有或沒有遮掩步驟)以從其應為非導電之區移除矽(例如，移除其可能使源極和汲極短路之任何矽)。例如，如圖10A-10C中所描繪，矽1000(其被沈積以再填入先前蝕刻的源極和汲極710(圖7A))已被蝕刻回以致閘極706之頂部被暴露且源極和汲極未被一同短路。
雖然圖10A-10C之矽1000被描繪以一特定的陰影，但矽1000之結晶結構亦可橫越裝置而改變。例如，假如矽1000係以外延程序來產生，則源極和汲極區中之矽1000的部分可為結晶的，而在STI上方之矽1000的部分可為多晶的。對於矽1000之單一陰影的使用並非為了表示其矽1000具有均勻的結晶結構或者必須具有其他均勻的特徵。
另一方面，可使用選擇性外延生長以生長矽僅在暴露的矽之上(例如，在操作306中之源極和汲極的移除後所暴露之晶圓和鰭片的矽部分)而不在其他材料之上(例如STI絕緣體)。圖9A-9C描繪在選擇性地生長矽900以再填入已蝕刻的源極和汲極710(圖7A)之後的基底400。利用選擇性外延，可能不需要蝕刻回步驟。圖9A-9C係相反於圖10A-10C，其描繪在非選擇性生長及蝕刻回步驟之後的基底400。圖9A-9C中之源極和汲極900的形狀僅為了示範藉由使用選擇性外延以再生長源極和汲極區所產生的形狀。亦可產生源極和汲極區之其他形狀而不背離本發明之範例實施例。
為了控制熱預算，一開始，可使用高溫外延程序以生長高品質矽的初始厚度。接著可用較低溫度沈積多晶矽以再填入更多的源極和汲極。亦可使用CMP、蝕刻回、或兩者以使晶圓平坦化。此外，可能需要蝕刻回以從非源極和非汲極區移除矽，如先前所述者。
雖然圖9A-9C及10A-10C描繪其已蝕刻的源極和汲極被完全地再填入矽，但於其他情況下，僅有源極和汲極之一部分需被再填入矽。
除了產生低電阻的源極和汲極之外，源極和汲極710(圖7A)之取代亦可能增加應變至通道708(圖10A)。例如，可利用選擇性外延以生長SiGe或SiC(假如使用矽基底的話)於其中源極和汲極區已被蝕刻掉的通道708(圖10A)之側邊上。相較於Si(或其他形成通道之半導體 材料)之SiGe或SiC的不同晶格常數可能使通道708中之半導體形變，其可能增加通道708中之電子或電洞的移動率。
雖然係參考數個處理步驟以描述第一範例程序，但那些熟悉本項技術人士應理解亦將需要其他眾所周知的處理步驟以產生有作用的鰭片式場效電晶體。例如，可能需要臨限值調整植入以適當地設定n型或p型鰭片式場效電晶體之臨限電壓。當作另一範例，透過矽之沈積或外延生長的源極和汲極之再填入可能需被執行兩次：一次針對需要p型源極和汲極之p型鰭片式場效電晶體及一次針對需要n型源極和汲極之n型鰭片式場效電晶體。
圖11A-11C描繪基底1100上之鰭片式場效電晶體的另一範例實施例。此範例實施例係類似於圖10A-10C中所描繪之範例實施例，除了一SOI晶圓被用於基底1100以取代如上所述之大塊晶圓。同時，用於此範例實施例之程序不包括STI區之形成。圖11A-11C中之源極和汲極1102的形狀僅為了示範藉由使用選擇性外延以再生長源極和汲極區所產生的形狀。亦可產生源極和汲極區之其他形狀而不背離本發明之實施例。
圖12A-12C描繪利用具有不同材料性質之非對稱源極1200和汲極1202之鰭片式場效電晶體的範例實施例。例如，源極1200和汲極1202可由不同材料所製。當作另一範例，兩區之摻雜可為不同的。於又另一範例中，兩區之應變可為不同的。此範例實施例需要源極1200和汲極 1202被分離地生長。圖12A-12C中之源極1200和汲極1202的形狀僅為了示範藉由使用選擇性外延以再生長源極和汲極區所產生的形狀。亦可產生源極和汲極區之其他形狀而不背離本發明之實施例。
圖13A-13C描繪另一範例程序之一階段。此範例程序類似於範例程序300(圖3)，除了其以上參考圖5A-5C所描述之STI蝕刻回步驟被稍後執行於此程序中。圖13A-13C描繪在鰭片結構1306之形成(操作302中所描述者)、STI 1304之沈積(參考圖5A-5C所描述者)、及源極汲極1302之蝕刻和再填入(操作306、308、及310中所描述者)以後的基底1300。然而，STI 1304之蝕刻回尚未發生。STI蝕刻回步驟(參考圖5A-5C所描述者)係發生於閘極形成(操作304)前之某時刻。基底1300被描繪為SOI晶圓；然而，此程序亦可被用於大塊晶圓上。
圖14A-14C描繪用於鰭片式場效電晶體之製造的另一範例程序之一階段。此範例程序類似於範例程序300(圖3)，除了其源極和汲極蝕刻及再填入(操作306、308、及310中所描述者)係發生於鰭片結構之形成(操作302中所描述者)以前。於此程序中，可使用標準的抗蝕劑遮罩以蝕刻掉源極和汲極1402於再填入之前。此外，只有將形成源極和汲極1402之矽被蝕刻及再填入。區1404保持為未蝕刻且為基底1400之原始頂部表面。此範例程序中之後續階段形成一鰭片結構，如以上參考操作302所述者。基底1400被描繪為SOI晶圓；然而，此程序亦可被 使用以大塊晶圓。
圖15A-15C描繪用於鰭片式場效電晶體之製造的另一範例程序之一階段。此範例程序類似於參考圖14A-14C所描述者，除了在源極和汲極1502被蝕刻並再填入之外，於源極和汲極1502周圍之區域1504亦被蝕刻並再填入。僅有區1506保持為基底1500之原始頂部表面。此範例程序中之後續階段形成一鰭片結構，如以上參考操作302所述者。基底1500被描繪為SOI晶圓；然而，此程序亦可被使用以大塊晶圓。
雖然圖15A-15C之源極和汲極1502及源極和汲極1502周圍的區域1504被描繪以一特定陰影，但這些區域之結晶結構可隨著其已針對說明和描述之目的而提呈之本發明的特定實施例之以上描述而改變。其並非為了詳盡或限制本發明於所揭示的精確形式，而應理解根據上述教導可能有許多修改及變化。例如，假如係使用外延以再生長矽於這些區域中，則鄰接區1506之矽可為結晶的而較遠離區1506之矽可為多晶的。單一陰影之使用並非為了表示其這些區域具有均勻的結晶結構或者必須具有其他均勻的特徵。
本發明之特定實施例的以上描述已被提呈以供說明和描述之目的。其並非為了詳盡或限制本發明於所揭示的精確形式，而應理解根據上述教導可能有許多修改及變化。
100‧‧‧鰭片式場效電晶體
102‧‧‧鰭片結構
104‧‧‧閘極堆疊
106‧‧‧淺溝槽隔離(STI)
108‧‧‧氧化物層
200‧‧‧金氧半導體場效電晶體
202‧‧‧矽區
204‧‧‧閘極堆疊
206‧‧‧STI
208‧‧‧氧化物層
400‧‧‧基底
402‧‧‧平面
404‧‧‧平面
500‧‧‧鰭片結構
502‧‧‧STI
504‧‧‧頂部
506‧‧‧頂部
600‧‧‧頂部部分
602‧‧‧底部部分
700‧‧‧閘極電介質
702‧‧‧導電閘極材料
704‧‧‧硬遮罩層
706‧‧‧閘極
708‧‧‧通道
710‧‧‧源極和汲極
800‧‧‧間隔物
900‧‧‧矽
1000‧‧‧矽
1100‧‧‧基底
1102‧‧‧源極和汲極
1200‧‧‧源極
1202‧‧‧汲極
1300‧‧‧基底
1302‧‧‧源極和汲極
1304‧‧‧STI
1306‧‧‧鰭片結構
1400‧‧‧基底
1402‧‧‧源極和汲極
1404‧‧‧區
1500‧‧‧基底
1502‧‧‧源極和汲極
1504‧‧‧區域
1506‧‧‧區
本案可藉由參考其配合後附圖形所提供之下列描述而被最佳地瞭解，其中類似的部件可被指稱以類似的數字。
圖1描繪一鰭片式場效電晶體。
圖2描繪一SOI MOSFET。
圖3描繪一用以形成鰭片式場效電晶體之範例程序的流程圖。
圖4A描繪一鰭片式場效電晶體之範例實施例的透視圖，於依據圖3中所描繪之範例程序的初始製造階段。
圖4B描繪沿著圖4A中之點切平面402的範例實施例之橫斷面視圖。
圖4C描繪沿著圖4A中之點切平面404的範例實施例之橫斷面視圖。
圖5A-5C；6A-6C；7A-7C；8A-8C；9A-9C；及10A-10C描繪於依據圖3中所描繪之範例程序的各個製造階段之範例實施例。
圖11A-11C描繪於SOI晶圓上之鰭片式場效電晶體的範例實施例。
圖12A-12C描繪具有非對稱源極和汲極區之鰭片式場效電晶體的範例實施例。
圖13A-13C描繪用以製造鰭片式場效電晶體之另一範例程序的一階段。
圖14A-14C描繪用以製造鰭片式場效電晶體之另一範例程序的一階段。
圖15A-15C描繪用以製造鰭片式場效電晶體之另一範 例程序的一階段。
上述圖形係描繪本發明之各個實施例以僅供說明之目的。熟悉本項技術人士將從下列討論輕易理解：此處所說明之結構和方法的替代實施例可被應用而不背離此處所述之本發明的原理。

Claims (18)

  1. 一種用以製造鰭片式場效電晶體(finFET)之方法，該鰭片式場效電晶體具有一包括源極區、汲極區和介於該些源極與汲極區之間的通道區之鰭片，該方法包含：蝕刻該鰭片於一半導體基底上；形成一閘極堆疊於該通道區上，該閘極堆疊具有一與該通道區直接接觸之絕緣層及一與該絕緣層直接接觸之閘極材料；蝕刻該些源極和汲極區以留下該通道區；生長外延半導體於其鄰接該些源極和汲極區之該通道區的側邊上，以個別地形成源極外延區和汲極外延區；及原位摻雜該外延半導體而同時生長該外延半導體。
  2. 如申請專利範圍第1項之方法，進一步包含：沈積一隔離層於該鰭片周圍及該鰭片上；及拋光該隔離層以具有與該鰭片之表面近乎共面的頂部表面。
  3. 如申請專利範圍第2項之方法，其中沈積一隔離層及拋光該隔離層之該步驟係發生於形成該閘極堆疊之前。
  4. 如申請專利範圍第3項之方法，進一步包含：蝕刻回該隔離層以致該鰭片之頂部部分被暴露而該隔離仍覆蓋該鰭片之底部部分。
  5. 如申請專利範圍第1項之方法，其中蝕刻該源極和汲極及生長該外延半導體係發生於蝕刻該鰭片之前。
  6. 如申請專利範圍第1項之方法，其中該通道區具有 本質應變，其中該源極外延區具有第一應變，且其中該源極外延區之該第一應變係修改該通道區之至少一部分的該本質應變以增進該通道區中之電子或電洞的移動率。
  7. 如申請專利範圍第1項之方法，其中該半導體基底為大塊矽晶圓。
  8. 如申請專利範圍第1項之方法，其中該汲極外延區為與該半導體晶圓不同的材料。
  9. 如申請專利範圍第1項之方法，其中該外延半導體被選擇性地生長為該半導體基底之材料。
  10. 如申請專利範圍第1項之方法，進一步包含：移除該閘極堆疊之一部分；及形成一金屬閘極於該通道區之上。
  11. 如申請專利範圍第10項之方法，進一步包含：在形成該金屬閘極於該通道區之上以前，沈積一電介質層於該通道區上。
  12. 一種位於半導體基底上之鰭片式場效電晶體，該鰭片式場效電晶體包含：一通道區，其具有突出自該半導體基底之第一側及與該第一側相反並突出自該半導體基底之第二側；一位於該通道區上方之閘極堆疊，其中該閘極堆疊包括一直接接觸該通道區之該些第一和第二側的絕緣層，及其中該閘極堆疊包括一直接接觸該絕緣層之導電閘極材料；一半導體外延地生長於該通道區上之源極外延區，其 中該源極外延區被原位摻雜；及一遠離該源極外延區而半導體外延地生長於該通道區上之汲極外延區，其中該汲極外延區被原位摻雜。
  13. 如申請專利範圍第12項之鰭片式場效電晶體，其中該通道區具有本質應變，其中該些源極和汲極外延區具有第一應變，及其中該些源極和汲極外延區之該第一應變係修改該通道區之至少一部分的該本質應變以增進該通道區中之電子或電洞的移動率。
  14. 如申請專利範圍第12項之鰭片式場效電晶體，其中該半導體基底為大塊矽晶圓。
  15. 如申請專利範圍第12項之鰭片式場效電晶體，其中該汲極外延區為與該半導體晶圓不同的材料。
  16. 如申請專利範圍第12項之鰭片式場效電晶體，其中該源極外延區與該汲極外延區具有不同的材料性質。
  17. 如申請專利範圍第12項之鰭片式場效電晶體，其中該閘極材料為金屬。
  18. 如申請專利範圍第12項之鰭片式場效電晶體，其中該絕緣材料包含鉿。
TW101123719A 2011-07-27 2012-07-02 替換源極／汲極鰭片式場效電晶體（ｆｉｎｆｅｔ）之製造方法 TW201318077A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10403626B2 (en) 2014-03-24 2019-09-03 Intel Corporation Fin sculpting and cladding during replacement gate process for transistor channel applications

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8561003B2 (en) 2011-07-29 2013-10-15 Synopsys, Inc. N-channel and P-channel finFET cell architecture with inter-block insulator
US8595661B2 (en) * 2011-07-29 2013-11-26 Synopsys, Inc. N-channel and p-channel finFET cell architecture
US9099388B2 (en) * 2011-10-21 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. III-V multi-channel FinFETs
KR101805634B1 (ko) * 2011-11-15 2017-12-08 삼성전자 주식회사 Ⅲ-ⅴ족 배리어를 포함하는 반도체 소자 및 그 제조방법
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
CN103811340B (zh) * 2012-11-09 2017-07-14 中国科学院微电子研究所 半导体器件及其制造方法
US9064077B2 (en) 2012-11-28 2015-06-23 Qualcomm Incorporated 3D floorplanning using 2D and 3D blocks
US9098666B2 (en) 2012-11-28 2015-08-04 Qualcomm Incorporated Clock distribution network for 3D integrated circuit
US8853025B2 (en) * 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9536840B2 (en) 2013-02-12 2017-01-03 Qualcomm Incorporated Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
US9041448B2 (en) 2013-03-05 2015-05-26 Qualcomm Incorporated Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
US9177890B2 (en) * 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
US9299840B2 (en) 2013-03-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9171608B2 (en) 2013-03-15 2015-10-27 Qualcomm Incorporated Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
KR102017625B1 (ko) * 2013-05-10 2019-10-22 삼성전자주식회사 반도체 장치 및 그 제조방법
US9385233B2 (en) * 2013-06-26 2016-07-05 Globalfoundries Inc. Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
US9349730B2 (en) 2013-07-18 2016-05-24 Globalfoundries Inc. Fin transformation process and isolation structures facilitating different Fin isolation schemes
US9224865B2 (en) 2013-07-18 2015-12-29 Globalfoundries Inc. FinFET with insulator under channel
US9716174B2 (en) 2013-07-18 2017-07-25 Globalfoundries Inc. Electrical isolation of FinFET active region by selective oxidation of sacrificial layer
US9093496B2 (en) 2013-07-18 2015-07-28 Globalfoundries Inc. Process for faciltiating fin isolation schemes
US9105707B2 (en) 2013-07-24 2015-08-11 International Business Machines Corporation ZRAM heterochannel memory
US10147793B2 (en) 2013-07-30 2018-12-04 Samsung Electronics Co., Ltd. FinFET devices including recessed source/drain regions having optimized depths
US9685509B2 (en) 2013-07-30 2017-06-20 Samsung Electronics Co., Ltd. Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions
US9048262B2 (en) * 2013-09-20 2015-06-02 International Business Machines Corporation Multi-fin finFETs with merged-fin source/drains and replacement gates
KR102105363B1 (ko) 2013-11-21 2020-04-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9716176B2 (en) 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
EP2889906B1 (en) * 2013-12-30 2019-02-20 IMEC vzw Improvements in or relating to electrostatic discharge protection
US9087900B1 (en) 2014-01-07 2015-07-21 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
KR102157839B1 (ko) * 2014-01-21 2020-09-18 삼성전자주식회사 핀-전계효과 트랜지스터의 소오스/드레인 영역들을 선택적으로 성장시키는 방법
JP6361180B2 (ja) * 2014-03-10 2018-07-25 富士通セミコンダクター株式会社 半導体装置の製造方法
KR102017611B1 (ko) 2014-04-04 2019-09-04 삼성전자주식회사 반도체 장치 및 그 제조방법
CN105097535B (zh) * 2014-05-12 2018-03-13 中国科学院微电子研究所 FinFet器件的制造方法
US9209305B1 (en) * 2014-06-06 2015-12-08 Stmicroelectronics, Inc. Backside source-drain contact for integrated circuit transistor devices and method of making same
US9406522B2 (en) 2014-07-24 2016-08-02 Applied Materials, Inc. Single platform, multiple cycle spacer deposition and etch
US9818877B2 (en) 2014-09-18 2017-11-14 International Business Machines Corporation Embedded source/drain structure for tall finFET and method of formation
US10559690B2 (en) 2014-09-18 2020-02-11 International Business Machines Corporation Embedded source/drain structure for tall FinFET and method of formation
US9660059B2 (en) 2014-12-12 2017-05-23 International Business Machines Corporation Fin replacement in a field-effect transistor
KR102310080B1 (ko) * 2015-03-02 2021-10-12 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9343300B1 (en) * 2015-04-15 2016-05-17 Globalfoundries Inc. Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
US9748364B2 (en) * 2015-04-21 2017-08-29 Varian Semiconductor Equipment Associates, Inc. Method for fabricating three dimensional device
US9741829B2 (en) * 2015-05-15 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9437496B1 (en) 2015-06-01 2016-09-06 Globalfoundries Inc. Merged source drain epitaxy
KR102395073B1 (ko) 2015-06-04 2022-05-10 삼성전자주식회사 반도체 소자
US9601621B1 (en) * 2015-08-25 2017-03-21 International Business Machines Corporation Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
US10050043B2 (en) 2016-01-29 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory (SRAM) using FinFETs with varying widths of fin structures
US9634084B1 (en) 2016-02-10 2017-04-25 Globalfoundries Inc. Conformal buffer layer in source and drain regions of fin-type transistors
US9865589B1 (en) * 2016-10-31 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of fabricating ESD FinFET with improved metal landing in the drain
US10008603B2 (en) * 2016-11-18 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and method of fabrication thereof
US10763116B2 (en) * 2017-10-30 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure
US10373912B2 (en) 2018-01-05 2019-08-06 International Business Machines Corporation Replacement metal gate processes for vertical transport field-effect transistor
US10529831B1 (en) 2018-08-03 2020-01-07 Globalfoundries Inc. Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging
US10714399B2 (en) 2018-08-21 2020-07-14 International Business Machines Corporation Gate-last process for vertical transport field-effect transistor
US10672905B2 (en) 2018-08-21 2020-06-02 International Business Machines Corporation Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts
US10672670B2 (en) 2018-08-21 2020-06-02 International Business Machines Corporation Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages
JP7000568B2 (ja) * 2019-06-21 2022-01-19 株式会社日立ハイテク プラズマ処理方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7355233B2 (en) * 2004-05-12 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for multiple-gate semiconductor device with angled sidewalls
US6979622B1 (en) * 2004-08-24 2005-12-27 Freescale Semiconductor, Inc. Semiconductor transistor having structural elements of differing materials and method of formation
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
JP2007250665A (ja) * 2006-03-14 2007-09-27 Toshiba Corp 半導体装置及びその製造方法
US7709312B2 (en) 2006-09-29 2010-05-04 Intel Corporation Methods for inducing strain in non-planar transistor structures
KR100836761B1 (ko) * 2006-12-08 2008-06-10 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조방법
KR100832721B1 (ko) * 2006-12-27 2008-05-28 동부일렉트로닉스 주식회사 씨모스 이미지 센서의 제조방법
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US8450165B2 (en) * 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US8601973B2 (en) 2007-09-01 2013-12-10 Nanosolar, Inc. Solution deposition assembly
US8247312B2 (en) 2008-04-24 2012-08-21 Innovalight, Inc. Methods for printing an ink on a textured wafer surface
DE102008049719A1 (de) * 2008-09-30 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Asymmetrische Transistorbauelemente, die durch asymmetrische Abstandshalter und eine geeignete Implantation hergestellt sind
US7615393B1 (en) 2008-10-29 2009-11-10 Innovalight, Inc. Methods of forming multi-doped junctions on a substrate
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices
US20100207175A1 (en) * 2009-02-16 2010-08-19 Advanced Micro Devices, Inc. Semiconductor transistor device having an asymmetric embedded stressor configuration, and related manufacturing method
US8497528B2 (en) * 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8334184B2 (en) * 2009-12-23 2012-12-18 Intel Corporation Polish to remove topography in sacrificial gate layer prior to gate patterning
US8900936B2 (en) * 2011-01-31 2014-12-02 International Business Machines Corporation FinFET device having reduce capacitance, access resistance, and contact resistance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10403626B2 (en) 2014-03-24 2019-09-03 Intel Corporation Fin sculpting and cladding during replacement gate process for transistor channel applications

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