CN105097535B - FinFet器件的制造方法 - Google Patents

FinFet器件的制造方法 Download PDF

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CN105097535B
CN105097535B CN201410199311.5A CN201410199311A CN105097535B CN 105097535 B CN105097535 B CN 105097535B CN 201410199311 A CN201410199311 A CN 201410199311A CN 105097535 B CN105097535 B CN 105097535B
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刘金彪
王垚
王桂磊
杨涛
刘青
李俊峰
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Abstract

本发明提供了一种FinFet器件的制造方法，包括：提供衬底；对衬底进行源漏掺杂；刻蚀掺杂后的衬底，以形成源区和漏区；在源区和漏区之间形成鳍沟道；在鳍沟道上形成栅极。本发明在衬底上进行完源漏掺杂之后，才进行鳍以及栅极的形成，使得源漏掺杂如同平面器件的掺杂，保证了源漏掺杂的质量，提高了FinFet器件的性能。

Description

FinFet器件的制造方法
技术领域
本发明涉及半导体制造领域，特别涉及一种FinFet器件的制造方法。
背景技术
随着平面半导体器件的尺寸不断缩小，短沟道效应愈发突出，提高栅控能力成为下一代器件的开发中的重点方向，类似FinFet(鳍式场效应晶体管)的多栅器件，FinFet是具有鳍型沟道结构的晶体管，它利用薄鳍(Fin)的几个表面作为沟道，可以增大工作电流，从而可以防止传统晶体管中的短沟道效应。
在FinFet器件的实际制备过程中，一个重要的挑战就是FinFet源漏掺杂区的制备，在平面器件当中，离子都直接注入到平面器件表面，在通过退火进行激活，掺杂浓度分布较为均匀。而FinFet源漏注入时，要求在Fin的顶部和侧墙部分同时注入并获得近似相同的浓度分布即共型掺杂，为了实现这个目的，一般多尝试采用大角度注入或是等离子体掺杂的方法。
然而，传统的大角度注入会受到Fin的间距较小而带来的阴影效应的影响，而导致不均匀掺杂，鳍的侧面的掺杂浓度较顶部小。等离子体掺杂尽管能实现均匀的掺杂，但由于不能进行质量筛选，又有可能会引入其他缺陷，影响器件的特性。
发明内容
本发明的目的旨在解决上述技术缺陷，提供一种FinFet器件的制造方法，实现共型掺杂。
为此，本发明提供了一种FinFet器件的制造方法，包括：
提供衬底；
对衬底以平面半导体器件掺杂方式进行源漏掺杂；
刻蚀掺杂后的衬底，以形成源区和漏区；
在源区和漏区之间形成鳍沟道；
在所述鳍沟道上形成栅极。
可选的，在源区和漏区之间形成鳍的步骤具体包括：
在源区和漏区之外的衬底上形成介质层；
进行平坦化，直至暴露源区和漏区；
刻蚀源区和漏区之间的介质层，以在介质层中形成鳍沟道区；
在鳍沟道区内形成鳍沟道；
至少去除部分厚度的介质层。
可选的，通过选择性外延生长在鳍沟道区内形成鳍沟道。
可选的，去除部分厚度的介质层，剩余的介质层为隔离结构。
可选的，通过离子注入或外延掺杂的方式对衬底进行源漏掺杂。
可选的，源漏掺杂的浓度大于1e20cm-3。可选的，
本发明实施例提供的FinFet器件的制造方法，在衬底上进行完源漏掺杂之后，才进行鳍以及栅极的形成，使得源漏掺杂如同平面器件的掺杂，保证了源漏掺杂的质量，提高了FinFet器件的性能。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1示出了根据本发明实施例的FinFet器件的制造方法的流程图；
图2-图8示出了根据本发明实施例的FinFet器件的各个形成阶段的立体示意图；
图9为图8中沿栅极方向的截面示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
在附图中示出了根据本发明实施例的层结构示意图。这些图并非是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
正如背景技术的描述，为了达到FinFet器件离子注入的共型掺杂，本发明提出了一种FinFet器件的制造方法，参考图1所示，包括步骤：
提供衬底；
对衬底进行源漏掺杂；
刻蚀掺杂后的衬底，以形成源区和漏区；
在源区和漏区之间形成鳍；
在所述鳍上形成栅极。
在本发明中，在衬底上进行完源漏掺杂之后，才进行鳍以及栅极的形成，使得源漏掺杂如同平面器件的掺杂，保证了源漏掺杂的质量，提高了FinFet器件的性能。
为了更好的理解本发明，以下将结合具体的实施例进行详细的描述。
首先，在步骤S01，提供半导体衬底，如图2所示。
在本发明中，所述半导体衬底可以为Si衬底、Ge衬底、SiGe衬底等体衬底。在本实施例中，所述衬底为体硅衬底。
而后，对衬底进行源漏掺杂，参考图2所示。
在对衬底进行掺杂时，可以采用平面器件进行源漏掺杂的方法，例如可以采用离子注入的方法或外延掺杂等方法进行掺杂。
在本实施例中，通过根据期望的晶体管结构，注入p型或n型掺杂物或杂质到所述衬底中，源漏掺杂的浓度大于1e20cm-3，而后进行退火来实现掺杂。在其他实施例中，可以通过在衬底上进行外延掺杂来实现。
接着，刻蚀掺杂后的衬底，以形成源区102和漏区104，如图3所示。
在本实施例中，具体地，首先，在掺杂后的衬底上形成图案化硬掩膜，例如氮化硅；而后，在硬掩膜的掩蔽下，利用刻蚀技术，例如RIE(反应离子刻蚀)的方法，进一步刻蚀衬底，从而形成源区和漏区；最后，将硬掩膜去除。
而后，在源区102和漏区104之间形成鳍沟道区108，如图5所示。
在本实施例中，具体地，首先，淀积介质材料，例如未掺杂的氧化硅(SiO2)、掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)、氮化硅(Si3N4)或其他低k介质材料；而后，进行平坦化，例如CMP(化学机械抛光)，直至暴露源区102和漏区104，从而，在衬底上形成介质层106，如图4所示；接着，进行掩膜，刻蚀源区和漏区之间的介质层，直到暴露衬底100，以在介质层中形成鳍沟道区108，如图5所示，该鳍沟道区用于形成鳍沟道；而后，在鳍沟道区中形成鳍沟道，如图6所示，可以通过选择性外延生长的方法在沟道区内形成鳍沟道；而后，去除部分厚度的介质层106，暴露出鳍沟道110，剩余的介质层为器件间的隔离结构112，如图7所示。当然，在其他实施例中，也可以将介质层全部去除，而后重新形成隔离结构。
接着，在鳍沟道上形成栅极，如图8、图9所示。
形成栅极的步骤同传统的鳍式器件形成栅的步骤，可以通过分别淀积栅介质层114、栅电极116和帽层(图未示出)，而后利用刻蚀技术进行刻蚀，以在鳍的沟道区域的侧壁及顶部上形成栅极，如图8所示。其中，所述栅介质层114可以为一层或多层结构，一层结构的一些实施例中，栅介质层可以为高k介质材料(例如，和氧化硅相比，具有高介电常数的材料)或其他栅介质材料，多层结构的一些实施例中，栅介质层可以包括界面层和高k介质材料，所述界面层可以为氧化硅、氮化硅、氮氧化硅或其他材料，高k介质材料例如铪基氧化物，HFO2、HfSiO、HfSiON、HfTaO、HfTiO等。所述栅电极116可以为一层或多层结构，栅电极可以包括金属栅电极或多晶硅，例如可以包括：Ti、TiAlx、TiN、TaNx、HfN、TiCx、TaCx、HfCx、Ru、TaNx、TiAlN、WCN、MoAlN、RuOx、多晶硅或其他合适的材料，或他们的组合。此处仅为示例，本发明不限于此。
而后，形成器件的其他结构，如形成侧墙、接触以及互连结构等。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (6)

1.一种FinFet器件的制造方法，其特征在于，包括：
提供半导体衬底；
对衬底以平面半导体器件掺杂方式进行源漏掺杂；
刻蚀掺杂后的衬底，以形成源区和漏区；
在源区和漏区之间形成鳍沟道；
在鳍沟道上形成栅极。
2.根据权利要求1所述的制造方法，其特征在于，在源区和漏区之间形成鳍沟道的步骤具体包括：
在源区和漏区之外的衬底上形成介质层；
进行平坦化，直至暴露源区和漏区；
刻蚀源区和漏区之间的介质层，以在介质层中形成鳍沟道区；
在鳍沟道区内形成鳍沟道；
至少去除部分厚度的介质层。
3.根据权利要求2所述的制造方法，其特征在于，通过选择性外延生长在鳍沟道区内形成鳍沟道。
4.根据权利要求2所述的制造方法，其特征在于，去除部分厚度的介质层，剩余的介质层为隔离结构。
5.根据权利要求1所述的制造方法，其特征在于，通过离子注入或外延掺杂的方式对衬底进行源漏掺杂。
6.根据权利要求1所述的制造方法，其特征在于，源漏掺杂的浓度大于1e20cm-3。
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US14/402,303 US9590076B1 (en) 2014-05-12 2014-08-01 Method for manufacturing a FinFET device
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