CN105374752B - 一种垂直纳米线晶体管的集成方法 - Google Patents

一种垂直纳米线晶体管的集成方法 Download PDF

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CN105374752B
CN105374752B CN201510701681.9A CN201510701681A CN105374752B CN 105374752 B CN105374752 B CN 105374752B CN 201510701681 A CN201510701681 A CN 201510701681A CN 105374752 B CN105374752 B CN 105374752B
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CN105374752A (zh
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黎明
杨远程
陈珙
樊捷闻
张昊
黄如
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Abstract

本发明公开了一种垂直纳米线晶体管的集成方法，属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域。该方法结合图形化外延和侧壁替代栅以实现垂直纳米线晶体管集成，与现有的通过刻蚀形成垂直纳米线沟道的方法相比，能够精确地控制器件沟道的截面积大小和形貌，提高器件的特性的一致性；避免了现有方法中沟道形成过程中的刻蚀损伤，提高了器件的性能。

Description

一种垂直纳米线晶体管的集成方法
技术领域
本发明属于超大规模集成电路制造技术领域，涉及一种结合图形化外延和侧壁替代栅以实现垂直纳米线晶体管集成的方法。
背景技术
当半导体器件进入22nm技术代后，以鱼鳍型场效应晶体管(FinFET)为代表的水平沟道三维多栅器件(Multi-gate MOSFET,MuGFET)，以其出众的抑制短沟效应能力，高集成密度，与传统CMOS工艺兼容等优点，成为半导体器件的主流。
但是，在向更小尺寸技术节点迈进时，水平沟道三维多栅器件又面临接触孔的间距难以缩小(限制了集成密度的提高)、复杂形貌上的栅刻蚀等挑战。
因此，垂直沟道围栅器件因其具有更高的集成密度、与新型存储器(如RRAM等)混合集成的潜力等优势，而备受关注。
目前，见诸报道的垂直纳米线器件的集成方案主要是B.Yang等提出的基于刻蚀形成沟道的方法[B.Yang et al.,EDL,2008,29(7):791～794]：
该方法在体硅衬底上通过刻蚀形成了直径20nm，高宽比大于50:1的垂直沟道，并通过注入形成器件的源漏，使用传统氧化硅介质和多晶硅栅电极。
但是，如利用该方法形成于更小尺寸的垂直纳米线沟道器件时，则会出现如下问题：
通过刻蚀的方法形成更小直径且大高宽比的垂直沟道，其本身对刻蚀工艺提出很大挑战，且刻蚀形成的沟道截面形貌难以控制，造成器件特性一致性的退化；刻蚀造成的沟道损伤，引起器件性能的进一步退化；
该方法形成的器件上有源区为刻蚀形成的垂直纳米线的一部分，其截面积随器件尺寸缩小而缩小，因此通过注入的方法在该区域难以进行重掺杂，且器件间该区域的杂质浓度涨落随器件尺寸缩小而增加；
该集成方案难以使用后栅工艺，限制了器件性能的提升；
因此，业界急需一种实现小尺寸垂直沟道纳米线晶体管的集成方法。
发明内容
针对以上问题，本发明提供一种结合图形化外延和侧壁替代栅的垂直纳米线晶体管集成方法，以改善现有的公知技术，如图1所示，包括如下步骤：
A.提供一半导体衬底，并形成器件之间的隔离；
B.形成器件的重掺杂的下有源区，该下有源区即垂直晶体管的下方的源端(或漏端)；
C.淀积假栅叠层；
具体实现步骤如下：
C1.淀积一层介质作SDE掩膜层1，其厚度定义了器件的源漏延伸区SDE(即LDD)的长度；
C2.淀积一层介质作假栅层，其厚度定义了器件的沟道长度Lg；
C3.淀积一层介质作SDE掩膜层2，其厚度定义了器件的源漏延伸区SDE(即LDD)的长度；
其中，SDE掩膜层1与SDE掩膜层2的材料相同，与假栅层材料相异。并且要求假栅层材料对SDE掩膜层1的各向同性刻蚀选择比大于5:1，以保证在F4中通过各向同性刻蚀去除假栅层时不损伤SDE掩膜层1与SDE掩膜层2；
D.通过图形化外延形成沟道；
具体实现步骤如下：
D1.通过光刻定义沟道外延窗口，其大小、形状决定了器件沟道截面的大小、形状；
D2.通过各向异性刻蚀形成沟道外延窗口，窗口底部露出器件的重掺杂下有源区；
D3.通过外延形成器件的沟道，并通过CMP去除超出SDE掩膜层2上表面的外延沟道材料，实现平坦化；
E.通过图形化外延形成器件的重掺杂的上有源区，该上有源区即垂直晶体管上方的漏端(或源端)；
具体实现步骤如下：
E1.淀积一层介质作硬掩膜，通过光刻、各向异性刻蚀露出NMOS的沟道；
E2.通过原位掺杂外延形成NMOS的重掺杂上有源区；
E3.去除硬掩膜；
E4.淀积一层介质作硬掩膜，通过光刻、各向异性刻蚀露出PMOS的沟道；
E5.通过原位掺杂外延形成PMOS的重掺杂上有源区；
E6.去除硬掩膜；
E7.通过退火工艺激活源漏杂质，并使源漏杂质扩散进入SDE区形成LDD；
其中，E1与E4中所述硬掩膜材料与SDE掩膜层2的材料不同，且要求该硬掩膜材料对SDE掩膜层2的材料和外延沟道材料的各向异性刻蚀选择比大于5:1，以保证在通过各向异性刻蚀去除该硬掩膜时，不损伤SDE掩膜层2与外延沟道；
F.去除假栅，淀积HKMG并形成栅电极；
具体实现步骤如下：
F1.淀积一层介质作顶部掩膜层；
F2.通过光刻定义栅电极；
F3.通过各向异性刻蚀，露出SDE掩膜层1的上表面；
F4.通过各向同性刻蚀，去除整个假栅层；
F5.依次淀积高K介质(High-K，HK)和金属栅(Metal-Gate，MG)材料；
F6.通过各向异性刻蚀，去除不被顶部掩膜层覆盖的HKMG材料，露出SDE掩膜层1的上表面；
其中，F1中所述顶部掩膜层材料与假栅层不同，并且要求假栅层材料对该顶部掩膜层的各向同性刻蚀选择比大于5:1，以保证在F4中通过各向同性刻蚀去除假栅层时不损伤该顶部掩膜层；F1中所述顶部掩膜层厚度应足够厚，以保证F6中通过各向异性刻蚀，去除不被顶部掩膜层覆盖的HKMG材料，露出SDE掩膜层1的上表面后，在器件的上有源区上该顶部掩膜层仍有剩余；
H.形成器件各端的金属接触；
具体实现步骤如下：
H1.淀积一层介质作层间隔离，并通过CMP实现平坦化；
H2.通过光刻、各向异性刻蚀形成器件各端的接触孔；
H3.在各接触孔中填充金属Metal 0；
H4.通过对金属Metal 0进行CMP，实现器件之间的导电层分离，达到器件隔离的效果；
I.后续按已公开的后端工艺完成器件集成。
进一步地，本发明中所述结构参数(如上有源区和下有源区的厚度及掺杂浓度，SDE掩膜层1、SDE掩膜层2、假栅层的厚度，以及HKMG的材料及厚度等)皆根据具体器件性能要求设定；
进一步地，A中所述半导体衬底，包括体硅衬底，SOI衬底，体锗衬底，GOI衬底，化合物衬底等；
进一步地，A中所述隔离，对于体衬底(体硅、体锗等)，可使用阱隔离加浅槽隔离(Shallow Trench Isolation，STI)；对于SOI、GOI等衬底，可仅使用浅槽隔离；
进一步地，B中所述下有源区可通过注入形成，也可通过图形化的原位掺杂外延形成，优选后者(与注入相比，原位掺杂外延具有更高的杂质浓度，更优化的杂质分布，更小的杂质激活热预算)；
进一步地，B、E中所述上有源区与下有源区，二者中何者作器件源端、何者作器件漏端，并无一定之规，可根据器件性能和后续互联的方便进行设定；
进一步地，D中所述通过外延形成的器件沟道，其材料可与下有源区材料相同(如在重掺杂的Si下有源区上外延形成Si沟道)，也可与下有源区材料不同(如在N+重掺杂的GeSi下有源区上外延形成Si沟道，在P+重掺杂的GeSi下有源区上外延形成Ge沟道)；可以是非掺杂的，也可通过原位掺杂外延或离子注入的方式形成掺杂的沟道；
进一步地，F中所述HKGM材料，要求HK介质与沟道之间、MG与HK之间具有良好的界面特性、良好的热稳定性和化学稳定性，淀积方法优选保形性好的原子层淀积(ALD)；
进一步地，H中所述作为导电层的填充金属Metal 0，要求具备低的电阻率，可选择W、Cu等。
本发明的优点和积极效果如下：
1)与现有的通过刻蚀形成垂直纳米线沟道的方法相比，本发明提出的结合图形化外延和侧壁替代栅的集成方法，能够精确地控制器件沟道的截面积大小和形貌，提高器件的特性的一致性；避免了现有方法中沟道形成过程中的刻蚀损伤，提高了器件的性能；
2)本发明能够灵活实现多种材料沟道或源漏的混合集成，这是现有的通过刻蚀形成垂直纳米线沟道的方法难以做到的；
3)本发明提出的通过原位掺杂外延的方法形成有源区，解决了现有通过注入形成有源区方法中源漏掺杂困难、杂质分布难以控制、源漏杂质激活浓度低等一系列问题，进而提高器件性能；
4)本发明提出的侧壁替代栅(后栅工艺)方案，解决了现有通过刻蚀形成垂直纳米线沟道的方法中难以实现替代栅的问题，提高了器件特性。
附图说明
图1是本发明提出的一种结合图形化外延和侧壁替代栅的垂直纳米线晶体管集成方法的工艺流程示意图。
图2-18为体硅垂直纳米线CMOS器件的各关节工艺的示意图。各图中，(a)为俯视图，(b)为(a)中沿A-A’的剖面图。
其中：
图2形成双阱及STI隔离；
图3通过原位掺杂外延形成器件重掺杂的下有源区；
图4淀积形成假栅叠层；
图5光刻、刻蚀形成沟道的外延窗口；
图6外延形成器件的沟道；
图7CMP进行平坦化；
图8通过原位掺杂外延形成NMOS的重掺杂上有源区；
图9通过原位掺杂外延形成PMOS的重掺杂上有源区；
图10淀积顶部掩膜层；
图11光刻、刻蚀形成栅图形，去除假栅；
图12依次淀积HKMG；
图13通过各向异性刻蚀形成栅电极；
图14淀积隔离层；
图15光刻、刻蚀形成器件各端接触孔；
图16在接触控制填充金属Metal 0；
图17CMP实现器件导电层的隔离；
图18为图2～图17的图例；
图19-23为SOI衬底上混合沟道垂直纳米线CMOS器件的各关节工艺的示意图。各图中，(a)为俯视图，(b)为(a)中沿A-A’的剖面图。
其中：
图19在SOI衬底上外延GeSi形成器件重掺杂下有源区；
图20分别在NMOS的下有源区上形成P型轻掺杂Si沟道，在PMOS的下有源区上形成N型轻掺杂Ge沟道；
图21外延器件的重掺杂GeSi上有源区，并淀积顶部掩膜；
图22形成器件各端的金属接触；
图23为图19～图22的图例。
具体实施方式
下面结合附图和具体实例对本发明进行详细说明。
实施例1：
根据下列步骤可以实现直径6nm的体硅垂直纳米线器件的CMOS集成(其结构参数根据ITRS-2013中“11/10nm”技术代的High-Performance器件进行设定)：
1)在(100)体硅衬底上按已公开的体硅工艺形成双阱(N well/P well)、SiO2的浅槽隔离(Shallow Trench Isolation，STI)，通过化学机械抛光(Chemical-MechanicalPolishing，CMP)进行表面平坦化，衬底表面保留50nm SiO2，如图2所示；
2)通过光刻、各向异性刻蚀形成器件下有源区的外延窗口；
3)通过原位掺杂的外延工艺分别在N well上形成P+重掺杂下有源区(作为PMOS的源/漏端)，在P well上形成N+重掺杂下有源区(作为NMOS的源/漏端)，如图3所示；
4)通过ALD依次淀积5nm SiO2(作SDE掩膜层1，其厚度定义了器件的源漏延伸区SDE的长度为5nm)、17nm Si3N4(作假栅层，其厚度定义了器件的沟道长度Lg＝17nm)、5nmSiO2(作SDE掩膜层2，其厚度定义了器件的源漏延伸区SDE的长度为5nm)，如图4所示；
5)通过光刻、各向异性刻蚀形成器件沟道外延窗口(窗口为直径6nm的圆柱体，窗口底部露出N/PMOS的重掺杂下有源区)，如图5所示；
6)通过外延本征硅形成器件的沟道，如图6所示；
7)通过CMP磨去超出SDE掩膜层2上表面的外延沟道材料，实现平坦化，如图7所示；
8)LPCVD 20nm Si3N4作为掩膜，通过光刻、各向异性刻蚀露出NMOS的沟道(Si3N4掩膜覆盖所有PMOS的沟道)；
9)通过原位掺杂外延形成NMOS的重掺杂上有源区(作为NMOS的源/漏端)；
10)去除Si3N4掩膜，如图8所示；
11)通过LPCVD淀积20nm Si3N4作为掩膜，通过光刻、各向异性刻蚀露出PMOS的沟道(Si3N4掩膜覆盖所有NMOS的沟道与重掺杂上有源区)；
12)通过原位掺杂外延形成PMOS的重掺杂上有源区(作为PMOS的源/漏端)；
13)去除Si3N4掩膜，如图9所示；
14)通过退火工艺激活N/PMOS的源漏杂质，并使源漏杂质扩散进入SDE区形成LDD；
15)通过LPCVD淀积30nm SiO2作为顶部掩膜，如图10所示；
16)通过光刻定义栅电极；
17)通过各向异性刻蚀，去除30nm SiO2(顶部掩膜)、5nm SiO2(SDE掩膜层2)、17nmSi3N4(假栅层)，露出SDE掩膜层1的上表面；
18)通过各向同性刻蚀，去除整个Si3N4假栅层，如图11所示；
19)通过ALD依次淀积HK介质和金属栅(MG)材料，如图12所示；
20)通过各向异性刻蚀去除不被顶部SiO2掩膜覆盖的HKMG材料，露出SDE掩膜层1的上表面，如图13所示；
21)通过PECVD淀积200nm SiO2作为隔离层，并通过CMP实现平坦化，如图14所示；
22)通过光刻、各向异性刻蚀形成器件栅、源、漏、体各端的接触孔，如图15所示；
23)通过溅射在各接触孔中填充金属Metal 0，如图16所示；
24)通过对金属Metal 0进行CMP，实现器件之间的导电层分离，达到器件隔离的效果，如图17所示；
25)后续按已公开的后端工艺完成器件集成。
实施例2：
根据下列步骤可以实现SOI衬底上两种材料沟道的直径4.5nm的垂直纳米线器件(如Si-NMOS与Ge-PMOS)的混合集成(其结构参数根据ITRS-2013中“8/7nm”技术代的High-Performance器件进行设定)：
1)在(100)SOI衬底上外延20nm的GeSi，分别进行N+与P+掺杂形成器件的下有源区(作器件的源/漏端)；
2)通过光刻、刻蚀实现N/P器件下有源区的隔离，如图19所示；
3)通过LPCVD SiO2形成STI，通过CMP进行表面平坦化，露出重掺杂下有源区的上表面；
4)通过ALD依次淀积3nm SiO2(作SDE掩膜层1，其厚度定义了器件的源漏延伸区SDE的长度为3nm)、14nm Si3N4(作假栅层，其厚度定义了器件的沟道长度Lg＝14nm)、3nmSiO2(作SDE掩膜层2，其厚度定义了器件的源漏延伸区SDE的长度为3nm)；
5)通过光刻、各向异性刻蚀形成器件沟道外延窗口(窗口为直径4.5nm的圆柱体，窗口底部露出N/PMOS的重掺杂下有源区)；
6)通过原位掺杂外延工艺，分别在NMOS的下有源区上形成P型轻掺杂Si沟道，在PMOS的下有源区上形成N型轻掺杂Ge沟道，如图20所示；
7)通过CMP磨去超出SDE掩膜层2上表面的外延沟道材料，实现平坦化；
8)通过原位掺杂外延工艺，分别在本征Si沟道上形成N+重掺杂SiGe上有源区(作为NMOS器件的源/漏端)，在本征Ge沟道上形成P+重掺杂SiGe上有源区(作为PMOS器件的源/漏端)；
9)通过退火工艺激活N/PMOS的源漏杂质，并使源漏杂质扩散进入SDE区形成LDD；
10)通过LPCVD淀积30nm SiO2作为掩膜，如图21所示；
11)通过光刻定义栅电极；
12)通过各向异性刻蚀，去除30nm SiO2(顶部掩膜)、3nm SiO2(SDE掩膜层2)、14nmSi3N4(假栅层)，露出SDE掩膜层1的上表面；
13)通过各向同性刻蚀，去除整个Si3N4假栅层；
14)通过ALD依次淀积HK介质和金属栅(MG)材料；
15)通过各向异性刻蚀去除不被顶部SiO2掩膜覆盖的HKMG材料，露出SDE掩膜层1的上表面；
16)通过PECVD淀积200nm SiO2作为隔离层，并通过CMP实现平坦化；
17)通过光刻、各向异性刻蚀形成器件栅、源、漏各端的接触孔；
18)通过溅射在各接触孔中填充金属Metal 0；
19)通过对金属Metal 0进行CMP，实现器件之间的导电层分离，达到器件隔离的效果，如图22所示；
20)后续按已公开的后端工艺完成器件集成。
本发明实施例并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (7)

1.一种垂直纳米线晶体管的集成方法，包括如下步骤：
A.提供一半导体衬底，并形成器件之间的隔离；
B.形成器件的重掺杂的下有源区；
C.淀积假栅叠层，具体实现步骤如下：
C1.淀积一层介质作第一SDE掩膜层，其厚度定义了器件的源漏延伸区SDE的长度；
C2.淀积一层介质作假栅层，其厚度定义了器件的沟道长度Lg；
C3.淀积一层介质作第二SDE掩膜层，其厚度定义了器件的源漏延伸区SDE的长度；
D.通过图形化外延形成沟道，具体实现步骤如下：
D1.通过光刻定义沟道外延窗口，其大小、形状决定了器件沟道截面的大小、形状；
D2.通过各向异性刻蚀形成沟道外延窗口，窗口底部露出器件的重掺杂的下有源区；
D3.通过外延形成器件的沟道，并通过CMP去除超出SDE掩膜层2上表面的外延沟道材料，实现平坦化；
E.通过图形化外延形成器件的重掺杂的上有源区，具体实现步骤如下：
E1.淀积一层介质作硬掩膜，通过光刻、各向异性刻蚀露出NMOS的沟道；
E2.通过原位掺杂外延形成NMOS的重掺杂的上有源区；
E3.去除硬掩膜；
E4.淀积一层介质作硬掩膜，通过光刻、各向异性刻蚀露出PMOS的沟道；
E5.通过原位掺杂外延形成PMOS的重掺杂的上有源区；
E6.去除硬掩膜；
E7.通过退火工艺激活源漏杂质，并使源漏杂质扩散进入SDE区形成LDD；
F.去除假栅，淀积高K介质和金属栅材料并形成栅电极，具体实现步骤如下：
F1.淀积一层介质作顶部掩膜层；
F2.通过光刻定义栅电极；
F3.通过各向异性刻蚀，露出SDE掩膜层1的上表面；
F4.通过各向同性刻蚀，去除整个假栅层；
F5.依次淀积高K介质和金属栅材料；
F6.通过各向异性刻蚀，去除不被顶部掩膜层覆盖的HKMG材料，露出SDE掩膜层1的上表面；
H.形成器件各端的金属接触，具体实现步骤如下：
H1.淀积一层介质作层间隔离，并通过CMP实现平坦化；
H2.通过光刻、各向异性刻蚀形成器件各端的接触孔；
H3.在各接触孔中填充金属Metal 0；
H4.通过对金属Metal 0进行CMP，实现器件之间的导电层分离，达到器件隔离的效果；
I.后续按已公开的后端工艺完成器件集成。
2.如权利要求1所述的集成方法，其特征在于，所述半导体衬底为体硅衬底、SOI衬底、体锗衬底、GOI衬底或化合物衬底。
3.如权利要求1所述的集成方法，其特征在于，所述步骤A中隔离，对于体衬底使用阱隔离加浅槽隔离；对于SOI或GOI衬底，使用浅槽隔离。
4.如权利要求1所述的集成方法，其特征在于，所述步骤C中第一SDE掩膜层与第二SDE掩膜层的材料相同，与假栅层材料相异，且假栅层材料对第一SDE掩膜层、第二SDE掩膜层的各向同性刻蚀选择比均大于5:1。
5.如权利要求1所述的集成方法，其特征在于，所述步骤F1中所述顶部掩膜层的材料与假栅层的材料不同，且假栅层材料对该顶部掩膜层的各向同性刻蚀选择比大于5:1。
6.如权利要求1所述的集成方法，其特征在于，所述步骤F1中所述顶部掩膜层的厚度要求，在F6中通过各向异性刻蚀，去除不被顶部掩膜层覆盖的高K介质和金属栅材料，露出第一SDE掩膜层的上表面后，在器件的上有源区上该顶部掩膜层仍有剩余。
7.如权利要求1所述的集成方法，其特征在于，所述步骤H3中金属Metal 0为W或Cu。
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