JP6173083B2 - 電界効果半導体デバイスを製造する方法 - Google Patents
電界効果半導体デバイスを製造する方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title description 8
- 239000004065 semiconductor Substances 0.000 title description 8
- 239000010410 layer Substances 0.000 claims description 126
- 229910052732 germanium Inorganic materials 0.000 claims description 38
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 38
- 125000006850 spacer group Chemical group 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 25
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 5
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 7
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- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910002616 GeOx Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
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- 101100071627 Schizosaccharomyces pombe (strain 972 / ATCC 24843) swo1 gene Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 102100036550 WD repeat-containing protein 82 Human genes 0.000 description 1
- 101710093192 WD repeat-containing protein 82 Proteins 0.000 description 1
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Description
シリコン層またはシリコンゲルマニウム層を含むゲート構造をゲルマニウムチャネル層の上に設ける工程であって、
ゲート構造は、側壁によって横方向に区切られ、
シリコン層またはシリコンゲルマニウム層は、ゲート構造の或る高さレベルで、側壁と横方向に接しているようにした工程と、
シリコン層またはSiGe層のレベルで側壁の上にシリコン酸化物を形成するように、かつ、ゲルマニウムチャネル層の上に形成された幾らかの(any)ゲルマニウム酸化物を除去するように適合した溶液に、ゲルマニウムチャネル層とゲート構造をさらす(subject)工程と、
ゲルマニウムチャネル層の上にソース/ドレイン材料を選択的にエピタキシャル成長させることにより、ダミー構造に隣接するゲルマニウムチャネル層の上に、隆起したソース/ドレイン構造を設ける工程とを含む。
基板層SLの上にゲルマニウムチャネル層CLを堆積させ、続いてダミー誘電体層DDとDGアモルファスシリコンまたは多結晶シリコン層(あるいは、例としてSiGe層を使用できる)を堆積させる。次に、DD層で停止するドライエッチングプロセスを使用してDG層をパターニングする。次に、ウェットプロセスまたはドライプロセスのいずれかにより、DGとCL層に向けてDD層を選択的に除去する。シリコン酸化物誘電体層の場合、フッ化水素酸を使用したウェットプロセスによりDDを除去できる。この時点で、本開示は洗浄工程を含む。洗浄工程では、DGから露出したシリコンを酸化して薄い化学的SiO2層OXとする一方で、露出したゲルマニウムCLの上に成長した最終のGeOxを最小化し、後続のソースS層とドレインD層の選択的なエピタキシャル成長が、露出した酸化物フリーのゲルマニウムCL層の上でのみ生じ、酸化されたDGの上部と側壁の上でブロックされるようにする。これにより、ダミーゲートのシリコンまたはシリコンゲルマニウムの側壁にシリコン酸化物が形成されることに加えて、ダミーゲートの上に保護酸化物層が設けられることが想定される。あるいは、当該技術分野で知られているように、ダミーゲートのシリコンまたはシリコンゲルマニウムの上にシリコン酸化物のハードマスクを付加する別の工程を適用できる。
Claims (13)
- ゲルマニウムチャネル層を備えたFETトランジスタデバイスを製造する方法であって、
シリコン層またはSiGe層を含むゲート構造を前記ゲルマニウムチャネル層の上に設ける工程であって、前記ゲート構造は側壁によって横方向に区切られ、前記シリコン層またはSiGe層は前記ゲート構造の或る高さレベルで前記側壁と横方向に接しているようにした工程と、
前記シリコン層またはSiGe層のレベルで前記側壁の上にシリコン酸化物を形成するように、かつ、前記ゲルマニウムチャネル層の上に形成された幾らかのゲルマニウム酸化物を除去するように適合した溶液に、前記ゲルマニウムチャネル層と前記ゲート構造をさらす工程と、
前記ゲルマニウムチャネル層の上にソース/ドレイン材料を選択的にエピタキシャル成長させることにより、前記ゲート構造に隣接する前記ゲルマニウムチャネル層の上に、隆起したソース/ドレイン構造を設ける工程とを含む方法。 - 前記ゲート構造を設ける工程は、
除去可能ゲート構造を設けることを含み、
前記除去可能ゲート構造を設けることは、
少なくとも1つのダミー酸化物層を設けることと、
ダミーシリコン層またはダミーSiGe層を設けることと、
少なくとも1つの誘電体層を設けることとを含む、請求項1に記載の方法。 - パターニングとドライエッチングによって前記ゲート構造のための横スペーサ構造を設ける工程を含まない、請求項2に記載の方法。
- 前記少なくとも1つのダミー酸化物層と、前記ダミーシリコン層またはダミーSiGe層と、前記少なくとも1つの誘電体層とを除去する工程と、
対応するゲート領域中にhigh−K誘電体層を設ける工程とをさらに含む、請求項2または3に記載の方法。 - 前記溶液は、ゲルマニウム酸化物を除去し、シリコン酸化物に作用しないように適合した、請求項1〜4のいずれか1項に記載の方法。
- 前記溶液は、O3と脱イオン化水とを含む、請求項5に記載の方法。
- 前記ゲルマニウムチャネル層と前記ゲート構造とを、ほぼO3フリーの脱イオン化水にさらす工程をさらに含む、請求項6に記載の方法。
- シリコン酸化物の単一の単分子層より大きい厚さを有する前記シリコン層またはSiGe層のレベルで、前記側壁の上に前記シリコン酸化物を形成する工程を含む、請求項1〜7のいずれか1項に記載の方法。
- 3nmより小さい厚さを有する前記シリコン層またはSiGe層のレベルで、前記側壁の上に前記シリコン酸化物を形成する工程を含む、請求項1〜8のいずれか1項に記載の方法。
- 前記ゲルマニウムチャネル層の上にソース/ドレイン層を選択的にエピタキシャル成長させる工程は、前記ゲルマニウムチャネル層の上にのみ成長させることを含む、請求項1〜9のいずれか1項に記載の方法。
- 前記ゲルマニウムチャネル層の上にソース/ドレイン層を選択的にエピタキシャル成長させる工程は、前記ゲート構造の上に成長させることも、前記ゲート構造の前記側壁の上の前記酸化物の上に成長させることも含まない、請求項1〜10のいずれか1項に記載の方法。
- 前記隆起したソース/ドレイン構造を前記ゲルマニウムチャネル層の上に設けた後、前記隆起したソース/ドレイン構造と前記ゲート構造の前記側壁の上の前記酸化物との間に、更なるスペーサ構造を設ける工程を含む、請求項1〜11のいずれか1項に記載の方法。
- 前記ゲルマニウムチャネル層は、FINFETデバイスまたは同等の3DトランジスタデバイスのFIN構造である、請求項1〜12のいずれか1項に記載の方法。
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WO2017111914A1 (en) * | 2015-12-21 | 2017-06-29 | Intel Corporation | Low band gap semiconductor devices having reduced gate induced drain leakage (gidl) and their methods of fabrication |
US10283620B2 (en) | 2017-01-26 | 2019-05-07 | International Business Machines Corporation | Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices |
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US10763104B2 (en) | 2017-09-28 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming differential etch stop layer using directional plasma to activate surface on device structure |
US10608096B2 (en) | 2018-06-11 | 2020-03-31 | International Business Machines Corporation | Formation of air gap spacers for reducing parasitic capacitance |
US10943818B2 (en) | 2018-10-31 | 2021-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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