WO2014110852A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014110852A1
WO2014110852A1 PCT/CN2013/071636 CN2013071636W WO2014110852A1 WO 2014110852 A1 WO2014110852 A1 WO 2014110852A1 CN 2013071636 W CN2013071636 W CN 2013071636W WO 2014110852 A1 WO2014110852 A1 WO 2014110852A1
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Prior art keywords
fin
gate stack
substrate
barrier
ion implantation
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PCT/CN2013/071636
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English (en)
French (fr)
Inventor
朱慧珑
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中国科学院微电子研究所
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Publication of WO2014110852A1 publication Critical patent/WO2014110852A1/zh
Priority to US14/797,767 priority Critical patent/US9583621B2/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L21/26—Bombardment with radiation
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    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • a three-dimensional semiconductor device such as a FinFET (Fin Field Effect Transistor) has been proposed.
  • a FinFET Fin Field Effect Transistor
  • a FinFET includes a fin that is vertically formed on a substrate and a gate stack that intersects the fin. Additionally, an isolation layer is formed over the substrate to isolate the gate stack from the substrate. Therefore, the bottom of the fin is surrounded by the isolation layer, so that it is difficult to effectively control the bottom of the fin. As a result, leakage current between the source and the drain via the bottom of the fin is apt to occur.
  • a punch-through barrier can be used to reduce this leakage current.
  • PTS punch-through barrier
  • a method of fabricating a semiconductor device comprising: forming a fin structure on a substrate; forming an isolation layer on the substrate, the isolation layer exposing a portion of the fin structure, and exposing the fin structure Partially serving as a fin of the semiconductor device; performing a first ion implantation to form a punch-through barrier in a region under the fin; forming a gate stack intersecting the fin structure on the isolation layer; and performing a second ion implantation to The through barrier is compensated.
  • a semiconductor device comprising: a fin formed on a substrate; a gate stack formed on the substrate intersecting the fin, the gate stack being isolated from the substrate via the isolation layer; a through barrier formed in a region below the fin, the through barrier including a first portion below the intersection of the fin and the gate stack and a second portion on both sides of the first portion, wherein the through portion of the barrier
  • the doping concentration of the two portions is lower than the doping concentration of the first portion of the punch-through barrier.
  • a PTS is formed under the fin.
  • the first portion of the PTS having a high doping concentration is self-aligned below the channel region, so that the leakage current between the source and the drain can be effectively reduced.
  • the second portion of the PTS having a low doping concentration is self-aligned below the source and drain regions, thereby reducing the junction capacitance between the source and drain and the substrate.
  • FIGS. 1-12 are schematic diagrams showing a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a semiconductor device can include a substrate, fins formed on the substrate, and a gate stack that intersects the fins.
  • the gate stack can be isolated from the substrate by an isolation layer.
  • the semiconductor device can be included under the fin Capacitor and junction leakage, the PTS can include a first portion having a relatively high doping concentration below the channel region and a second portion having a relatively low doping concentration below the source/drain region.
  • Such PTS can be formed, for example, by the self-alignment techniques described herein.
  • such a self-alignment technique can be implemented as follows. For example, after forming a fin structure on the substrate and forming an isolation layer exposing a portion of the fin structure (where the exposed portion of the fin structure can be used as a true fin of the semiconductor device), the first ion implantation may be performed to A through barrier (PTS) is formed in a region below the fin. Thereafter, a gate stack (eg, including a gate dielectric layer, a gate conductor layer, and a gate spacer) may be formed on the isolation layer.
  • PTS through barrier
  • a gate stack eg, including a gate dielectric layer, a gate conductor layer, and a gate spacer
  • the gate stack intersects the fin to define a channel region and a source/drain region in the fin (specifically, a portion where the fin intersects the gate stack may become a channel region, and a portion of the fin located on both sides of the channel region may become Source/drain area).
  • a second ion implantation can be performed. Due to the presence of the gate stack, the second ion implantation enters the region below the source/drain region and does not substantially enter the region below the channel region.
  • the dopant type of the second ion implantation may be opposite to the dopant type of the first ion implantation to compensate for the PTS under the source/drain region (e.g., by reducing its doping concentration).
  • the PTS includes a first portion having a relatively high doping concentration (the doping concentration is substantially determined by the first ion implantation) and a second portion on both sides of the first portion (the doping concentration is substantially by the first ion implantation and the second The sum of the effects of ion implantation is determined). Due to the gate stack, the first portion is self-aligned below the gate stack (or channel region) and the second portion is self-aligned below the source/drain regions.
  • strain source/drain techniques may also be applied.
  • the gate stack can be used as a mask to selectively etch the fin structure.
  • a semiconductor layer can be formed by epitaxial growth to form source and drain regions.
  • source and drain regions can stress the channel region (e.g., apply a compressive stress to a p-type device; and apply a tensile stress to an n-type device) to enhance device performance.
  • a replacement gate process may also be combined.
  • the gate stack formed above is a sacrificial gate stack (eg, including a sacrificial gate dielectric layer, a sacrificial gate conductor layer, and a gate spacer).
  • the sacrificial gate conductor layer and the sacrificial gate dielectric can be selectively removed after source/drain implantation (or, after applying the strain source/drain technique as described above, after the source/drain regions are grown)
  • the layer forms a gate trench (or hole) in the gate sidewall.
  • a gate dielectric layer eg, a high-k gate dielectric
  • a gate conductor layer eg, a metal gate conductor
  • the substrate 1000 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • well region 1000-1 may be formed in substrate 1000.
  • an n-type well region can be formed; and for an n-type device, a p-type well region can be formed.
  • the n-type well region can be formed by implanting an n-type impurity such as P or As in the substrate 1000, and the p-type well region can be formed by implanting a p-type impurity such as B in the substrate 1000. If necessary, annealing can also be performed after the implantation.
  • annealing can also be performed after the implantation.
  • the substrate 1000 can be patterned to form a fin structure.
  • a patterned photoresist 1002 is formed on the substrate 1000 as designed.
  • photoresist 1002 is patterned into a series of parallel equally spaced lines.
  • the substrate 1000 is etched by, for example, reactive ion etching (RIE) using the patterned photoresist 1002 as a mask to form a fin structure 1004.
  • RIE reactive ion etching
  • etching of the substrate 1000 is performed into the well region 1000-1. Thereafter, the photoresist 1002 can be removed.
  • the shape of the trench (between the fin structures 1004) formed by etching is not necessarily the regular rectangular shape shown in FIG. 2, and may be, for example, a taper that gradually becomes smaller from top to bottom. Table shape.
  • the position and number of fin structures formed are not limited to the example shown in Fig. 2.
  • the fin structure is not limited to being formed by directly patterning the substrate.
  • an additional semiconductor layer can be epitaxially grown on the substrate, and the additional semiconductor layer can be patterned to form a fin structure. If there is sufficient etch selectivity between the additional semiconductor layer and the substrate, the patterning can be substantially stopped on the substrate when patterning the fin structure, thereby achieving more precise control of the height of the fin structure. .
  • the expression "forming a fin structure on a substrate” includes forming a fin structure on the substrate in any suitable manner.
  • an isolation layer may be formed on the substrate.
  • a spacer layer 1006 can be formed by forming a dielectric layer (e.g., including an oxide such as silicon oxide) on a substrate, for example, by deposition, and then etching back the deposited dielectric layer.
  • the deposited dielectric layer can completely cover the fin structure 1004 and the deposited dielectric can be planarized prior to etch back, such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the deposited dielectric layer can be planarized by sputtering.
  • sputtering may use a plasma such as an Ar or N plasma.
  • the isolation layer 1006 preferably slightly exposes the well region. That is, the top surface of the isolation layer 1006 is slightly larger than the top surface of the well region 1000-1 (the height difference between them is not shown in the drawing).
  • a punch-through barrier (PTS) 1020 is formed by implantation (hereinafter referred to as "first ion implantation") as indicated by an arrow in FIG. .
  • first ion implantation for an n-type device, a p-type impurity such as 8, BF 2 or In can be implanted; for a p-type device, an n-type impurity such as 8 or ? .
  • the first ion implantation can be perpendicular to the surface of the substrate.
  • the parameters of the first ion implantation are controlled such that the PTS is formed in a portion of the fin structure 1004 below the surface of the isolation layer 1006 and has a desired doping concentration, for example, about 5E17-2E19 cm- 3 , and the doping concentration should be high.
  • the doping concentration of the well region 1000-1 in the substrate due to the shape factor (elongated shape) of the fin structure 1004, a part of the dopant (ion or element) may be scattered from the exposed portion of the fin structure, thereby facilitating the formation of a steep doping profile in the depth direction. .
  • Annealing such as spike annealing, laser annealing, and/or rapid annealing may be performed to activate the implanted dopant. This PTS helps to reduce source and drain leakage.
  • a gate stack intersecting the fins may be formed on the isolation layer 1006.
  • a gate dielectric layer 1008 is formed, for example, by deposition.
  • gate dielectric layer 1008 can comprise an oxide having a thickness of between about 0.8 and 1.5 nm. In the example shown in Fig. 7, only the " ⁇ " shaped gate dielectric layer 1008 is shown. However, the gate dielectric layer 1008 may also include a portion that extends over the top surface of the isolation layer 1006.
  • the gate conductor layer 1010 is formed, for example, by deposition.
  • the gate conductor layer 1010 may include polysilicon.
  • the gate conductor layer 1010 may fill a gap between the fins and may be subjected to a planarization process such as CMP.
  • the gate conductor layer 1010 is patterned as shown in Fig. 6 (Fig. 6(b) showing a cross-sectional view taken along line BB' in Fig. 6(a)).
  • the gate conductor layer 1010 is patterned into a strip shape that intersects the fin structure.
  • the patterned gate conductor layer 1010 can also be used as a mask, further
  • the gate dielectric layer 1008 is patterned.
  • a halo implant and an extension implant may be performed using the gate conductor as a mask.
  • a gate spacer 1012 may be formed on the sidewall of the gate conductor layer 1010.
  • the gate spacer 1012 can be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride.
  • a nitride e.g., silicon nitride
  • RIE reactive ion etching
  • a gate stack is formed as described above (eg, including a gate dielectric layer, a gate conductor layer, and a gate spacer) After that, the PTS under the source/drain regions can be compensated.
  • Fig. 8 shows a cross-sectional view taken along line ⁇ 1 of Fig. 7(a)
  • Fig. 8(b) shows a cross-sectional view taken along line B2B2' of Fig.
  • second ion implantation ion implantation
  • the dopant conductivity type of the second ion implantation may be opposite to the dopant conductivity type of the first ion implantation.
  • the second ion implantation may use an n-type dopant such as As or P; for a p-type device, the first ion implantation utilizes an n-type For the dopant, the second ion implantation may use a p-type dopant such as 8, BF 2 or In.
  • the second ion implantation can be perpendicular to the surface of the substrate. The parameters of the second ion implantation are controlled such that they can be injected into the PTS 1020 to effectively compensate the PTS 1020, such as reducing the dopant concentration in the PTS 1020 to about 5E16-1E19 cm- 3 .
  • the region under which the fin structure 1004 intersects the gate stack is substantially unaffected by the second ion implantation.
  • the shape factor (elongated shape) of the fin structure 1004 similar to the above first ion implantation, it can be formed Steep doping profile.
  • the portion of the PTS 1020 under the gate stack retains the original doping concentration, while the remaining portion has a reduced doping concentration (shown as 1020' in Fig. 8(c)).
  • the distribution of the high concentration portion 1020 and the low concentration portion 1020' of the PTS is based on a gate stack (eg, a gate dielectric layer) 1008, gate conductor layer 1010 and gate spacer 1012). Therefore, the high concentration portion 1020 is self-aligned below the channel region, and the low concentration portion 1020' is self-aligned below the source/drain regions.
  • a gate stack eg, a gate dielectric layer
  • source/drain (S/D) implantation may be performed using the gate conductor and the sidewall as a mask. Subsequently, the implanted ions can be activated by annealing to form source/drain regions to obtain a FinFET.
  • strain source/drain techniques can be utilized in accordance with an example of the present disclosure.
  • the exposed gate dielectric layer 1008 is first selectively removed (eg, RIE).
  • RIE reactive ion etching
  • Portions of the fin structure 1004 exposed by the removal of the gate dielectric layer 1008 can then be selectively removed (e.g., RIE). This portion of the fin structure 1004 can be etched to reach the well region 1000-1. Due to the presence of the gate stack, the fin structure 1004 can remain below the gate stack. It is to be noted here that although the edge of the etched fin structure 1004 is shown as being completely aligned with the edge of the gate spacer 1012 in Fig. 9, the present disclosure is not limited thereto. For example, due to the lateral action of the etch (which may be small), the edge of the etched fin structure 1004 is retracted inwardly relative to the edge of the gate spacer 1012.
  • the semiconductor layer 1014 may be formed on the exposed fin structure portion by epitaxy. Source/drain regions can then be formed in the semiconductor layer 1014.
  • the semiconductor layer 1014 may be doped in situ while being grown. For example, for n-type devices, n-type in-situ doping can be performed; for p-type devices, p-type in-situ doping can be performed. Additionally, to further enhance performance, the semiconductor layer 1014 can include a material different from the fin structure 1004 to enable stress to be applied to the fins 1004 where the channel regions of the device will be formed.
  • the semiconductor layer 1014 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for a p-type device, the semiconductor layer 1014 may include SiGe (for example, an atomic percentage of Ge is about 15-75%) to apply compressive stress.
  • the semiconductor layer 1014 is illustrated as a fin corresponding to the fin structure 1004 in the drawing (for example, a portion indicated by a broken line in FIGS. 11(a), 12(a)), the present disclosure is not limited thereto.
  • the semiconductor layer 1014 may be grown to be broadened in the lateral direction. Degree.
  • the gate conductor layer 1010 includes polysilicon
  • growth of the semiconductor layer 1014 may also occur on the top surface of the sacrificial gate conductor layer 1010. This is not shown in the drawings.
  • the gate stack is directly formed.
  • the present disclosure is not limited to this.
  • an alternative gate process is equally applicable to the present disclosure.
  • the gate dielectric layer 1008 and the gate conductor layer 1010 formed in FIG. 5 are a sacrificial gate dielectric layer and a sacrificial gate conductor layer (such a gate stack obtained by the operations described in connection with FIGS. To sacrifice the gate stack).
  • the PTS can be compensated in the same manner as described above in connection with FIG.
  • the strain source/drain technique can be applied as described above in connection with Figures 9-10.
  • the sacrificial gate stack can be processed according to a replacement gate process to form a true gate stack of the device. For example, this can be done as follows.
  • a dielectric layer 1016 is formed, for example, by deposition.
  • the dielectric layer 1016 can comprise, for example, an oxide.
  • the dielectric layer 1016 is subjected to a planarization process such as CMP.
  • the CMP can be stopped at the gate spacer 1012 to expose the sacrificial gate conductor layer 1010.
  • Fig. 12 shows a cross-sectional view taken along line BB' in Fig. 12 (a)
  • Fig. 12 (c) shows a cross-sectional view along line CC' in Fig. 12 (a)
  • the sacrificial gate conductor 1010 is selectively removed, for example, by a TMAH solution, thereby forming a gate trench inside the gate spacer 1012.
  • the sacrificial gate dielectric layer 1008 can also be further removed.
  • a final gate stack is formed by forming a gate dielectric layer 1022 and a gate conductor layer 1024 in the gate trenches.
  • the gate dielectric layer 1022 can comprise a high K gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • Gate conductor layer 1024 can include a metal gate conductor.
  • a success function adjustment layer (not shown) may also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024.
  • the semiconductor device can include a fin 1004 formed on a substrate 1000 and a gate stack intersecting the fin 1004.
  • the gate stack can include a gate dielectric layer 1022 and a gate conductor layer 1024 (and gate spacers 1022) and is isolated from the substrate by an isolation layer 1006.
  • the semiconductor device also includes a PTS formed in a region under the fin, the PTS including self-aligned to the channel region (corresponding to the intersection of the fin 1004 and the gate stack)
  • the lower doped concentration portion 1020 and the low doping concentration portion 1020' that is self-aligned below the source/drain regions (corresponding to portions of the fin 1004 located on either side of the channel region).
  • the doping of the PTS can be a p-type impurity such as 8, BF 2 or In; for a p-type device, the doping of the PTS can be an n-type impurity such as 8 or ? .
  • a well region 1000-1 may be formed in the substrate 1000.
  • the doping concentration of the high doping concentration portion 1020 self-aligned below the channel region is higher than the doping concentration of the well region 1000-1 in the substrate.
  • a portion of the fin structure 1004 exposed by the isolation layer 1006 (the above-mentioned "fin") is left under the gate stack, and a semiconductor layer 1014 is formed on the opposite side of the fin for A source/drain region is formed.
  • the semiconductor layer 1014 may be formed in a fin shape.

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Abstract

一种半导体器件及其制造方法。半导体器件包括：在衬底（1000）上形成的鳍（1004）；在衬底（1000）上形成的与鳍（1004）相交的栅堆叠，栅堆叠经由隔离层（1006）与衬底（1000）隔离；以及在鳍（1004）下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鳍（1004）与栅堆叠相交部分下方的第一部分（1020）以及位于第一部分（1020）两侧的第二部分（1020'），其中穿通阻挡部的第二部分（1020'）的掺杂浓度低于穿通阻挡部的第一部分（1020）的掺杂浓度。

Description

半导体器件及其制造方法
本申请要求了 2013年 1月 15日提交的、 申请号为 201310014886.0、发明 名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通 过引用结合在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。 背景技术
随着平面型半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提 出了立体型半导体器件如 FinFET (鰭式场效应晶体管）。 一般而言， FinFET 包括在衬底上竖直形成的鰭以及与鰭相交的栅堆叠。 另外，衬底上形成有隔离 层， 以隔离栅堆叠与衬底。 因此， 鰭的底部被隔离层所包围， 从而栅难以有效 控制鰭的底部。 结果， 易于出现源和漏之间经由鰭底部的漏电流。
通常， 可以釆用穿通阻挡部（PTS )来减小这种漏电流。 但是， 这种 PTS 的引入增大了结泄漏和结电容。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬 底上形成鰭状结构； 在衬底上形成隔离层， 隔离层露出鰭状结构的一部分， 鰭 状结构的露出部分用作该半导体器件的鰭； 进行第一离子注入， 以在鰭下方的 区域中形成穿通阻挡部； 在隔离层上形成与鰭状结构相交的栅堆叠； 以及进行 第二离子注入， 以对穿通阻挡部进行补偿。
根据本公开的另一方面， 提供了一种半导体器件， 包括： 在衬底上形成的 鰭； 在衬底上形成的与鰭相交的栅堆叠， 栅堆叠经由隔离层与衬底隔离； 以及 在鰭下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鰭与栅堆叠相交 部分下方的第一部分以及位于第一部分两侧的第二部分，其中穿通阻挡部的第 二部分的掺杂浓度低于穿通阻挡部的第一部分的掺杂浓度。
根据本发明的示例性实施例，在鰭的下方形成 PTS。通过上述第一离子注 入和第二离子注入， PTS中掺杂浓度高的第一部分自对准于沟道区下方，从而 可以有效降低源和漏之间的漏电流。 另夕卜， PTS中掺杂浓度低的第二部分自对 准于源、 漏区下方， 从而可以降低源、 漏与衬底之间的结电容。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1-12是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些 细节。 图中所示出的各种区域、 层的形状以及它们之间的相对大小、位置关系 仅是示例性的， 实际中可能由于制造公差或技术限制而有所偏差， 并且本领域 技术人员根据实际所需可以另外设计具有不同形状、 大小、 相对位置的区域 / 层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该 层 /元件可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时， 该层 /元件可以位于该另一层 /元件 "下"。
根据本公开的实施例，提供了一种半导体器件， 该半导体器件可以包括衬 底、在衬底上形成的鰭以及与鰭相交的栅堆叠。栅堆叠可以通过隔离层与衬底 相隔离。
为防止源漏区之间经由鰭底部的泄漏，该半导体器件可以包括在鰭下方的 电容和结泄漏， PTS可以包括位于沟道区下方的掺杂浓度相对较高的第一部 分以及位于源 /漏区下方的掺杂浓度相对较低的第二部分。 这种 PTS例如可以 通过本文所述的自对准技术来形成。
根据本公开的实施例， 这种自对准技术可以如下实现。 例如， 在衬底上形 成鰭状结构并形成露出鰭状结构一部分的隔离层（其中，鰭状结构的露出部分 可以用作该半导体器件的真正鰭）之后， 可以进行第一离子注入， 以在鰭下方 的区域中形成穿通阻挡部（PTS )。 之后， 可以在隔离层上形成栅堆叠（例如， 包括栅介质层、 栅导体层和栅侧墙）。 栅堆叠与鰭相交， 从而在鰭中限定了沟 道区以及源 /漏区 （具体地， 鰭与栅堆叠相交的部分可以成为沟道区， 而鰭中 位于沟道区两侧的部分可以成为源 /漏区）。 可以进行第二离子注入。 由于栅堆 叠的存在， 第二离子注入进入到源 /漏区下方的区域中， 而基本不会进入沟道 区下方的区域中。该第二离子注入的掺杂剂类型可以与第一离子注入的掺杂剂 类型相反，从而对源 /漏区下方的 PTS进行补偿（例如，通过降低其掺杂浓度）。 于是， PTS包括掺杂浓度相对较高的第一部分（掺杂浓度基本上由第一离子注 入决定）以及位于第一部分两侧的第二部分（掺杂浓度基本上由第一离子注入 和第二离子注入的效果总和来决定）。 由于栅堆叠， 第一部分自对准于栅堆叠 (或者沟道区） 下方， 而第二部分自对准于源 /漏区下方。
根据本公开的其他实施例， 还可以应用应变源 /漏技术。 例如， 在形成栅 堆叠之后， 可以栅堆叠为掩模， 对鰭状结构进行选择性刻蚀。 然后， 可以通过 外延生长形成一半导体层， 用以形成源、 漏区。 这种源、 漏区可以向沟道区施 加应力 （例如， 对于 p型器件， 施加压应力； 而对于 n型器件， 施加拉应力）， 以增强器件性能。
根据本公开的其他实施例， 还可以结合替代栅工艺。 例如， 上述形成的栅 堆叠为牺牲栅堆叠 （例如， 包括牺牲栅介质层、 牺牲栅导体层和栅侧墙）。 根 据替代栅工艺， 在进行源 /漏注入之后 （或者， 在如上所述应用应变源 /漏技术 的情况下， 在生长源 /漏区之后）， 可以选择性去除牺牲栅导体层和牺牲栅介质 层， 在栅侧墙内形成栅槽（或孔）。 然后， 在栅槽（或孔）内形成栅介质层（例 如， 高 K栅介质）和栅导体层（例如， 金属栅导体）， 从而形成器件的真正栅 堆叠。
本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如 但不限于体半导体材料衬底如体 Si衬底、 绝缘体上半导体 ( SOI )衬底、 化合 物半导体衬底如 SiGe衬底等。 在以下的描述中， 为方便说明， 以体 Si衬底为 例进行描述。
根据本公开的一些示例， 可以在衬底 1000中形成阱区 1000-1。 例如， 对 于 p型器件，可以形成 n型阱区； 而对于 n型器件，可以形成 p型阱区。例如， n型阱区可以通过在衬底 1000中注入 n型杂质如 P或 As来形成， p型阱区可 以通过在衬底 1000中注入 p型杂质如 B来形成。 如果需要， 在注入之后还可 以进行退火。 本领域技术人员能够想到多种方式来形成 n型阱、 p型阱， 在此 不再赘述。
接下来， 可以对衬底 1000进行构图， 以形成鰭状结构。 例如， 这可以如 下进行。 具体地， 在衬底 1000上按设计形成构图的光刻胶 1002。 通常， 光刻 胶 1002被构图为一系列平行的等间距线条。 然后， 如图 2所示， 以构图的光 刻胶 1002为掩模， 对衬底 1000进行刻蚀例如反应离子刻蚀 （RIE ), 从而形 成鰭状结构 1004。 在此， 对衬底 1000的刻蚀进行到阱区 1000-1中。 之后， 可 以去除光刻胶 1002。
这里需要指出的是， 通过刻蚀所形成的 （鰭状结构 1004之间的） 沟槽的 形状不一定是图 2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥 台形。 另外， 所形成的鰭状结构的位置和数目不限于图 2所示的示例。
另外， 鰭状结构不限于通过直接对衬底进行构图来形成。 例如， 可以在衬 底上外延生长另外的半导体层， 对该另外的半导体层进行构图来形成鰭状结 构。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性， 则在对鰭状结 构进行构图时， 可以使构图基本上停止于衬底，从而实现对鰭状结构高度的较 精确控制。
因此， 在本公开中， 表述 "在衬底上形成鰭状结构" 包括以任何适当的方 式在衬底上形成鰭状结构。
在通过上述处理形成鰭状结构之后， 可以在衬底上形成隔离层。 例如， 如 图 3所示， 可以在衬底上例如通过淀积形成电介质层（例如， 可以包括氧化物 如氧化硅）， 然后对淀积的电介质层进行回蚀， 来形成隔离层 1006。 通常， 淀 积的电介质层可以完全覆盖鰭状结构 1004, 并且在回蚀之前可以对淀积的电 介质进行平坦化， 如化学机械抛光（CMP )。 根据一优选示例， 可以通过溅射 来对淀积的电介质层进行平坦化处理。 例如， 溅射可以使用等离子体， 如 Ar 或 N等离子体。 在衬底 1000中形成阱区 1000-1的情况下， 隔离层 1006优选 稍稍露出阱区。 即， 隔离层 1006的顶面略 ^于阱区 1000-1的顶面（附图中没 有示出它们之间的高度差）。
为改善器件性能， 特别是降低源漏泄漏， 根据本公开的一示例， 如图 4 中的箭头所示，通过注入（以下称作"第一离子注入"）来形成穿通阻挡部（ PTS ) 1020。 例如， 对于 n型器件而言， 可以注入 p型杂质， 如：8、 BF2或 In; 对于 p型器件， 可以注入 n型杂质， 如 8或？。 第一离子注入可以垂直于衬底表 面。控制第一离子注入的参数,使得 PTS形成于鰭状结构 1004位于隔离层 1006 表面之下的部分中， 并且具有期望的掺杂浓度， 例如约 5E17-2E19 cm-3, 并且 掺杂浓度应高于衬底中阱区 1000-1的掺杂浓度。应当注意，由于鰭状结构 1004 的形状因子 （细长形）， 一部分掺杂剂 （离子或元素）可能从鰭状结构的露出 部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。 可以进行退火 如尖峰退火、 激光退火和 /或快速退火， 以激活注入的掺杂剂。 这种 PTS有助 于减小源漏泄漏。
随后， 可以在隔离层 1006上形成与鰭相交的栅堆叠。 例如， 这可以如下 进行。 具体地， 如图 5所示， 例如通过淀积， 形成栅介质层 1008。 例如， 栅 介质层 1008可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 7所示的示例中， 仅 示出了 " Π " 形的栅介质层 1008。 但是， 栅介质层 1008也可以包括在隔离层 1006的顶面上延伸的部分。 然后， 例如通过淀积， 形成栅导体层 1010。 例如， 栅导体层 1010可以包括多晶硅。栅导体层 1010可以填充鰭之间的间隙， 并可 以进行平坦化处理例如 CMP。
如图 6 (图 6 ( b )示出了沿图 6 ( a ) 中 BB'线的截面图）所示， 对栅导体 层 1010进行构图。在图 6的示例中，栅导体层 1010被构图为与鰭状结构相交 的条形。 根据另一实施例， 还可以构图后的栅导体层 1010为掩模， 进一步对 栅介质层 1008进行构图。
在形成构图的栅导体之后， 例如可以栅导体为掩模， 进行晕圈 （halo)注 入和延伸区 (extension) 注入。
接下来， 如图 7 (图 7 (b)示出了沿图 7 (a) 中 CC'线的截面图）所示， 可以在栅导体层 1010的侧壁上形成栅侧墙 1012。 例如， 可以通过淀积形成厚 度约为 5-20nm的氮化物（如氮化硅）， 然后对氮化物进行 RIE, 来形成栅侧墙 1012。 本领域技术人员知道多种方式来形成这种侧墙， 在此不再赘述。 在鰭之 间的沟槽为从上到下逐渐变小的锥台形时 (由于刻蚀的特性，通常为这样的情 况）， 栅侧墙 1012基本上不会形成于鰭的侧壁上。
为改善器件性能， 特别是降低源 /漏区与衬底之间的结电容， 根据本公开 的一示例，在如上所述形成栅堆叠（例如， 包括栅介质层、栅导体层和栅侧墙） 之后， 可以对源 /漏区下方的 PTS进行补偿。 例如， 如图 8 (图 8 (a)示出了 沿图 7 (a) 中 Β1ΒΓ线的截面图， 图 8 (b)示出了沿图 7 (a) 中 B2B2'线的 截面图， 图 8 (c)示出了沿图 7 (a) 中 CC'线的截面图） 中的箭头所示， 进 行离子注入（以下称作 "第二离子注入"）， 以降低 PTS 1020中的掺杂浓度。 具体地，第二离子注入的掺杂剂导电类型可以与第一离子注入的掺杂剂导电类 型相反。 例如， 对于 n型器件， 由于第一离子注入利用 p型掺杂剂， 则第二离 子注入可以使用 n型掺杂剂， 如 As或 P; 对于 p型器件， 由于第一离子注入 利用 n型掺杂剂， 则第二离子注入可以使用 p型掺杂剂， 如：8、 BF2或 In。 第 二离子注入可以垂直于衬底表面。控制第二离子注入的参数，使得其能够注入 到 PTS 1020中， 以对 PTS 1020进行有效补偿， 例如将 PTS 1020中的掺杂剂 浓度降低到约 5E16-1E19 cm-3。
如图 8 (a)所示， 由于栅堆叠的存在， 鰭状结构 1004与栅堆叠相交部分 (沟道区将在其中形成）下方的区域基本上不会受到第二离子注入的影响。相 反， 如图 8 (b)所示， 在鰭状结构 1004位于栅堆叠两侧的部分下方， 由于鰭 状结构 1004的形状因子（细长形；)， 同以上第一离子注入类似， 能够形成陡峭 的掺杂分布。 结果， 如图 8 (c)所示， PTS 1020位于栅堆叠下方的部分保留 原有掺杂浓度， 而其余部分则掺杂浓度降低（图 8 (c) 中示出为 1020')。 PTS 的高浓度部分 1020和低浓度部分 1020'的分布是根据栅堆叠（例如， 栅介质层 1008、 栅导体层 1010和栅侧墙 1012 )得到的。 因此， 高浓度部分 1020 自对 准于沟道区下方， 而低浓度部分 1020'自对准于源 /漏区下方。
在形成侧墙之后， 可以栅导体及侧墙为掩模， 进行源 /漏（ S/D )注入。 随 后， 可以通过退火， 激活注入的离子， 以形成源 /漏区， 得到 FinFET。
为改善器件性能， 根据本公开的一示例， 可以利用应变源 /漏技术。 具体 地， 如图 9所示， 首先选择性去除（例如， RIE )暴露在外的栅介质层 1008。 在栅介质层 1008和隔离层 1006均包括氧化物的情况下， 由于栅介质层 1008 较薄， 因此对栅介质层 1008的 RIE基本上不会影响隔离层 1006。 在以上形成 栅堆叠的过程中， 以栅导体为掩模进一步构图栅介质层的情况下， 不再需要该 操作。
然后， 可以选择性去除（例如， RIE ) 由于栅介质层 1008 的去除而露出 的鰭状结构 1004的部分。对鰭状结构 1004该部分的刻蚀可以进行至到达阱区 1000-1。 由于栅堆叠的存在， 鰭状结构 1004可以留于栅堆叠下方。 这里需要 指出的是， 尽管在图 9中将刻蚀后鰭状结构 1004的边缘示出为与栅侧墙 1012 的边缘完全对准， 但是本公开不限于此。 例如， 由于刻蚀的横向作用 （可能很 小 ) , 从而刻蚀后鰭状结构 1004的边缘相对于栅侧墙 1012的边缘向里缩进。
接下来， 如图 10所示， 例如可以通过外延， 在露出的鰭状结构部分上形 成半导体层 1014。 随后可以在该半导体层 1014中形成源 /漏区。根据本公开的 一实施例， 可以在生长半导体层 1014的同时， 对其进行原位掺杂。 例如， 对 于 n型器件， 可以进行 n型原位掺杂； 而对于 p型器件， 可以进行 p型原位掺 杂。另外，为了进一步提升性能，半导体层 1014可以包括不同于鰭状结构 1004 的材料， 以便能够向鰭 1004 (其中将形成器件的沟道区）施加应力。 例如， 在鰭状结构 1004包括 Si的情况下， 对于 n型器件， 半导体层 1014可以包括 Si:C ( C的原子百分比例如为约 0.2-2% ), 以施加拉应力； 对于 p型器件， 半 导体层 1014可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ), 以施加压 应力。
尽管在附图中将半导体层 1014示出为与鰭状结构 1004相对应的鰭状（例 如， 图 11 ( a )、 12 ( a ) 中的虚线所示部位）， 但是本公开不限于此。 例如， 为 了方便制造与源 /漏区的接触， 可以将半导体层 1014生长为在横向上展宽一定 程度。
在栅导体层 1010包括多晶硅的情况下，半导体层 1014的生长可能也会发 生在牺牲栅导体层 1010的顶面上。 这在附图中并未示出。
在上述实施例中， 在形成鰭之后， 直接形成了栅堆叠。 本公开不限于此。 例如， 替代栅工艺同样适用于本公开。
根据本公开的另一实施例， 在图 5 中形成的栅介质层 1008 和栅导体层 1010为牺牲栅介质层和牺牲栅导体层（这样， 通过结合图 6、 7描述的操作得 到的栅堆叠为牺牲栅堆叠）。 接下来， 可以同样按以上结合图 8描述的操作来 对 PTS进行补偿。 另外， 同样可以按以上结合图 9-10描述的操作， 来应用应 变源 /漏技术。
接下来， 可以根据替代栅工艺， 对牺牲栅堆叠进行处理， 以形成器件的真 正栅堆叠。 例如， 这可以如下进行。
具体地， 如图 11 (图 11 ( b )示出了沿图 11 ( a ) 中 CC'线的截面图） 所 示， 例如通过淀积， 形成电介质层 1016。 该电介质层 1016例如可以包括氧化 物。 随后， 对该电介质层 1016进行平坦化处理例如 CMP。 该 CMP可以停止 于栅侧墙 1012, 从而露出牺牲栅导体层 1010。
随后， 如图 12 (图 12 ( b )示出了沿图 12 ( a ) 中 BB'线的截面图， 图 12 ( c )示出了沿图 12 ( a ) 中 CC'线的截面图）所示， 例如通过 TMAH溶液， 选择性去除牺牲栅导体 1010, 从而在栅侧墙 1012内侧形成了栅槽。 根据另一 示例， 还可以进一步去除牺牲栅介质层 1008。 然后， 通过在栅槽中形成栅介 质层 1022和栅导体层 1024,形成最终的栅堆叠。栅介质层 1022可以包括高 K 栅介质例如 Hf02, 厚度为约 l-5nm。 栅导体层 1024可以包括金属栅导体。 优 选地，在栅介质层 1022和栅导体层 1024之间还可以形成功函数调节层（未示 出）。
这样， 就得到了根据本公开实施例的半导体器件。 如图 12所示， 该半导 体器件可以包括在衬底 1000上形成的鰭 1004以及与鰭 1004相交的栅堆叠。 在该实施例中， 栅堆叠可以包括栅介质层 1022和栅导体层 1024 (以及栅侧墙 1022 ),且通过隔离层 1006与衬底隔离开。该半导体器件还包括在鰭下方的区 域中形成的 PTS, 该 PTS包括自对准于沟道区 （对应于鰭 1004与栅堆叠相交 的部分） 下方的高掺杂浓度部分 1020 以及自对准于源 /漏区 （对应于鰭 1004 中位于沟道区两侧的部分） 下方的低掺杂浓度部分 1020'。 例如， 对于 n型器 件而言， PTS的掺杂可以为 p型杂质， 如：8、 BF2或 In; 对于 p型器件， PTS 的掺杂可以为 n型杂质， 如 8或？。
衬底 1000中可以形成有阱区 1000-1。 自对准于沟道区下方的高掺杂浓度 部分 1020的掺杂浓度高于衬底中阱区 1000-1的掺杂浓度。
另外，在应用应变源漏技术的情况下， 鰭状结构 1004被隔离层 1006露出 的部分（上述 "鰭"） 留于栅堆叠下方， 且在鰭的相对侧面上形成有半导体层 1014, 用以形成源 /漏区。 半导体层 1014可以形成为鰭状。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种制造半导体器件的方法， 包括：
在衬底上形成鰭状结构；
在衬底上形成隔离层， 隔离层露出鰭状结构的一部分，鰭状结构的露出部 分用作该半导体器件的鰭；
进行第一离子注入， 以在鰭下方的区域中形成穿通阻挡部；
在隔离层上形成与鰭状结构相交的栅堆叠； 以及
进行第二离子注入， 以对穿通阻挡部进行补偿。
2. 根据权利要求 1所述的方法， 其中，
进行第一离子注入包括： 对于 n型器件， 注入 p型掺杂剂； 和 /或对于 p 型器件， 注入 n型掺杂剂；
进行第二离子注入包括：注入与第一离子注入的掺杂剂导电类型相反的掺 杂剂。
3. 根据权利要求 2所述的方法， 其中， 在第二离子注入之前穿通阻挡 部中的掺杂剂浓度为约 5E17-2E19 cm-3 ,在第二离子注入之后穿通阻挡部中受 到补偿的区域的掺杂剂浓度为约 5E16-1E19 cm_3。
4. 根据权利要求 1所述的方法， 其中， 在第二离子注入之后， 该方法 还包括：
以栅堆叠为掩模， 对鰭状结构进行选择性刻蚀； 以及
外延生长半导体层， 用以形成源、 漏区。
5. 根据权利要求 4所述的方法， 还包括： 在外延生长半导体层同时， 对该半导体层进行原位掺杂。
6. 根据权利要求 4所述的方法， 其中， 对于 p型器件， 半导体层带压 应力； 而对于 n型器件， 半导体层带拉应力。
7. 根据权利要求 1所述的方法， 其中， 形成的栅堆叠为牺牲栅堆叠， 该方法还包括： 根据替代栅工艺， 对牺牲栅堆叠进行处理， 以形成器件栅 堆叠。
8. 一种半导体器件， 包括： 在衬底上形成的鰭；
在衬底上形成的与鰭相交的栅堆叠，栅堆叠经由隔离层与衬底隔离； 以及 在鰭下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鰭与栅堆叠 相交部分下方的第一部分以及位于第一部分两侧的第二部分，其中穿通阻挡部 的第二部分的掺杂浓度低于穿通阻挡部的第一部分的掺杂浓度。
9. 根据权利要求 8所述的半导体器件， 其中， 鰭位于栅堆叠下方， 且 该半导体器件还包括在鰭的相对侧面上形成的半导体层，用以形成半导体器件 的源 /漏区。
10. 根据权利要求 9所述的半导体器件， 其中， 对于 p型器件， 半导体 层带压应力； 而对于 n型器件， 半导体层带拉应力。
11. 根据权利要求 10所述的半导体器件， 其中， 衬底包括 Si, 鰭与衬底 一体， 半导体层包括 SiGe或 Si:C。
12. 根据权利要求 9所述的半导体器件， 其中， 穿通阻挡部的第一部分 自对准于栅堆叠， 且穿通阻挡部的第二部分自对准于源 /漏区。
13. 根据权利要求 8所述的半导体器件， 其中， 穿通阻挡部的第一部分 中掺杂剂浓度为约 5E17-2E19 cm_3, 穿通阻挡部的第二部分中掺杂剂浓度为约 5E16-1E19 cm"3„
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