WO2014015448A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014015448A1
WO2014015448A1 PCT/CN2012/001152 CN2012001152W WO2014015448A1 WO 2014015448 A1 WO2014015448 A1 WO 2014015448A1 CN 2012001152 W CN2012001152 W CN 2012001152W WO 2014015448 A1 WO2014015448 A1 WO 2014015448A1
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Prior art keywords
layer
gate
semiconductor device
fins
gate stack
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PCT/CN2012/001152
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English (en)
French (fr)
Inventor
殷华湘
秦长亮
徐秋霞
陈大鹏
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中国科学院微电子研究所
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Priority to US13/812,867 priority Critical patent/US8652891B1/en
Publication of WO2014015448A1 publication Critical patent/WO2014015448A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a self-aligned multi-gate nanowire FET and a method of fabricating the same. Background technique
  • a three-dimensional multi-gate device In the current sub-20nm technology, a three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects.
  • a MOSFET with a dual-gate SOI structure can suppress short channel effects (SCE) and leakage induced leakage barriers compared to conventional single-gate Si or SOI MOSFETs.
  • SCE short channel effects
  • DIBL depleted metal bipolar transistor
  • EOT effective gate oxygen Thickness
  • the gate of the tri-gate device surrounds the top surface of the channel region and the two sides, and the gate control capability is stronger. Further, full surround nanowire multi-gate devices are more advantageous.
  • the present invention provides a semiconductor device comprising: a plurality of fins, located in a lining Bottom and extending in the first direction; a plurality of gate stack structures extending in the second direction and spanning each of the fins; a plurality of stress layers in the fins on both sides of the gate stack structure, and in the stress layer There are a plurality of source and drain regions; a plurality of channel regions are located between the plurality of source and drain regions in the first direction; and the plurality of gate stack structures surround the plurality of channel regions.
  • the material of the fin is different from the material of the stress layer.
  • the material of the fin and/or the material of the stress layer are Si, SiGe, SiSn, GeSn, Si:C, Si:H, SiGe:C, and combinations thereof.
  • the gate stack structure comprises a gate insulating layer of a high-k material and a gate conductive layer of a metal material.
  • the cross-sectional shape of the gate stack structure located under the channel region in the second direction is a dome shape, a C shape, a D shape, and a combination thereof.
  • the stress layer and/or source and drain regions comprise SiGe, SiSn, GeSn, Si: C Si:H, SiGe:C, and combinations thereof.
  • the present invention also provides a method of fabricating a semiconductor device, comprising: forming a plurality of fins extending in a first direction on a substrate and a hard mask layer on the fin; forming a second electrode extending and spanning each a plurality of dummy gate stack structures of the fins; forming a stress layer and a stress layer in the fins on both sides of the dummy gate stack structure; depositing the interlayer dielectric layer covering the fins, the stress layer, and the dummy gate stack structure; Removing the dummy gate stack structure, leaving a first gate trench in the interlayer dielectric layer to expose the hard mask layer; etching the fin under the hard mask layer to form a second gate trench, wherein the The fin between the second gate trench and the hard mask layer constitutes a channel region; and a plurality of gate stack structures are deposited in the first and second gate trenches to surround the plurality of channel regions.
  • the material of the fin is different from the material of the stress layer.
  • the material of the fin and/or the material of the stress layer are Si, SiGe, SiSn, GeSn, Si: C, Si: H, SiGe: C, and combinations thereof.
  • the gate stack structure comprises a gate insulating layer of a high-k material and a gate material layer of a metal material.
  • the cross-sectional shape of the second gate trench in the second direction is a dome shape, a C shape, a D shape, and a combination thereof.
  • the stress layer and/or source and drain regions comprise SiGe, SiSn, GeSn, Si:C, Si:H, SiGe:C and combinations thereof.
  • the forming the second gate trench further includes: etching to remove the hard mask layer.
  • the dummy gate stack comprises a pad oxide layer and a dummy gate layer.
  • the step of forming the stress layer and the source and drain regions in the stress layer further comprises: forming a gate spacer on the fins on both sides of the dummy gate stack structure in the first direction; and fins on both sides of the gate sidewall
  • the medium etch forms a source/drain trench; the stress layer is epitaxially deposited in the source and drain trench; the doping is performed at the same time as the stress layer is formed or after the stress layer is formed, and the source and drain regions are formed in the stress layer.
  • the hard mask and the dummy gate are used to form a fully-wound nanowire metal multi-gate in a self-aligned manner by punching through the fin in which the channel region is located, thereby enhancing device performance.
  • FIG. 1A and FIG. 1B to FIG. 8 are schematic cross-sectional views showing respective steps of a FinFET manufacturing method according to the present invention, wherein a certain figure A is a cross-sectional view parallel to the channel direction, and a certain picture B Is a cross-sectional view perpendicular to the direction of the channel;
  • Figure 9 is a perspective view showing the structure of a FinFET device in accordance with the present invention. detailed description
  • FIG. 9 is a perspective view of a FinFET fabricated in accordance with the present invention, wherein the FinFET includes a plurality of fins extending in a first direction, a plurality of metal gates extending in a second direction and spanning each fin, located in the metal A plurality of source and drain regions on the fins on both sides of the gate are located in a plurality of channel regions between the plurality of source and drain regions, wherein the metal gate surrounds the channel region.
  • the FinFET includes a plurality of fins extending in a first direction, a plurality of metal gates extending in a second direction and spanning each fin, located in the metal
  • a plurality of source and drain regions on the fins on both sides of the gate are located in a plurality of channel regions between the plurality of source and drain regions, wherein the metal gate surrounds the channel region.
  • FIG. 9 a certain figure A is a cross-sectional view along the channel direction (in the first direction) in FIG. 9, and a drawing B is a cross-section in the direction perpendicular to the channel (in the second direction) in FIG. Figure.
  • a plurality of fin structures and a hard mask layer extending in a first direction are formed.
  • the village bottom 1 is reasonably selected according to the needs of the device, and may include single crystal silicon (Si), silicon-on-insulator (SOI), single crystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si).
  • Silicon germanium (SiGe), or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, etc.
  • the substrate 1 is preferably bulk Si for compatibility with CMOS processes. Photolithography/etching the substrate 1, forming a plurality of trenches distributed in the first direction in the first direction, depositing silicon oxide, oxynitriding in the trench by PECVD, HDPCVD, RTO (rapid thermal oxidation) An insulating isolation dielectric layer of silicon or the like forms shallow trench isolation (STI) 2.
  • the substrate 1 between the STIs 2 constitutes a fin substrate 1A and a fin channel 1B.
  • Preferred 1A and 1B are the same substrate and are simultaneously formed during the STI etching process.
  • Substrate 1A can be doped to isolate the electrical effects of the channel from the substrate.
  • the spacing between the STIs 2 is, for example, 2 to 50 nm, and the height is, for example, 5 to 500 nm.
  • epitaxial fins 1B are epitaxially grown on the fin substrate 1 A by UHVCVD, MOCVD, MBE, ALD, atmospheric pressure epitaxy, etc., and the material thereof may be the same as that of the substrate 1 (1A), for example, Si, in addition to its material shield can also be other high mobility materials, such as Ge, SiGe, SiGe: (, Si: C, Si: H, SiSn, GeSn, GaAs, InP, GaSb, InAs, InSb, etc.
  • the material of epitaxial fin 1B is preferably Si, SiGe.
  • Fin substrate 1A and fin The patch channels (or epitaxial fins) 1B may together constitute a fin structure.
  • a plurality of fins parallel to each other may be formed, which may be enhanced.
  • the device driving capability and the gate control capability may be Similarly, only one fin is shown in the following figures, but is not limited thereto.
  • the method of forming the fin structure may also be to etch the substrate 1 to form a deeper trench.
  • the Si layer is deposited on the fin structure 1A/1B by conventional methods such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and then etching to form the hard mask layer 3, the material and STI 2 and substrate 1, fin structure 1A / 1B are different, such as silicon nitride, silicon oxynitride, diamond-like amorphous Carbon (DLC), etc. and combinations thereof.
  • DLC diamond-like amorphous Carbon
  • a plurality of dummy gate stack structures extending in a second direction are formed, wherein the second direction intersects the first direction and is preferably perpendicular (orthogonal) such that a plurality of dummy gate stack structures are covered and A portion of the plurality of fin structures is surrounded, that is, a portion of the fin channel 1B above the STI 2.
  • a pad oxide layer 4 is deposited on the entire device by LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, etc., and then deposited on the gate insulating layer 3 by PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and the like.
  • the method forms a dummy gate layer 5 and then a CMP planarization process, the dummy gate layer 5 covering (the top surface and the side surface) of the pad oxide layer 4 and the top surface of the STI 2 .
  • the material of the dummy gate layer 5 may be polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, polycrystalline germanium, amorphous germanium, or the like, and combinations thereof.
  • the fin structures on both sides of the dummy gate stack structure 5/4 (in the first direction) will correspond to the source and drain regions, and the fins surrounded by the dummy gate stack structure 5/4 The structural portion will constitute the channel region.
  • source and drain regions are formed in the fin structures on both sides of the etched dummy gate stack structure.
  • the wall 6 has a material different from that of the dummy gate layer 5, the hard mask layer 3, and the fin structure 1 B, and is, for example, silicon nitride, silicon oxynitride, amorphous carbon, DLC, or the like, and combinations thereof.
  • Source/drain trenches are etched in the fin structures 1B on both sides of the gate stack structure 5/4.
  • a stress layer is epitaxially grown in the source and drain trenches.
  • the embedded stress layer 7 is epitaxially grown in the source/drain trench by epitaxial growth processes such as UHVCVD, MOCVD, ALD, MBE, and atmospheric pressure epitaxy. Among them, the stress layer 7 material can be different for different MOSFET types.
  • the stress layer 7 may be SiGe, SiSn, GeSn, or the like, and combinations thereof, to apply compressive stress to the channel region 1C to improve hole mobility; and for NMOS, the stress layer 7 may be Si : (:, Si: H, SiGe: C, etc., and combinations thereof. Further, the material of the stress layer 7 may be different from the material of the fin channel IB. Wherein, as shown in FIG. 3A, the top of the stress layer 7 is higher than the fin channel 1B/channel region 1C (thus constitutes a boost source and drain, which can effectively reduce the contact resistance) and is lower than the dummy gate layer 5, and this configuration is only For the purpose of illustration, the top height difference can be arbitrarily set.
  • in-situ doping may be performed to adjust the conductivity type of the stress layer 7 in accordance with the MOSFET type, for example, doping phosphorus for the NMOS? , arsenic As, ⁇ Sb, etc., doped with boron B, aluminum Al, gallium Ga, indium In, etc. for PMOS.
  • the time point at which the dopant is added may be controlled such that the doping concentration of the stress layer 7 near the bottom of the fin channel 1B is smaller than that near the top of the fin channel 1B.
  • the concentration, for example, the bottom of the stress layer 7 is not doped in situ and only stress is applied, and the top of the stress layer 7 is doped in situ as the source and drain regions 7A. Further, it is also possible to epitaxially grow the stress layer 7 and then perform ion implantation doping (the implanted ions are the same as the in-situ doping) to form the source and drain regions 7A, while the regions of the 7 regions inside the trench are not doped.
  • the shape of the source/drain trench and the stress layer may not be limited to the rectangular-like, trapezoid-like shape shown in FIG. 3A, but may be a dome shape (having a groove toward the trench in the first direction).
  • the recessed area of the track area, (inverted) trapezoid or triangle can also be a curve, a curved surface, for example, a C shape (the side of the groove facing the side of the channel area is (half or more) circular, elliptical, Sector, etc.) or D-shape (the side of the groove facing the side of the channel region is semi-circular or semi-elliptical).
  • the method of etching the source/drain trench may be a dry-method wet etching, or a separate dry etching or wet etching (by adjusting the etching process parameters).
  • the recess toward the channel region may also be a one-time (or two) etching to form a C-shaped or D-shaped trench by an isotropic dry etching method using a fluorocarbon-based etching gas.
  • the interlayer dielectric layer is formed by covering at least the fins in the first direction, and planarizing until the dummy gate layer is exposed.
  • An interlayer dielectric layer (ILD) 8 is formed on the entire device by spin coating, spray coating, screen printing, etc., and the material thereof is, for example, silicon oxide, silicon oxynitride or a low-k material, and the low-k material includes but is not limited to organic low.
  • k materials such as organic polymers containing aryl or polycyclic rings
  • inorganic low-k materials such as amorphous carbon nitride film, polycrystalline boron nitride film, fluorosilicate glass, BSG, PSG, BPSG
  • porous low-k materials For example, a disilane trioxane (SSQ)-based porous low-k material, porous silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer).
  • SSQ disilane trioxane
  • the ILD 8 is then planarized by conventional methods such as CMP, etchback, etc. until the dummy gate layer 5 is exposed. Referring to FIGS.
  • the dummy gate stack structure is etched away, leaving a first gate trench in the ILD.
  • a suitable etching method is selected, the dummy gate stack structure 5/4 is completely removed, and the first gate trench 8A is left in the ILD 8, exposing the hard mask.
  • the etching method includes, for example, removing the dummy gate layer 5 of a silicon-based material such as polysilicon or amorphous silicon by TMAH wet etching, removing the pad oxide layer 4 of the silicon oxide by using an HF-based etching solution, or using a fluorocarbon-based plasma. Body etching is dry removal.
  • the fin structure is etched in the second direction, and a through gate second gate trench 8B is formed under the hard mask layer 3.
  • the silicon-based fin 1B is wet-etched by TMAH to form a second gate trench 8B under the hard mask layer 3, wherein the remaining fin channel 1B portion under the second gate trench 8B constitutes Channel region 1C, and second gate trench 8B will communicate with first gate trench 8A over hard mask layer 3 in a direction perpendicular to the top surface of the substrate such that gate trench 8A/8B Completely surrounded by the channel region 1C.
  • the shape of the second gate trench may not be limited to the dome shape shown in FIG.
  • the bottom edge faces the channel region) or the triangle (that is, the channel region 1C in FIG. 6A is substantially connected to the remaining fin channel 1B below, the trench 8B only penetrates a small portion), and may also be a curved surface or a curved surface.
  • it is C-shaped (the side of the groove facing one side of the channel region is (half or more) circular, elliptical, fan-shaped, etc.) or D-shaped (the side of the groove facing the side of the channel region is (less than Equal to half) round, oval, fan, etc.).
  • the channel region 1 C is further etched on the basis of the fin channel 1B having a small line, the scale is often 20 nm or less or even 10 nm or less, so it can be regarded as
  • the nanowires, that is, the nanowires, constitute the channel region.
  • the hard mask layer 3 is removed by etching.
  • a hot phosphoric acid or a combination of a strong oxidizing agent and a strong acid (eg, sulfuric acid + hydrogen peroxide)
  • a strong acid eg, sulfuric acid + hydrogen peroxide
  • a gate stack structure 9A/9B is formed in the gate trenches 8A/8B.
  • the gate insulating layer 9A is deposited by PECVD, HDPCVD, MOCVD, MBE, ALD, etc., and may be made of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, or other high-k materials, including but not limited to high-k materials.
  • the oxygen atom content X may be reasonably adjusted, for example, may be 1 to 6 and not limited to an integer, or may be selected from Zr0 2 , La 2 0 3 , LaA10 3 , Ti0. 2 , Y 2 0 3 rare earth-based high-k dielectric material, or a composite layer comprising ⁇ 1 2 0 3 , with the above materials.
  • the gate conductive layer 9B is deposited by PECVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and may be polysilicon, polysilicon, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Metal elements such as Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or alloys of these metals and nitrides of these metals, may also be doped in the gate conductive layer 9B Miscellaneous C, F, N, 0, B, P, As and other elements to adjust the work function.
  • a barrier layer (not shown) of nitride is preferably formed between the gate conductive layer 9B and the gate insulating layer 9A by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z , M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.
  • the ILD 8 is etched to form a source/drain contact hole (not shown); in the source/drain contact hole, a metal layer (not shown) is formed by a process such as evaporation, sputtering, MOCVD, or the like, for example, Ni, Pt, Co, Ti, Ge and its combination are then annealed at a high temperature of 550 to 850 ° C to form a metal silicide and remove the unreacted metal layer, leaving a silicide layer (not shown) in the contact hole on the source/drain region 7A, the material of which is, for example It is CoSi 2 , TiSi 2 NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi in order to reduce the source-drain contact resistance; filling the contact hole with a metal, a metal nitride to form a source/drain contact plug or the
  • the finally formed device structure is as shown in FIG. 9, and includes: a plurality of fins (fin fin channel 1B and fin substrate 1A) extending in the first direction, extending in the second direction (intersecting with the first direction and preferably a plurality of metal gates 9B spanning each fin, a plurality of stress layers 7 on the fins on both sides of the metal gate, and source and drain regions 7A in the stress layer, located in the plurality of source and drain regions A plurality of channel regions 1C are interposed, wherein the metal gate 9B surrounds the channel region 1C.
  • the materials and geometries of the above structures have been described in detail in the method description, and therefore will not be described again.
  • the hard mask and the dummy gate are used to form a fully-wound nanowire metal multi-gate in a self-aligned manner by punching through the fin in which the channel region is located, thereby enhancing device performance.

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Abstract

提供了一种半导体器件，包括：多个鳍片（1A，1B），位于衬底（1）上并且沿第一方向延伸；多个栅极堆叠结构（9A，9B），沿第二方向延伸并且跨越了每个鳍片；多个应力层（7），位于栅极堆叠结构两侧的鳍片中，并且在应力层中具有多个源漏区（7A）；多个沟道区（1C），沿第一方向位于多个源漏区之间；多个栅极堆叠结构环绕包围了多个沟道。还提供了该器件的制造方法。利用硬掩模和假栅结合穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多栅，增强了器件性能。

Description

半导体器件及其制造方法 优先权要求
本申请要求了 2012年 7月 25日提交的、 申请号为 201210260565.4、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件及其制造方法， 特别是涉及一种自对 准多栅纳米线 FET及其制造方法。 背景技术
在当前的亚 20nm技术中， 三维多栅器件（ FinFET或 Tri-gate )是 主要的器件结构， 这种结构增强了栅极控制能力、 抑制了漏电与短沟 道效应。
例如， 双栅 SOI 结构的 MOSFET 与传统的单栅体 Si 或者 SOI MOSFET 相比， 能够抑制短沟道效应 （SCE ) 以及漏致感应势垒降低
( DIBL ) 效应， 具有更低的结电容， 能够实现沟道轻掺杂， 可以通过 设置金属栅极的功函数来调节阔值电压， 能够得到约 2倍的驱动电流， 降低了对于有效栅氧厚度 （EOT ) 的要求。 而三栅器件与双栅器件相 比， 栅极包围了沟道区顶面以及两个侧面， 栅极控制能力更强。 进一 步地， 全环绕纳米线多栅器件更具有优势。
一般的纳米线三维多栅器件需要与金属栅后栅工艺集成以保持性 能优势， 但是这些纳米线多栅器件的制造工艺一般比较复杂， 与主流 工艺不兼容， 特别是难以应用当前流行的 MG (金属材料的栅极） /HK
(高 k 材料的栅极绝缘层）栅极堆叠结构。 这制约了三维多栅器件提 高器件性能的能力。 发明内容
由上所述， 本发明的目的在于克服上述技术困难， 釆用 MG/HK后 栅工艺来制造自对准金属栅多栅纳米线。
为此， 本发明提供了一种半导体器件， 包括： 多个鳍片， 位于衬 底上并且沿第一方向延伸； 多个栅极堆叠结构， 沿第二方向延伸并且 跨越了每个鳍片； 多个应力层， 位于栅极堆叠结构两侧的鳍片中， 并 且在应力层中具有多个源漏区； 多个沟道区， 沿第一方向位于多个源 漏区之间； 其特征在于， 多个栅极堆叠结构环绕包围了多个沟道区。
其中， 鳍片的材质与应力层的材质不同。
其中， 鳍片的材质和 /或应力层的材质为 Si、 SiGe、 SiSn、 GeSn、 Si:C, Si:H、 SiGe:C及其组合。
其中， 栅极堆叠结构包括高 k材料的栅极绝缘层和金属材料的栅极 导电层。
其中， 位于沟道区下方的栅极堆叠结构的沿第二方向的剖面形状 为∑形、 C形、 D形及其组合。
其中， 应力层和 /或源漏区包括 SiGe、 SiSn、 GeSn、 Si:C Si:H、 SiGe:C及其组合。
本发明还提供了一种半导体器件制造方法， 包括： 在衬底上形成 沿笫一方向延伸的多个鳍片以及鳍片上的硬掩模层； 形成沿第二方向 延伸的并且跨越了每个鳍片的多个假栅极堆叠结构； 在假栅极堆叠结 构两侧的鳍片中形成应力层以及应力层中的； 沉积层间介质层覆盖鳍 片、 应力层以及假栅极堆叠结构； 去除假栅极堆叠结构， 在层间介质 层中留下第一栅极沟槽， 暴露出硬掩模层； 刻蚀硬掩模层下方的鳍片， 形成第二栅极沟槽， 其中第二栅极沟槽与硬掩模层之间的鳍片构成沟 道区； 在第一和第二栅极沟槽中沉积形成多个栅极堆叠结构， 环绕包 围了多个沟道区。
其中， 鳍片的材质与应力层的材质不同。
其中， 鳍片的材质和 /或应力层的材质为 Si、 SiGe、 SiSn、 GeSn、 Si:C、 Si:H、 SiGe:C及其组合。
其中， 栅极堆叠结构包括高 k材料的栅极绝缘层和金属材料的栅极 材料层。
其中， 第二栅极沟槽沿第二方向的剖面形状为∑形、 C形、 D形及 其组合。
其中， 应力层和 /或源漏区包括 SiGe、 SiSn、 GeSn、 Si:C, Si:H、 SiGe:C及其组合。
其中， 形成第二栅极沟槽之后还包括： 刻蚀去除硬掩模层。 其中， 假栅极堆叠包括垫氧化层和假栅极层。
其中， 形成应力层以及应力层中的源漏区的步骤进一步包括： 在 假栅极堆叠结构沿笫一方向的两側的鳍片上形成栅极側墙； 在栅极侧 墙两侧的鳍片中刻蚀形成源漏沟槽； 在源漏沟槽中外延沉积形成应力 层； 在形成应力层的同时或者形成应力层之后进行掺杂， 在应力层中 形成源漏区。
依照本发明的半导体器件及其制造方法， 利用硬掩模和假栅结合 穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多 栅， 增强了器件性能。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1 (图 1A以及图 1B ) 至图 8 (图 8A以及图 8B ) 为依照本发明的 FinFET制造方法各步骤的剖面示意图，其中某图 A是沿平行于沟道方向 的剖视图， 某图 B是沿垂直于沟道方向的剖视图； 以及
图 9为依照本发明的 FinFET器件结构的立体示意图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了有效增大沟道区载流子迁移率以提高器 件驱动能力的 FinFET及其制造方法。 需要指出的是， 类似的附图标记 表示类似的结构， 本申请中所用的术语 "第一" 、 "第二，， 、 "上" 、 "下" 等等可用于修饰各种器件结构或制造工序。 这些修饰除非特别 说明并非暗示所修饰器件结构或制造工序的空间、 次序或层级关系。
图 9所示为依照本发明制造的 FinFET的立体示意图，其中 FinFET 包括沿第一方向延伸的多个鳍片， 沿第二方向延伸并且跨越了每个鳍 片的多个金属栅极， 位于金属栅极两侧的鳍片上的多个源漏区， 位于 多个源漏区之间的多个沟道区， 其中金属栅极环绕沟道区。 以下将先 参照图 1 至图 8来描述制造方法的各个剖视图， 最后将回头进一步详 细描述图 9的器件结构。
特别地， 以下某图 A是沿图 9中平行于沟道方向 （沿第一方向） 的剖视图， 某图 B是沿图 9中垂直于沟道方向 （沿第二方向） 的剖视 图。
参照图 1A以及图 1B， 形成沿第一方向延伸的多个鳍片结构以及 硬掩模层。 提供村底 1， 村底 1依照器件用途需要而合理选择， 可包括 单晶体硅（Si ) 、 绝缘体上硅（SOI ) 、 单晶体锗（Ge ) 、 绝缘体上锗 ( GeOI ) 、 应变硅（Strained Si ) 、 锗硅（SiGe ) , 或是化合物半导体 材料， 例如氮化镓（GaN ) 、 砷化镓 （GaAs ) 、 磷化铟 (InP)、 锑化铟 ( InSb ) ,以及碳基半导体例如石墨烯、 SiC、碳纳管等等。出于与 CMOS 工艺兼容的考虑， 衬底 1优选地为体 Si。 光刻 /刻蚀衬底 1 , 在衬底 1 中形成多个沿第一方向平行分布的沟槽， 在沟槽中通过 PECVD、 HDPCVD、 RTO (快速热氧化） 等工艺沉积氧化硅、 氮氧化硅等材质 的绝缘隔离介质层， 从而构成了浅沟槽隔离 （STI ) 2。 STI 2之间的 衬底 1构成了鳍片衬底 1A与鳍片沟道 1B。 优选的 1A与 1B为同一衬 底， 在 STI刻蚀过程中同时形成。 衬底 1A可以进行掺杂以隔离沟道与 衬底的电学影响。 STI 2之间的间距 （也即鳍片村底 1A与 1B的宽度） 例如是 2 ~ 50nm， 其高度度例如是 5 ~ 500nm。 另外一种方法， 通过 UHVCVD, MOCVD、 MBE、 ALD、 常压外延等方法在鳍片衬底 1 A上 外延生长了外延鳍片 1B, 其材质可以是与衬底 1 ( 1A )相同， 例如均 为 Si，此外其材盾也可以是其他高迁移率材料，例如 Ge、 SiGe, SiGe: (、 Si:C、 Si:H、 SiSn、 GeSn、 GaAs, InP、 GaSb、 InAs、 InSb等等。 为了 与 CMOS 以及主流的 HK/MG工艺兼容， 外延鳍片 1B的材质优选为 Si、 SiGe. SiGe:C、 Si:C、 Si:H SiSn、 GeSn并且最佳为 Si。 鳍片衬底 1A以及鳍片沟道 （或者外延鳍片） 1B可以共同构成鳍片结构。 其中， 虽然图 1 中为了方便说明仅示出了一个鳍片， 但是实际上可以形成多 个相互平行的鳍片， 如此可以增强器件驱动能力以及栅控能力。 并且 类似地， 以下各图中也仅示出了一个鳍片， 但是不限于此。 此外， 形 成鳍片结构的方法也可以是刻蚀衬底 1 形成更深的沟槽， 填充一部分 绝缘介质材料而留下垂直突出的鳍片结构； 或者是在 SOI衬底中刻蚀 形成穿透埋氧层直达底 Si层的沟槽， 在沟槽中外延 Si, 然后选择性刻 蚀去除沟槽区域之外的顶 Si 层。 之后， 在鳍片结构 1A/1B 之上通过 LPCVD、 PECVD、 HDPCVD, MOCVD、 MBE、 ALD、 蒸发、 溅射等 常规方法沉积并且随后刻蚀形成硬掩模层 3 ,其材质与 STI 2和衬底 1、 鳍片结构 1A/1B均不同， 例如为氮化硅、 氮氧化硅、 类金刚石无定形 碳 （DLC ) 等及其组合。
参照图 2A以及图 2B, 形成沿第二方向延伸的多个假栅极堆叠结 构， 其中第二方向与第一方向相交并且优选地垂直 （正交） ， 使得多 个假栅极堆叠结构覆盖并且包围了多个鳍片结构的一部分， 也即位于 STI 2 之上的鳍片沟道 1B 部分。 首先在整个器件上通过 LPCVD、 PECVD、 HDPCVD、 RTO、 化学氧化等方法沉积形成垫氧化层 4， 然 后在栅极绝缘层 3上通过 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD、 蒸发、 溅射等沉积方法形成假栅极层 5并且随后 CMP平坦化处理， 假 栅极层 5覆盖了垫氧化层 4 (的顶面以及側面）以及 STI 2 (的顶面） 。 假栅极层 5的材质可以是多晶硅、 非晶硅、 微晶硅、 非晶碳、 多晶锗、 非晶锗等等及其组合。 最后 （沿第一方向） 光刻 /刻蚀假栅极层 5 以及 垫氧化层 4, 去除了对应于未来沟道区之外的叠层， 沿第二方向覆盖包 围了鳍片 1B以及硬掩模层 3的顶面以及两个侧面，仅在未来沟道区（可 以是相互平行的多个） 对应的位置上留下沿第二方向 （与第一方向相 交并且优选地垂直）延伸的多个假栅极堆叠结构 5/4。 其中， 假栅极堆 叠结构 5/4 (沿第一方向上） 两側的鳍片结构 （鳍片沟道 1B ) 将对应 于源漏区， 被假栅极堆叠结构 5/4包围的鳍片结构部分将构成沟道区。
参照图 3A以及图 3B， 刻蚀假栅极堆叠结构两側的鳍片结构中形 成源漏区
刻蚀假栅极堆叠结构 5/4以及下方的硬掩模层 3形成沿第二方向延 伸的线条， 然后在假栅极堆叠结构 5/4 (沿第一方向） 的两侧形成栅极 侧墙 6，其材质与假栅极层 5、硬掩模层 3、鳍片结构 1 B的材质均不同， 例如为氮化硅、 氮氧化硅、 非晶碳、 DLC等等及其组合。
采用干法刻蚀， 例如氟基、 氯基、 氧基的 （反应） 等离子体刻蚀， 或者采用 TMAH (针对 Si ) 或者强酸 /强氧化剂组合 （针对 SiGe等化 合物半导体） 的腐蚀液， 在假栅极堆叠结构 5/4两侧的鳍片结构 1B中 刻蚀形成源漏沟槽 （未示出） 。 在源漏沟槽中外延生长应力层。 通过 UHVCVD、 MOCVD, ALD、 MBE、 常压外延等外延生长工艺， 在上 述源漏沟槽中外延生长了嵌入式的应力层 7。 其中， 对于不同的 MOSFET类型， 应力层 7材质可以不同。 例如， 对于 PMOS而言， 应 力层 7可以是 SiGe、 SiSn、 GeSn等及其组合， 从而向沟道区 1C施加 压应力， 提高空穴迁移率； 而对于 NMOS而言， 应力层 7可以是 Si: (：、 Si:H、 SiGe:C等及其组合。 此外， 应力层 7的材质只要与鳍片沟道 IB 的材质不同即可。 其中， 如图 3A所示， 应力层 7顶部高于鳍片沟道 1B/沟道区 1C (因此构成提升源漏， 可以有效降低接触电阻）并且低于 假栅极层 5,这种配置仅出于示意目的，因此顶部高度差可以任意设定。
优选地， 在外延形成应力层 7 时， 可以进行原位掺杂， 以依照 MOSFET类型而调整应力层 7的导电类型， 例如对于 NMOS而言掺杂 磷？、 砷 As、 锑 Sb等， 对于 PMOS而言掺杂硼 B、 铝 Al、 镓 Ga、 铟 In 等。 此外， 外延生长中进行原位掺杂工艺时， 可以控制掺杂剂加入 的时间点， 以使得应力层 7靠近鳍片沟道 1B底部的掺杂浓度小于靠近 鳍片沟道 1B顶部的掺杂浓度，例如应力层 7底部不进行原位掺杂而仅 施加应力， 应力层 7顶部原位掺杂作为源漏区 7A。 此外， 也可以外延 生长了应力层 7之后再执行离子注入掺杂（注入离子与原位掺杂相同）， 以形成源漏区 7A， 同时 7区在沟道内部的区域不掺杂。
此外， 在本发明的其他实施例中， 源漏沟槽、 应力层的形状可以 不限于图 3A中所示的类矩形、 类梯形， 而是可以为∑形 （在第一方向 上具有朝向沟道区的凹进） 、 （倒）梯形或者三角形， 还可以为曲线、 曲面， 例如为 C形 （沟槽朝向沟道区的一側的側面为 （大于等于一半 的） 圆形、 椭圆形、 扇形等） 或者 D形 （沟槽朝向沟道区的一侧的侧 面为半圆形或者半椭圆形） 。
在本发明其他实施例中， 刻蚀形成源漏沟槽的方法可以是先干法 后湿法刻蚀， 也可以是单独的干法刻蚀或者湿法刻蚀 （通过调整刻蚀 工艺参数获得朝向沟道区的凹进） ， 还可以是采用碳氟基刻蚀气体的 各向同性干法刻蚀方法而一次性 （或者两次） 刻蚀形成 C形或者 D形 的沟槽。
参照图 4A和图 4B, 沿第一方向至少覆盖鳍片而形成层间介质层， 并且平坦化直至暴露假栅极层。 通过旋涂、 喷涂、 丝网印刷等方法， 在整个器件上形成层间介质层 （ILD ) 8， 其材质例如是氧化硅、 氮氧 化硅或低 k材料， 低 k材料包括但不限于有机低 k材料 （例如含芳基 或者多元环的有机聚合物） 、 无机低 k 材料 （例如无定形碳氮薄膜、 多晶硼氮薄膜、 氟硅玻璃、 BSG、 PSG、 BPSG ) 、 多孔低 k材料 （例 如二硅三氧烷 （SSQ )基多孔低 k材料、 多孔二氧化硅、 多孔 SiOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多孔金刚石、 多孔有机聚合物） 。 随后采用 CMP、回刻等常规方法平坦化 ILD 8,直至暴露出假栅极层 5。 参照图 5A和图 5B, 刻蚀去除假栅极堆叠结构， 在 ILD中留下第 一栅极沟槽。 针对假栅极层 5和垫氧化层 4的材质， 选择合适的刻蚀 方法， 完全去除了假栅极堆叠结构 5/4, 在 ILD8中留下第一栅极沟槽 8A, 暴露了硬掩模层 3。 刻蚀方法例如包括， 釆用 TMAH湿法腐蚀去 除多晶硅、 非晶硅等硅基材质的假栅极层 5 , 采用 HF基腐蚀液去除氧 化硅的垫氧化层 4, 或者可以采用碳氟基等离子体刻蚀干法去除。
参照图 6A和图 6B， 沿第二方向刻蚀鳍片结构， 在硬掩模层 3的 下方形成了穿通的第二栅极沟槽 8B。 例如采用 TMAH湿法腐蚀 Si基 材质的鳍片 1B， 形成位于硬掩模层 3下方的第二栅极沟槽 8B , 其中笫 二栅极沟槽 8B下方剩余的鳍片沟道 1B部分构成了沟道区 1C，并且第 二栅极沟槽 8B在垂直于衬底顶面的方向上将与硬掩模层 3上方的第一 栅极沟槽 8A相连通，使得栅极沟槽 8A/8B完全包围环绕了沟道区 1C。 此外， 第二栅极沟槽的形状可以不限于图 6A中所示的∑形（在第一方 向上具有朝向沟道区的凹进， 由多段折线构成） 、 （倒）梯形 （梯形 的短底边朝向沟道区） 或者三角形 （也即图 6A中沟道区 1C与下方的 剩余鳍片沟道 1B基本上相连， 沟槽 8B仅穿通了很小一部分） ， 还可 以为曲线、 曲面， 例如为 C形 （沟槽朝向沟道区的一侧的側面为 （大 于等于一半的） 圆形、 椭圆形、 扇形等） 或者 D形 （沟槽朝向沟道区 的一側的側面为 （小于等于一半的） 圆形、 椭圆形、 扇形等） 。 在此， 由于沟道区 1 C是在本身线条就较小的鳍片沟道 1B的基础上进一步刻 蚀加工而成， 因此其尺度往往在 20nm以下甚至仅 10nm以下， 故其可 以视为或者称作纳米线条， 也即纳米线条构成了沟道区。
参照图 7A和图 7B， 刻蚀去除硬掩模层 3。 采用热磷酸， 或者强氧 化剂和强酸的组合（例如硫酸 +双氧水） ， 去除例如为氮化硅、 氮氧化 硅材质的硬掩模层 3， 使得图 6A、 6B中的两个栅极沟槽 8A、 8B进一 步相连， 完全包围了纳米线条的沟道区 1C。
参照图 8A 和图 8B， 在栅极沟槽 8A/8B 中形成栅极堆叠结构 9A/9B。 通过 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD等方法沉积 栅极绝缘层 9A, 其材质可以是氧化硅、 掺氮氧化硅、 氮化硅、 或其它 高 K材料， 高 k材料包括但不限于包括选自 Hf02、 HfSiOx、 HfSiON, HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基村料（其中， 各材料依照多元金属组分配比以及化学价不同， 氧原子含量 X 可合理 调整， 例如可为 1 ~ 6且不限于整数） ， 或是包括选自 Zr02、 La203、 LaA103、 Ti02、 Y203的稀土基高 K介质材料， 或是包括 Α1203, 以其 上述材料的复合层。 通过 PECVD、 MOCVD, MBE、 ALD、 蒸发、 溅 射等方法沉积栅极导电层 9B， 可为多晶硅、 多晶锗硅、 或金属， 其中 金属可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 Ir、 Eu、 Nd、 Er、 La 等金属单质、 或这些金属的合金以及这 些金属的氮化物， 栅极导电层 9B中还可掺杂有 C、 F、 N、 0、 B、 P、 As等元素以调节功函数。栅极导电层 9B与栅极绝缘层 9A之间还优选 通过 PVD、 CVD、 ALD等常规方法形成氮化物的阻挡层 （未示出） ， 阻挡层材质为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz, 其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W或其它元素。
此后， 可以采用现有工艺， 继续完成器件制造。 例如刻蚀 ILD 8 形成源漏接触孔（未示出）； 在源漏接触孔中通过蒸发、溅射、 MOCVD 等工艺形成金属层（未示出）， 例如为 Ni、 Pt、 Co、 Ti、 Ge及其组合， 随后在 550 ~ 850°C下高温退火形成金属硅化物并且去除未反应的金属 层， 在源漏区 7A上接触孔中留下硅化物层（未示出） ， 其材质例如为 CoSi2、 TiSi2 NiSi、 PtSi、 NiPtSi、 CoGeSi, TiGeSi、 NiGeSi, 以便 降低源漏接触电阻； 在接触孔中填充金属、 金属氮化物形成源漏接触 塞等等。
最终形成的器件结构如图 9 所示， 包括： 沿第一方向延伸的多个 鳍片 （鳍片沟道 1B以及鳍片衬底 1A ) , 沿第二方向延伸 （与第一方 向相交并且优选地垂直） 并且跨越了每个鳍片的多个金属栅极 9B, 位 于金属栅极两侧的鳍片上的多个应力层 7 以及位于应力层中的源漏区 7A, 位于多个源漏区之间的多个沟道区 1C, 其中金属栅极 9B环绕沟 道区 1C。 上述这些结构的材料和几何形状已在方法描述中详述， 因此 在此不再赘述。
依照本发明的半导体器件及其制造方法， 利用硬掩模和假栅结合 穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多 栅， 增强了器件性能。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出备种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件， 包括：
多个鳍片， 位于衬底上并且沿第一方向延伸；
多个栅极堆叠结构， 沿第二方向延伸并且跨越了每个鳍片； 多个应力层， 位于栅极堆叠结构两侧的鳍片中， 并且在应力层中 具有多个源漏区；
多个沟道区， 沿第一方向位于多个源漏区之间；
其特征在于， 多个栅极堆叠结构环绕包围了多个沟道区。
2. 如权利要求 1的半导体器件， 其中， 鳍片的材质与应力层的材质 不同。
3. 如权利要求 2的半导体器件， 其中， 鳍片的材质和 /或应力层的 材质为 Si、 SiGe、 SiSn、 GeSn> Si:C、 Si:H、 SiGe:C及其组合。
4. 如权利要求 1的半导体器件， 其中， 栅极堆叠结构包括高 k材料 的栅极绝缘层和金属材料的栅极导电层。
5. 如权利要求 1的半导体器件， 其中， 位于沟道区下方的栅极堆叠 结构的沿笫二方向的剖面形状为∑形、 C形、 D形及其组合。
6. 如权利要求 1的半导体器件， 其中， 应力层和 /或源漏区包括 SiGe, SiSn、 GeSn、 Si:C Si:H、 SiGe:C及其组合。
7. 一种半导体器件制造方法， 包括：
在村底上形成沿第一方向延伸的多个鳍片以及鳍片上的硬掩模 层；
形成沿第二方向延伸的并且跨越了每个鳍片的多个假栅极堆叠结 构；
在假栅极堆叠结构两側的鳍片中形成应力层以及应力层中的源漏 区；
沉积层间介质层覆盖鳍片、 应力层以及假栅极堆叠结构； 去除假栅极堆叠结构， 在层间介质层中留下第一栅极沟槽， 暴露 出硬掩模层；
刻蚀硬掩模层下方的鳍片， 形成第二栅极沟槽， 其中第二栅极沟 槽与硬掩模层之间的鳍片构成沟道区；
在笫一和笫二栅极沟槽中沉积形成多个栅极堆叠结构， 环绕包围 了多个沟道区。
8. 如权利要求 7的半导体器件制造方法， 其中， 鳍片的材质与应力 层的材质不同。
9. 如权利要求 8的半导体器件制造方法， 其中， 鳍片的材质和 /或 应力层的材质为 Si、 SiGe、 SiSn、 GeSn、 Si:C、 Si:H SiGe:C及其组合。
10. 如权利要求 7的半导体器件制造方法， 其中， 栅极堆叠结构包 括高 k材料的栅极绝缘层和金属材料的栅极材料层。
11. 如权利要求 7的半导体器件制造方法， 其中， 第二栅极沟槽沿 第二方向的剖面形状为∑形、 C形、 D形及其组合。
12. 如权利要求 7的半导体器件制造方法， 其中， 应力层和 /或源漏 区包括 SiGe、 SiSn GeSn、 Si:C, Si:H、 SiGe.C及其组合。
13. 如权利要求 7的半导体器件制造方法， 其中， 形成第二栅极沟 槽之后还包括： 刻蚀去除硬掩模层。
14. 如权利要求 7的半导体器件制造方法， 其中， 假栅极堆叠包括 垫氧化层和假栅极层。
15. 如权利要求 7的半导体器件制造方法， 其中， 形成应力层以及 应力层中的源漏区的步骤进一步包括：
在假栅极堆叠结构沿第一方向的两侧的鳍片上形成栅极侧墙； 在栅极側墙两侧的鳍片中刻蚀形成源漏沟槽；
在源漏沟槽中外延沉积形成应力层；
在形成应力层的同时或者形成应力层之后进行掺杂， 在应力层中 形成源漏区。
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