CN103579315A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN103579315A CN103579315A CN201210260565.4A CN201210260565A CN103579315A CN 103579315 A CN103579315 A CN 103579315A CN 201210260565 A CN201210260565 A CN 201210260565A CN 103579315 A CN103579315 A CN 103579315A
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明公开了一种半导体器件,包括:多个鳍片,位于衬底上并且沿第一方向延伸;多个栅极堆叠结构,沿第二方向延伸并且跨越了每个鳍片;多个应力层,位于栅极堆叠结构两侧的鳍片中,并且在应力层中具有多个源漏区;多个沟道区,沿第一方向位于多个源漏区之间;其特征在于,多个栅极堆叠结构环绕包围了多个沟道区。依照本发明的半导体器件及其制造方法,利用硬掩模和假栅结合穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多栅,增强了器件性能。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,特别是涉及一种自对准多栅纳米线FET及其制造方法。
背景技术
在当前的亚20nm技术中,三维多栅器件(FinFET或Tri-gate)是主要的器件结构,这种结构增强了栅极控制能力、抑制了漏电与短沟道效应。
例如,双栅SOI结构的MOSFET与传统的单栅体Si或者SOI MOSFET相比,能够抑制短沟道效应(SCE)以及漏致感应势垒降低(DIBL)效应,具有更低的结电容,能够实现沟道轻掺杂,可以通过设置金属栅极的功函数来调节阈值电压,能够得到约2倍的驱动电流,降低了对于有效栅氧厚度(EOT)的要求。而三栅器件与双栅器件相比,栅极包围了沟道区顶面以及两个侧面,栅极控制能力更强。进一步地,全环绕纳米线多栅器件更具有优势。
一般的纳米线三维多栅器件需要与金属栅后栅工艺集成以保持性能优势,但是这些纳米线多栅器件的制造工艺一般比较复杂,与主流工艺不兼容,特别是难以应用当前流行的MG(金属材料的栅极)/HK(高k材料的栅极绝缘层)栅极堆叠结构。这制约了三维多栅器件提高器件性能的能力。
发明内容
由上所述,本发明的目的在于克服上述技术困难,采用MG/HK后栅工艺来制造自对准金属栅多栅纳米线。
为此,本发明提供了一种半导体器件,包括:多个鳍片,位于衬底上并且沿第一方向延伸;多个栅极堆叠结构,沿第二方向延伸并且跨越了每个鳍片;多个应力层,位于栅极堆叠结构两侧的鳍片中,并且在应力层中具有多个源漏区;多个沟道区,沿第一方向位于多个源漏区之间;其特征在于,多个栅极堆叠结构环绕包围了多个沟道区。
其中,鳍片的材质与应力层的材质不同。
其中,鳍片的材质和/或应力层的材质为Si、Si Ge、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
其中,栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极导电层。
其中,位于沟道区下方的栅极堆叠结构的沿第二方向的剖面形状为∑形、C形、D形及其组合。
其中,应力层和/或源漏区包括SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
本发明还提供了一种半导体器件制造方法,包括:在衬底上形成沿第一方向延伸的多个鳍片以及鳍片上的硬掩模层;形成沿第二方向延伸的并且跨越了每个鳍片的多个假栅极堆叠结构;在假栅极堆叠结构两侧的鳍片中形成应力层以及应力层中的;沉积层间介质层覆盖鳍片、应力层以及假栅极堆叠结构;去除假栅极堆叠结构,在层间介质层中留下第一栅极沟槽,暴露出硬掩模层;刻蚀硬掩模层下方的鳍片,形成第二栅极沟槽,其中第二栅极沟槽与硬掩模层之间的鳍片构成沟道区;在第一和第二栅极沟槽中沉积形成多个栅极堆叠结构,环绕包围了多个沟道区。
其中,鳍片的材质与应力层的材质不同。
其中,鳍片的材质和/或应力层的材质为Si、SiGe、SiSn、GeSn、Si∶C、Si∶H、Si Ge∶C及其组合。
其中,栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极材料层。
其中,第二栅极沟槽沿第二方向的剖面形状为∑形、C形、D形及其组合。
其中,应力层和/或源漏区包括SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
其中,形成第二栅极沟槽之后还包括:刻蚀去除硬掩模层。
其中,假栅极堆叠包括垫氧化层和假栅极层。
其中,形成应力层以及应力层中的源漏区的步骤进一步包括:在假栅极堆叠结构沿第一方向的两侧的鳍片上形成栅极侧墙;在栅极侧墙两侧的鳍片中刻蚀形成源漏沟槽;在源漏沟槽中外延沉积形成应 力层;在形成应力层的同时或者形成应力层之后进行掺杂,在应力层中形成源漏区。
依照本发明的半导体器件及其制造方法,利用硬掩模和假栅结合穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多栅,增强了器件性能。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1A以及图1B、图2A以及图2B、图3A以及图3B、图4A以及图4B、图5A以及图5B、图6A以及图6B、图7A以及图7B、图8A以及图8B分别为依照本发明的FinFET制造方法各步骤的剖面示意图,其中的各图A是沿平行于沟道方向的剖视图,各图B是沿垂直于沟道方向的剖视图;以及
图9为依照本发明的FinFET器件结构的立体示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了有效增大沟道区载流子迁移率以提高器件驱动能力的FinFET及其制造方法。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
图9所示为依照本发明制造的FinFET的立体示意图,其中FinFET包括沿第一方向延伸的多个鳍片,沿第二方向延伸并且跨越了每个鳍片的多个金属栅极,位于金属栅极两侧的鳍片上的多个源漏区,位于多个源漏区之间的多个沟道区,其中金属栅极环绕沟道区。以下将先参照图1至图8来描述制造方法的各个剖视图,最后将回头进一步详细描述图9的器件结构。
特别地,以下某图A是沿图9中平行于沟道方向(沿第一方向)的剖视图,某图B是沿图9中垂直于沟道方向(沿第二方向)的剖视图。
参照图1A以及图1B,形成沿第一方向延伸的多个鳍片结构以及硬掩模层。提供衬底1,衬底1依照器件用途需要而合理选择,可包括单晶体硅(Si)、绝缘体上硅(SOI)、单晶体锗(Ge)、绝缘体上锗(GeOI)、应变硅(Strained Si)、锗硅(SiGe),或是化合物半导体材料,例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)、 锑化铟(InSb),以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑,衬底1优选地为体Si。光刻/刻蚀衬底1,在衬底1中形成多个沿第一方向平行分布的沟槽,在沟槽中通过PECVD、HDPCVD、RTO(快速热氧化)等工艺沉积氧化硅、氮氧化硅等材质的绝缘隔离介质层,从而构成了浅沟槽隔离(STI)2。STI2之间的衬底1构成了鳍片衬底1A与鳍片沟道1B。优选的1A与1B为同一衬底,在STI刻蚀过程中同时形成。衬底1A可以进行掺杂以隔离沟道与衬底的电学影响。STI2之间的间距(也即鳍片衬底1A与1B的宽度)例如是2~50nm,其高度度例如是5~500nm。另外一种方法,通过UHVCVD、MOCVD、MBE、ALD、常压外延等方法在鳍片衬底1A上外延生长了外延鳍片1B,其材质可以是与衬底1(1A)相同,例如均为S i,此外其材质也可以是其他高迁移率材料,例如Ge、SiGe、SiGe∶C、Si∶C、Si∶H、SiSn、GeSn、GaAs、InP、GaSb、InAs、InSb等等。为了与CMOS以及主流的HK/MG工艺兼容,外延鳍片1B的材质优选为Si、SiGe、SiGe∶C、Si∶C、Si∶H、Si Sn、GeSn并且最佳为Si。鳍片衬底1A以及鳍片沟道(或者外延鳍片)1B可以共同构成鳍片结构。其中,虽然图1中为了方便说明仅示出了一个鳍片,但是实际上可以形成多个相互平行的鳍片,如此可以增强器件驱动能力以及栅控能力。并且类似地,以下各图中也仅示出了一个鳍片,但是不限于此。此外,形成鳍片结构的方法也可以是刻蚀衬底1形成更深的沟槽,填充一部分绝缘介质材料而留下垂直突出的鳍片结构;或者是在SOI衬底中刻蚀形成穿透埋氧层直达底Si层的沟槽,在沟槽中外延Si,然后选择性刻蚀去除沟槽区域之外的顶Si层。之后,在鳍片结构1A/1B之上通过LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规方法沉积并且随后刻蚀形成硬掩模层3,其材质与STI2和衬底1、鳍片结构1A/1B均不同,例如为氮化硅、氮氧化硅、类金刚石无定形碳(DLC)等及其组合。
参照图2A以及图2B,形成沿第二方向延伸的多个假栅极堆叠结构,其中第二方向与第一方向相交并且优选地垂直(正交),使得多个假栅极堆叠结构覆盖并且包围了多个鳍片结构的一部分,也即位于STI2之上的鳍片沟道1B部分。首先在整个器件上通过LPCVD、PECVD、HDPCVD、RTO、化学氧化等方法沉积形成垫氧化层4,然后在栅极绝缘层3上通过PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等沉积方法形成假栅极层5并且随后CMP平坦化处理,假栅极层5覆盖了垫氧化层4(的顶面以及侧面)以及STI2(的顶面)。假栅极层5的 材质可以是多晶硅、非晶硅、微晶硅、非晶碳、多晶锗、非晶锗等等及其组合。最后(沿第一方向)光刻/刻蚀假栅极层5以及垫氧化层4,去除了对应于未来沟道区之外的叠层,沿第二方向覆盖包围了鳍片1B以及硬掩模层3的顶面以及两个侧面,仅在未来沟道区(可以是相互平行的多个)对应的位置上留下沿第二方向(与第一方向相交并且优选地垂直)延伸的多个假栅极堆叠结构5/4。其中,假栅极堆叠结构5/4(沿第一方向上)两侧的鳍片结构(鳍片沟道1B)将对应于源漏区,被假栅极堆叠结构5/4包围的鳍片结构部分将构成沟道区。
参照图3A以及图3B,刻蚀假栅极堆叠结构两侧的鳍片结构中形成源漏区。
刻蚀假栅极堆叠结构5/4以及下方的硬掩模层3形成沿第二方向延伸的线条,然后在假栅极堆叠结构5/4(沿第一方向)的两侧形成栅极侧墙6,其材质与假栅极层5、硬掩模层3、鳍片结构1B的材质均不同,例如为氮化硅、氮氧化硅、非晶碳、DLC等等及其组合。
采用干法刻蚀,例如氟基、氯基、氧基的(反应)等离子体刻蚀,或者采用TMAH(针对Si)或者强酸/强氧化剂组合(针对SiGe等化合物半导体)的腐蚀液,在假栅极堆叠结构5/4两侧的鳍片结构1B中刻蚀形成源漏沟槽(未示出)。在源漏沟槽中外延生长应力层。通过UHVCVD、MOCVD、ALD、MBE、常压外延等外延生长工艺,在上述源漏沟槽中外延生长了嵌入式的应力层7。其中,对于不同的MOSFET类型,应力层7材质可以不同。例如,对于PMOS而言,应力层7可以是SiGe、SiSn、GeSn等及其组合,从而向沟道区1C施加压应力,提高空穴迁移率;而对于NMOS而言,应力层7可以是Si∶C、Si∶H、SiGe∶C等及其组合。此外,应力层7的材质只要与鳍片沟道1B的材质不同即可。其中,如图3A所示,应力层7顶部高于鳍片沟道1B/沟道区1C(因此构成提升源漏,可以有效降低接触电阻)并且低于假栅极层5,这种配置仅出于示意目的,因此顶部高度差可以任意设定。
优选地,在外延形成应力层7时,可以进行原位掺杂,以依照MOSFET类型而调整应力层7的导电类型,例如对于NMOS而言掺杂磷P、砷As、锑Sb等,对于PMOS而言掺杂硼B、铝Al、镓Ga、铟In等。此外,外延生长中进行原位掺杂工艺时,可以控制掺杂剂加入的时间点,以使得应力层7靠近鳍片沟道1B底部的掺杂浓度小于靠近鳍片沟道1B顶部的掺杂浓度,例如应力层7底部不进行原位掺杂而仅施加应力,应力层7顶部原位掺杂作为源漏区7A。此外,也可以外延生长了应力层7之后再执行离子注入掺杂(注入离子与原位掺杂相 同),以形成源漏区7A,同时7区在沟道内部的区域不掺杂。
此外,在本发明的其他实施例中,源漏沟槽、应力层的形状可以不限于图3A中所示的类矩形、类梯形,而是可以为∑形(在第一方向上具有朝向沟道区的凹进)、(倒)梯形或者三角形,还可以为曲线、曲面,例如为C形(沟槽朝向沟道区的一侧的侧面为(大于等于一半的)圆形、椭圆形、扇形等)或者D形(沟槽朝向沟道区的一侧的侧面为半圆形或者半椭圆形)。
在本发明其他实施例中,刻蚀形成源漏沟槽的方法可以是先干法后湿法刻蚀,也可以是单独的干法刻蚀或者湿法刻蚀(通过调整刻蚀工艺参数获得朝向沟道区的凹进),还可以是采用碳氟基刻蚀气体的各向同性干法刻蚀方法而一次性(或者两次)刻蚀形成C形或者D形的沟槽。
参照图4A和图4B,沿第一方向至少覆盖鳍片而形成层间介质层,并且平坦化直至暴露假栅极层。通过旋涂、喷涂、丝网印刷等方法,在整个器件上形成层间介质层(ILD)8,其材质例如是氧化硅、氮氧化硅或低k材料,低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。随后采用CMP、回刻等常规方法平坦化ILD8,直至暴露出假栅极层5。
参照图5A和图5B,刻蚀去除假栅极堆叠结构,在ILD中留下第一栅极沟槽。针对假栅极层5和垫氧化层4的材质,选择合适的刻蚀方法,完全去除了假栅极堆叠结构5/4,在ILD8中留下第一栅极沟槽8A,暴露了硬掩模层3。刻蚀方法例如包括,采用TMAH湿法腐蚀去除多晶硅、非晶硅等硅基材质的假栅极层5,采用HF基腐蚀液去除氧化硅的垫氧化层4,或者可以采用碳氟基等离子体刻蚀干法去除。
参照图6A和图6B,沿第二方向刻蚀鳍片结构,在硬掩模层3的下方形成了穿通的第二栅极沟槽8B。例如采用TMAH湿法腐蚀Si基材质的鳍片1B,形成位于硬掩模层3下方的第二栅极沟槽8B,其中第二栅极沟槽8B下方剩余的鳍片沟道1B部分构成了沟道区1C,并且第二栅极沟槽8B在垂直于衬底顶面的方向上将与硬掩模层3上方的第一栅极沟槽8A相连通,使得栅极沟槽8A/8B完全包围环绕了沟道区1C。此外,第二栅极沟槽的形状可以不限于图6A中所示的∑形(在第一方向上具有朝向沟道区的凹进,由多段折线构成)、(倒)梯形 (梯形的短底边朝向沟道区)或者三角形(也即图6A中沟道区1C与下方的剩余鳍片沟道1B基本上相连,沟槽8B仅穿通了很小一部分),还可以为曲线、曲面,例如为C形(沟槽朝向沟道区的一侧的侧面为((大于等于一半的)圆形、椭圆形、扇形等)或者D形(沟槽朝向沟道区的一侧的侧面为(小于等于一半的)圆形、椭圆形、扇形等)。在此,由于沟道区1C是在本身线条就较小的鳍片沟道1B的基础上进一步刻蚀加工而成,因此其尺度往往在20nm以下甚至仅10nm以下,故其可以视为或者称作纳米线条,也即纳米线条构成了沟道区。
参照图7A和图7B,刻蚀去除硬掩模层3。采用热磷酸,或者强氧化剂和强酸的组合(例如硫酸+双氧水),去除例如为氮化硅、氮氧化硅材质的硬掩模层3,使得图6A、6B中的两个栅极沟槽8A、8B进一步相连,完全包围了纳米线条的沟道区1C。
参照图8A和图8B,在栅极沟槽8A/8B中形成栅极堆叠结构9A/9B。通过PECVD、HDPCVD、MOCVD、MBE、ALD等方法沉积栅极绝缘层9A,其材质可以是氧化硅、掺氮氧化硅、氮化硅、或其它高K材料,高k材料包括但不限于包括选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料(其中,各材料依照多元金属组分配比以及化学价不同,氧原子含量x可合理调整,例如可为1~6且不限于整数),或是包括选自ZrO2、La2O3、LaAlO3、TiO2、Y2O3的稀土基高K介质材料,或是包括Al2O3,以其上述材料的复合层。通过PECVD、MOCVD、MBE、ALD、蒸发、溅射等方法沉积栅极导电层9B,可为多晶硅、多晶锗硅、或金属,其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物,栅极导电层9B中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。栅极导电层9B与栅极绝缘层9A之间还优选通过PVD、CVD、ALD等常规方法形成氮化物的阻挡层(未示出),阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz,其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。
此后,可以采用现有工艺,继续完成器件制造。例如刻蚀ILD8形成源漏接触孔(未示出);在源漏接触孔中通过蒸发、溅射、MOCVD等工艺形成金属层(未示出),例如为Ni、Pt、Co、Ti、Ge及其组合,随后在550~850℃下高温退火形成金属硅化物并且去除未反应的金属层,在源漏区7A上接触孔中留下硅化物层(未示出),其材质例如为CoSi2、TiSi2、NiSi、PtSi、NiPtSi、CoGeSi、TiGeSi、NiGeSi,以便降低源漏接触电阻;在接触孔中填充金属、金属氮化物形成源漏 接触塞等等。
最终形成的器件结构如图9所示,包括:沿第一方向延伸的多个鳍片(鳍片沟道1B以及鳍片衬底1A),沿第二方向延伸(与第一方向相交并且优选地垂直)并且跨越了每个鳍片的多个金属栅极9B,位于金属栅极两侧的鳍片上的多个应力层7以及位于应力层中的源漏区7A,位于多个源漏区之间的多个沟道区1C,其中金属栅极9B环绕沟道区1C。上述这些结构的材料和几何形状已在方法描述中详述,因此在此不再赘述。
依照本发明的半导体器件及其制造方法,利用硬掩模和假栅结合穿通腐蚀了沟道区所在的鳍片而自对准地形成了全环绕纳米线金属多栅,增强了器件性能。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (15)
1.一种半导体器件,包括:
多个鳍片,位于衬底上并且沿第一方向延伸;
多个栅极堆叠结构,沿第二方向延伸并且跨越了每个鳍片;
多个应力层,位于栅极堆叠结构两侧的鳍片中,并且在应力层中具有多个源漏区;
多个沟道区,沿第一方向位于多个源漏区之间;
其特征在于,多个栅极堆叠结构环绕包围了多个沟道区。
2.如权利要求1的半导体器件,其中,鳍片的材质与应力层的材质不同。
3.如权利要求2的半导体器件,其中,鳍片的材质和/或应力层的材质为Si、SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
4.如权利要求1的半导体器件,其中,栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极导电层。
5.如权利要求1的半导体器件,其中,位于沟道区下方的栅极堆叠结构的沿第二方向的剖面形状为∑形、C形、D形及其组合。
6.如权利要求1的半导体器件,其中,应力层和/或源漏区包括SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
7.一种半导体器件制造方法,包括:
在衬底上形成沿第一方向延伸的多个鳍片以及鳍片上的硬掩模层;
形成沿第二方向延伸的并且跨越了每个鳍片的多个假栅极堆叠结构;
在假栅极堆叠结构两侧的鳍片中形成应力层以及应力层中的源漏区;
沉积层间介质层覆盖鳍片、应力层以及假栅极堆叠结构;
去除假栅极堆叠结构,在层间介质层中留下第一栅极沟槽,暴露出硬掩模层;
刻蚀硬掩模层下方的鳍片,形成第二栅极沟槽,其中第二栅极沟槽与硬掩模层之间的鳍片构成沟道区;
在第一和第二栅极沟槽中沉积形成多个栅极堆叠结构,环绕包围了多个沟道区。
8.如权利要求7的半导体器件制造方法,其中,鳍片的材质与应力层的材质不同。
9.如权利要求8的半导体器件制造方法,其中,鳍片的材质和/或应力层的材质为Si、SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
10.如权利要求7的半导体器件制造方法,其中,栅极堆叠结构包括高k材料的栅极绝缘层和金属材料的栅极材料层。
11.如权利要求7的半导体器件制造方法,其中,第二栅极沟槽沿第二方向的剖面形状为∑形、C形、D形及其组合。
12.如权利要求7的半导体器件制造方法,其中,应力层和/或源漏区包括SiGe、SiSn、GeSn、Si∶C、Si∶H、SiGe∶C及其组合。
13.如权利要求7的半导体器件制造方法,其中,形成第二栅极沟槽之后还包括:刻蚀去除硬掩模层。
14.如权利要求7的半导体器件制造方法,其中,假栅极堆叠包括垫氧化层和假栅极层。
15.如权利要求7的半导体器件制造方法,其中,形成应力层以及应层中的源漏区的步骤进一步包括:
在假栅极堆叠结构沿第一方向的两侧的鳍片上形成栅极侧墙;
在栅极侧墙两侧的鳍片中刻蚀形成源漏沟槽;
在源漏沟槽中外延沉积形成应力层;
在形成应力层的同时或者形成应力层之后进行掺杂,在应力层中形成源漏区。
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