CN107527801A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN107527801A CN107527801A CN201710456366.3A CN201710456366A CN107527801A CN 107527801 A CN107527801 A CN 107527801A CN 201710456366 A CN201710456366 A CN 201710456366A CN 107527801 A CN107527801 A CN 107527801A
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
本发明的实施例公开了一种半导体器件以及形成半导体器件的方法。牺牲薄膜用于图案化对半导体结构的接触件,例如对晶体管的源极/漏极区的接触件。接触件可以包括沿平行于栅电极的轴线的锥形轮廓,以使在接触件远离源极/漏极区延伸时接触件的最外侧宽度减小。
Description
技术领域
本发明的实施例涉及半导体领域,并且更具体地,涉及半导体器件及其形成方法。
背景技术
金属氧化物半导体场效应晶体管(FET或MOSFET)在集成电路(IC)中广泛使用。为了增加在IC中的MOSFET的密度,诸如MOSFET的栅极长度LG的物理尺寸显著地减小。具有短LG的MOSFET可能遭受不希望的短沟道效应(SCE),例如,高断开状态漏电流和高漏感势垒降低。
为了抑制具有短栅极长度LG的晶体管中的SCE,可以采用多栅极场效应晶体管(MuGFET)体系结构。与平面器件结构相比,MuGFET通过栅电极具有更好的沟道电势静电控制。MuGFET包括诸如双栅极晶体管和三栅极或三重栅极晶体管的示例。双栅极晶体管也被称为双栅极FinFET。三栅极晶体管也被称为三栅极FinFET或仅仅是FinFET。双栅极或三栅极器件采用类似于鳍的沟道。导通状态或饱和驱动电流IDsat在鳍中流动,以实现单位占用空间或布局面积的高电流密度。
其他MuGFET包括pi栅极、omega栅极、环绕型栅极(SG)或全包围型栅极(GAA)结构,其中静电栅极控制进一步提升。SG晶体管具有与纳米线相似的沟道,其中纳米线可以水平或竖直定位。对于水平纳米线晶体管,多个水平定位的纳米线沟道可以竖直堆叠。
发明内容
根据本发明的实施例,提供了一种形成半导体器件的方法。该方法包括:在鳍的源极/漏极区和与鳍相邻的隔离区的上方形成牺牲薄膜;移除牺牲薄膜的在隔离区上方的第一部分以形成第一凹口,保留牺牲薄膜的在源极/漏极区上方的第二部分;以及在第一凹口中形成介电层。该方法还包括移除牺牲薄膜的第二部分以形成第二凹口以及在第二凹口中形成导电层。
根据本发明的实施例,提供了一种形成半导体器件的方法。该方法包括:在半导体结构上方形成第一栅电极和第二栅电极;在第一栅电极和第二栅电极之间形成第一牺牲薄膜;以及图案化第一牺牲薄膜以使第一牺牲薄膜的剩余部分保留在半导体结构的上方并且使得第一凹口在第一牺牲薄膜的剩余部分的相对侧上形成在第一栅电极和述栅第二电极之间。该方法还包括在第一凹口中形成层间电介质(ILD);移除第一牺牲薄膜的剩余部分以形成第二凹口;以及在第二凹口中形成导电部件。
根据本发明的实施例,提供了一种半导体器件。该半导体器件包括:在半导体结构上方的栅电极,半导体结构具有第一源极/漏极区、第二源极/漏极区以及介于第一源极/漏极区和第二源极/漏极区之间的沟道区,栅电极位于沟道区上方;在栅电极上方的栅极掩模;沿栅电极和栅极掩模的侧壁的侧壁间隔件,其中,侧壁间隔件的上部表面从栅极掩模的上部表面凹陷。该半导体器件还包括与侧壁间隔件相邻的接触件,接触件电连接至第一源极/漏极区,其中接触件接触栅极掩模的上部部分的侧壁。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本公开的各方面。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1A至图13D示出根据一些实施例的制造过程中的各种中间过程步骤。
图14A至图17B示出了可以与其他公开的实施例结合使用的各种视图。
图18A至图28D示出了根据一些实施例的制造过程中的各种中间过程步骤。
具体实施方式
可以理解,为了实施本发明,本公开提供了许多实施例或示例。以下描述了具体的示例,但并不意在限定。为了实施本发明的不同部件,以下公开提供许多不同的实施例或示例。以下描述了元件和布置的具体示例以简化本公开。当然,这些仅仅是示例并不意在限定。例如,在以下的描述中,第一部件形成在第二部件上方可以包括第一部件和第二部件以直接接触形成的实施例,并且也可包括其中额外的部件形成第一部件和第二部件之间的实施例,使得第一部件和第二部件不直接接触。另外,本公开可能在各个示例中重复参考数字和/或字母。这种重复只是为了简明和清晰的目的且其本身并不指定各个实施例和/或所讨论的结构之间的关系。
进一步地,在此处可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对位置术语,以描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且因此可以对本文中使用的空间相对位置描述符作同样地解释。
公开的实施例涉及一种形成用于多栅极场效应晶体管的接触件的方法,包括形成自对准接触件以及降低具有金属栅电极的这种装置的栅极与接触件之间的边缘电容的方法。诸如此处公开的实施例通常适用于双栅极或三栅极FinFET、环绕栅极或栅极完全包围晶体管和/或纳米线晶体管。
如下文更详细描述,被公开的实施例提供工艺流程以集成用于多栅极场效应晶体管或MuGFET(双栅极、三栅极FinFET、以及水平完全包围栅极晶体管)的金属栅电极和自对准接触件,但是其也可以应用于其他结构。被公开的实施例可以在用于多栅极场效应晶体管或MuGFET(双栅极、三栅极FinFETs以及水平完全包围栅极晶体管)的金属栅极和接触件之间提供降低的边缘电容。
为了说明的目的,附图和以下讨论涉及一个鳍和三个栅极。然而,需要注意的是,在其他实施例中,也可以使用更多鳍和更少或更多的栅极。此外,也可以使用其他结构。例如,可以结合相邻鳍的外延区以形成单个更大的源极/漏极区。
图1A至图13C是根据一些实施例的制造FinFET和各自接触件的中间阶段的截面图和透视图。实施例的各种变化被讨论。在各种视图和说明性实施例中,相同的附图标记用于表明相同的元件。在图1A至图13C中,图“A”(例如,图1A、2A等)示出透视图,图“B”(例如,图1B、2B等)示出沿各自图“A”中示出的Y切线的截面图,并且图“C”(例如,图1C、2C等)示出沿各自图“A”中示出的X切线的截面图。
首先参见图1A至图1C,显示了具有一个或多个鳍的衬底102,仅有一个鳍104被示出。可以理解,为了说明的目的示出一个鳍,但其他实施例可以包括任意数量的鳍。根据设计要求,衬底102可以包括各种掺杂区(例如,p型衬底或n型衬底)。在一些实施例中,掺杂区可以掺杂有p型或n型掺杂剂。例如,掺杂区可以掺杂有诸如硼或BF2的p型掺杂剂、诸如磷或砷的n型掺杂剂和/或它们的结合。掺杂区可以配置用于n型FinFET,或者可选地配置用于p型FinFET。
在一些实施例中,衬底102可以由一些其他诸如金刚石或锗的合适的元素半导体;诸如砷化镓、碳化硅、砷化铟或磷化铟的合适的化合物半导体;或诸如碳化硅锗、III-V化合物半导体(例如,砷化镓、铟镓砷化物InmGa1-mAs、砷化铟、磷化铟、锑化铟、磷化镓砷或磷化镓铟)的合适的合金半导体制成。进一步地,衬底102可以包括外延层(epi层),可以应变以增强性能和/或可以包括绝缘体上硅(SOI)结构。
鳍104例如可以使用图案化工艺形成以形成沟槽108,使得鳍104形成在相邻的鳍之间。在一些实施例中,利用光刻技术图案化掩模层(未示出)。通常,光刻胶材料(未示出)沉积在掩模层上方。光刻胶材料通过图案化的刻线被能量(例如,光)照射(暴露),以便在暴露在能量中的光刻胶材料的这些部分中引起反应。光刻胶材料被显影以移除光刻胶材料的一部分,其中剩余的光刻胶材料在诸如蚀刻的后续处理步骤中保护下层材料。如下文更详细地描述,鳍104将会被用于形成MuGFET。例如,沟道侧壁表面的晶体定向的示例可以是(110),并且沟道顶部表面可以是(001)。沟道侧壁表面可以是诸如(551)的其他晶体定向。沟道侧壁和沟道顶部表面可以具有其他晶体定向。
诸如浅沟槽隔离(STI)106的隔离区沿鳍104的侧壁在沟槽108中形成。在形成STI106之前,一个或多个衬垫(统称为衬垫110)形成在衬底102和鳍104的侧壁上方。在一些实施例中,衬垫110具有厚度在约至约之间的单层结构。在一些实施例中,衬垫110具有包括第一衬垫子层和第二衬垫子层的双层结构。在一些实施例中,第一衬垫子层包括氧化硅并且具有在约至约之间的厚度,并且第二衬垫子层包括氮化硅并且具有在约至约之间的厚度。衬垫110可以通过一种或多种工艺沉积,例如物理汽相沉积(PVD)、化学汽相沉积(CVD)或原子层沉积(ALD),当然任何可接受的工艺都可以被利用。在一些实施例中,沟槽108从鳍104的顶部的深度为约至约可以使用其他材料、尺寸和/或工艺。
STI 106可以由合适的介电材料制成,例如,氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(FSG)、诸如碳掺杂氧化物的低k介电材料、诸如多孔碳掺杂二氧化硅的极低k介电材料、诸如聚酰亚胺的聚合物、这些的结合等。在一些实施例中,STI 106通过诸如CVD、回流CVD(FCVD)、或旋转涂布玻璃工艺形成,当然任何可接受的工艺都可以被利用。接着在鳍104的顶部表面上方延伸的STI 106的一部分以及衬垫110在鳍104的顶部表面上方的部分被移除,例如,使用蚀刻工艺、化学机械抛光(CMP)等。
在一些实施例中,如图1A至图1C所示,STI 106和衬垫110凹陷以暴露鳍104的侧壁。在一些实施例中,STI 106和衬垫110使用一种或多种选定的蚀刻工艺利用鳍104作为蚀刻掩模形成凹陷。例如,STI 106和衬垫110使用单蚀刻工艺凹陷。在可选的实施例中,STI106和衬垫110使用多重蚀刻工艺凹陷。例如,STI 106使用第一蚀刻工艺利用鳍104和衬垫110作为蚀刻掩模凹陷,并且随后衬垫110使用第二蚀刻工艺凹陷。在STI 106包括氧化硅的实施例中,蚀刻工艺例如可以是干蚀刻、化学蚀刻或湿法清洗工艺。例如,化学蚀刻可以采用诸如稀氢氟(dHF)酸的含氟化学药品。在鳍形成工艺之后,鳍高度Hfin可以为30nm或更高,例如50nm或更高。可以理解,鳍高度可以通过随后的工艺而改变。也可以使用其他材料、工艺和尺寸。
图1A至图1C进一步示出了根据一些实施例的形成在暴露的鳍104上方的伪栅极电介质112和伪栅电极114。伪栅极电介质112和伪栅电极114将会随后用于限定和形成源极/漏极区。在一些实施例中,伪栅极电介质112和伪栅电极114通过沉积和图案化形成在暴露的鳍104上方的伪栅极介电层(未示出)和在伪栅极介电层上方的伪栅电极层(未示出)形成。伪栅极介电层可以通过热氧化、CVD、溅射或本领域已知和使用的用于形成伪栅极介电层的任何其他方法形成。在一些实施例中,伪栅极介电层可以由与STI 106相同的材料形成。在其他实施例中,伪栅极电介质112可以由一种或多种诸如氧化硅、氮化硅、SiCN、SiON、Si3N4和SiNxHy的介电材料、诸如碳掺杂氧化物的低k介电材料、诸如多孔碳掺杂二氧化硅的极低k介电材料、诸如聚酰亚胺的聚合物等或它们的结合制成。在一些实施例中,伪栅极介电层包括具有高介电常数(k值)的介电材料,例如大于3.9。该材料可以包括金属氧化物,例如,HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等或它们的结合以及它们的多层结构。
随后,伪栅电极层形成在伪栅极介电层上方。在一些实施例中,伪栅电极层为导电材料,并且可以从包括非晶硅、多晶硅、非晶锗、多晶锗、非晶硅锗、多晶硅锗、金属氮化物、金属硅化物、金属氧化物和金属的组中选择。在一个实施例中,伪栅电极层可以通过PVD、CVD、溅射沉积或其他本领域所已知和使用的用于沉积导电材料的方法沉积。可以使用其他导电或不导电的材料。伪栅电极层的顶部表面通常具有不平坦的顶部表面,并且在其沉积之后可以被平坦化。
诸如伪栅极掩模117的硬掩模可以形成在伪栅电极层上方以协助图案化。伪栅极掩模117包括一个或多个掩模层,并且将会用于图案化伪栅极介电层和伪栅电极层以形成如图1A至图1C所示的伪栅极电介质112和伪栅电极114。伪栅极掩模117可以包括一个或多个图案化层。在一些实施例中,伪栅极掩模117可以由SiO2、SiCN、SiON、Si3N4、Al2O3、SiNxHy或其他合适的材料形成。
在一些实施例中,伪栅极掩模117包括第一硬掩模层和第二硬掩模层。第一硬掩模层可以是氧化物层(例如,氧化硅),并且第二硬掩模层可以是氮化物(例如氮化硅)。第一硬掩模层和第二硬掩模层可以通过诸如CVD或旋转涂布玻璃工艺被沉积,当然任何可接受的工艺都可以被利用。第一硬掩模层可以具有约至约的厚度并且第二硬掩模层可以具有约至约的厚度。伪栅电极114和伪栅极电介质112共同形成伪栅极堆叠116。
根据一些实施例,侧壁间隔件118沿伪栅极堆叠116的侧壁形成。侧壁间隔件118可以通过沉积和图案化在伪栅极堆叠116、鳍104和STI 106上方的间隔件层(未示出)形成。在一些实施例中,间隔件层由氮化硅形成,并且可以具有单层结构。在可选实施例中,间隔件层可以具有包括多个层的复合结构。例如,间隔件层可以包括氧化硅层和在氧化硅层上方的氮化硅层。也可以使用诸如SiO2、SiCN、SiON、Si3N4、SiNxHy、SiOCN、其他低k材料或它们的结合的其他材料。
间隔件层可以被图案化以形成侧壁间隔件118,例如,使用各向异性蚀刻工艺移除在器件水平部分上方和沿伪栅极堆叠116侧壁的间隔件层。由于间隔件层在器件的水平部分上方和沿鳍104侧壁的厚度不同,当鳍104如图1A至图1C所示地暴露在源极/漏极区中时,间隔件层沿伪栅极堆叠116的侧壁保留。
应当注意,为了说明性目的,附图示出三个栅电极。在一些实施例中,在中间的栅电极可以代表有源栅电极,而在两侧的栅电极为用于图案化目的的伪栅电极(例如,无源)。在其他实施例中,所有的栅电极可以是有源栅电极。
图1A至图1C进一步示出了根据一些实施例的沿伪栅极堆叠116的相对侧形成在鳍104的暴露部分上的第一源极/漏极区120和第二源极/漏极区122。在一些实施例中,鳍104可以凹陷并且第一源极/漏极区120和第二源极/漏极区122外延形成在凹陷的鳍的暴露部分上。在源极/漏极区中使用外延生长材料允许源极/漏极区在沟道区124中施加应力。用于第一源极/漏极区120和第二源极/漏极区122的材料可以不同以用于n型和p型FinFET,以便用于n型FinFET的一种类型的材料在沟道区中施加拉伸应力,并且用于p型FinFET的另一种材料施加压缩应力。例如,SiP或SiC可以用于形成n型FinFET,并且SiGe或Ge可以用于形成p型FinFET。可以使用其他材料。
在n型器件和p型器件利用不同材料的实施例中,当在一个(例如,p型鳍)上形成外延材料时,期望掩盖另一个(例如n型鳍),并且对另一者重复上述工艺。第一源极/漏极区120和第二源极/漏极区122可以通过注入工艺注入适当的掺杂物,或当材料生长时通过原位掺杂被掺杂。例如,对于沟道可以是Si或Si1-xGex的p沟道MuGFET,掺杂的外延薄膜可以是硼掺杂Si1-yGey,其中y等于或大于x以在沟道中引起纵向压缩应变以用于改善空穴迁移率。对于沟道可以是Si的n沟道MuGFET,例如掺杂的外延薄膜可以是磷掺杂硅(Si:P)或碳化硅(Si1-zCz:P)。在沟道是诸如InmGa1-mAs的化合物半导体的情况下,例如掺杂的外延薄膜可以是InnGa1-nAs,其中n小于或等于m。
现在参照图2A至图2C,衬垫介电薄膜230沉积在第一源极/漏极区120、第二源极/漏极区122、侧壁间隔件118和伪栅极堆叠116的顶部。如下文将详细描述,随后将被图案化的填充材料将会形成在衬垫介电薄膜230的上方。衬垫介电薄膜230在填充材料图案化的过程中充当蚀刻停止部分。在一些实施例中,衬垫介电薄膜230包括SiO2、SiCN、SiON、Si3N4以及SiNxHy,但是也可以使用其他合适的介电材料。衬垫可以进一步包括多个层,该层包括上述材料的结合。衬垫介电薄膜230可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积,当然可以利用任何可接受的工艺。可以使用其他材料和/或工艺。
在一些实施例中,衬垫介电薄膜230具有5nm或更小(诸如3nm或更小)的厚度tl。可以使用其他厚度。
图3A至图3C示出了根据一些实施例的形成在衬垫介电薄膜230上方的牺牲栅极间薄膜332的形成。在一些实施例中,牺牲栅极间薄膜332包括Si、Ge、SiGe、SiO2、SiCN、SiON、SiOxCy、SiOxHy、SiNxHy或其他合适的半导体或介电材料。在一些实施例中,牺牲栅极间薄膜332通过诸如CVD、FCVD或旋转涂布玻璃工艺的工艺形成,当然可以利用任何可接受的工艺。随后,衬垫介电薄膜230和牺牲栅极间薄膜332在鳍104上方延伸的部分被移除,例如使用蚀刻工艺、CMP等。
如上所示并且在下文中详细解释,牺牲栅极间薄膜332随后将会从伪栅极堆叠116之间移除,并且在移除工艺的过程中,下层衬垫介电薄膜230充当蚀刻停止部分并且保护下层结构。这样,期望为衬垫介电薄膜230和牺牲栅极间薄膜332选择具有高蚀刻选择性的材料,以使得对于所选择的蚀刻工艺牺牲栅极间薄膜332的蚀刻速率大于衬垫介电薄膜230的蚀刻速率。
现在参照图4A至图4C,根据一些实施例,牺牲栅极间薄膜332被凹陷并且栅极间掩模434形成在凹陷中。在随后的工艺中移除伪栅电极114和伪栅极电介质112的过程中,栅极间掩模434防止或降低牺牲栅极间薄膜332的损失。在伪栅极掩模117包括氮化硅并且牺牲栅极间薄膜332包括氧化硅的实施例中,牺牲栅极间薄膜332可以使用各项同性干法或湿法蚀刻工艺凹陷,例如使用湿氢氟酸的湿蚀刻。
在一些实施例中,栅极间掩模434由SiO2、SiCN、SiON、Si3N4、Al2O3、La2O3、SiNxHy等使用CVD方法形成,其可以为等离子增强CVD(PECVD)、分子层沉积(MLD)、它们的结合或其他合适的方法。可以执行诸如CMP工艺的平坦化工艺以暴露伪栅极掩模117(见图3A至图3C)。在一些实施例中,如图4A至图4C所示,平坦化工艺可以继续移除伪栅极掩模117,并且暴露伪栅电极114。
图5A至图5C示出了根据一些实施例的伪栅电极114和伪栅极电介质112的移除。通过栅极间掩模434保护牺牲栅极间薄膜332,伪栅极堆叠116被移除。移除工艺可以包括一种或多种蚀刻工艺。例如,在栅极间掩模434包括氮化硅并且伪栅电极114包括多晶硅并且伪栅极电介质112包括氧化硅的实施例中,移除工艺可以包括使用干法或湿法蚀刻的选择性蚀刻。在使用干法蚀刻的情况下,工艺气体可以包括CF4、CHF3、NF3、SF6、Br2、HBr、Cl2或它们的结合。可以选用诸如N2、O2或Ar的稀释气体。在使用湿法蚀刻的情况下,化学药品包括NH4OH:H2O2:H2O(APM)、NH2OH、KOH、HNO3:NH4F:H2O和/或类似物。伪栅极电介质112可以使用湿法蚀刻工艺移除,例如可以使用稀氢氟酸。可以使用其他工艺和材料。
图6A至图6C示出了根据一些实施例的在鳍104的沟道区124上方形成的栅极介电层642。在实施例中,栅极介电层642包括一个或多个高k介电层(例如,具有大于3.9的介电常数)。例如,一个或多个栅极介电层可以包括一个或多个层,该层为金属氧化物,Hf、Al、Zr的硅酸盐,它们的结合,以及它们的多层结构。其他合适的材料包括金属氧化物、金属合金氧化物形式的La、Mg、Ba、Ti、Pb、Zr以及它们的结合。示例性材料包括MgOx、BaTixOy、BaSrxTiyOz、PbTixOy、PbZrxTiyOz、SiCN、SiON、Si3N4、Al2O3、La2O3、Ta2O3、Y2O3、HfO2、ZrO2、HfSiON、YGexOy、YSixOy和LaAlO3以及类似物。栅极介电层642的形成方法包括分子束沉积(MBD)、ALD、PVD等。在实施例中,栅极介电层642可以具有约至的厚度。
在一些实施例中,界面层(未示出)可以在形成栅极介电层642之前形成在沟道区124的上方,并且栅极介电层642形成在界面层上方。界面层有助于从下层半导体材料缓冲随后形成的高k介电层。在一些实施例中,界面层是化学氧化硅,其可以由化学反应形成。例如,化学氧化物可以使用去离子水+臭氧(DIO3)、NH4OH+H2O2+H2O(APM)或其他方法形成。其他实施例可以利用不同的材料或工艺用于界面层。在实施例中,界面层640可以具有约至约的厚度。
图6A至图6C进一步示出了形成在栅极介电层642上方的栅电极644。栅电极644可以是从W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr的组中选择的金属。在一些实施例中,栅电极644包括从TiN、WN、TaN和Ru的组中选择的金属。可以使用诸如Ti-Al、Ru-Ta、Ru-Zr、Pt-Ti、Co-Ni和Ni-Ta的金属合金和/或可以使用诸如WNx、TiNx、MoNx、TaNx和TaSixNy的金属氮化物。在一些实施例中,栅电极644具有在约5nm至约100nm范围内的厚度。栅电极644可以使用诸如ALD、CVD、PVD、电镀或它们的结合的合适的工艺形成。可以执行诸如CMP的平坦化工艺以移除多余的材料。
现在参照图7A至图7C,示出了根据一些实施例的栅电极644的凹陷以及栅电极掩模746在栅电极644剩余的部分上方的形成。在栅极间掩模434包括氮化硅的一些实施例中,栅电极例如可以使用Cl2/O2/BCl3在24℃至150℃的温度范围内在低于1托的操作压力下使用干法蚀刻工艺凹陷。
在凹陷栅电极644之后,栅电极掩模746可以形成在凹口中以在后续工艺过程中保护栅电极644。在一些实施例中,栅电极掩模746包括SiO2、SiCN、SiON、Si3N4、Al2O3、La2O3、SiNxHy、它们的结合或类似物,但是也可以使用其他合适的介电薄膜。栅电极掩模746例如可以使用CVD、PVD、旋转涂布等形成。可以使用其他合适的工艺步骤。
可以执行诸如CMP的平坦化工艺以移除多余的材料。此外,平坦化工艺可以如图7A至图7C所示地继续移除栅极间掩模434。
图8A至图8C示出了根据一些实施例的牺牲栅极间薄膜332的移除。如下文更详细地讨论,牺牲栅极间薄膜332将会被另一材料(例如牺牲薄膜950)代替,其具有比栅电极掩模746、衬垫介电薄膜230以及侧壁间隔件118的其他结构的材料(例如氧化硅、氮化硅等)更高的蚀刻速率选择性,以允许更易受控的接触形成。
在牺牲栅极间薄膜332由氧化硅形成并且栅电极掩模746由氮化硅形成的实施例中,牺牲栅极间薄膜332可以使用各向同性干法或湿法蚀刻工艺移除。例如,干法蚀刻工艺使用C4F6或氟基气体或它们的结合作为工艺气体,并且可以使用诸如N2、O2或Ar的载体气体。在使用湿法蚀刻的情况下,蚀刻剂可以包括稀HF和/或类似物。如图8A至图8C所示,在移除牺牲栅极间薄膜332以后,衬垫介电薄膜230被暴露。
图9A至图9C示出了根据一些实施例的牺牲薄膜950在通过移除牺牲栅极间薄膜332(见图8A至图8C)形成的凹口中的形成。在一些实施例中,牺牲薄膜950包括多晶硅,当然也可以使用诸如SiO2、SiCN、SiON、Si3N4、SiNxHy、Si、Ge、SiGe、SiGeC、GeSn或III-V材料的其他材料、其他合适的半导体或介电薄膜或类似物。在一些实施例中,牺牲薄膜950的沉积温度保持在600℃以下,例如在500℃以下,或400℃以下,以便降低或最小化对先前形成的金属栅极/高k介电堆叠的阈值电压的热冲击。牺牲薄膜950还可以具有良好的间隙填充能力。例如,在实施例中,开口的宽度wc小于20nm,例如小于10nm,或例如小于7nm。
例如,在一些实施例中,牺牲薄膜950为通过CVD工艺形成的Si、Ge、SiGe、SiGeC。例如,Si沉积工艺可以使用诸如硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)、四硅烷(Si4H10)或其他高阶硅烷的前体。CVD工艺温度通常取决于使用的前体。对于使用硅烷或乙硅烷的生长,生长温度可以是约300℃或更高。对于使用高阶硅烷的生长,可以使用低于300℃的温度。对于Ge生长的其他实施例,前体可以是甲锗烷(GeH4)、乙锗烷(Ge2H6)、三锗烷(Ge3H8)、四锗烷(Ge4H10)或其他高阶锗烷。生长温度可以是从约250℃至约650℃。操作压力范围可以从10托至760托。
如下文更详细地描述,牺牲薄膜950的部分可以被选择性移除,并且由此,期望选择与衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746相比具有高蚀刻速率选择性的材料用于牺牲薄膜950。例如,在牺牲薄膜950由多晶硅形成并且衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅或氧化硅形成的实施例中,可以使用蚀刻工艺以便牺牲薄膜950以比衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746高得多的速率被蚀刻。
图10A至图10C示出了根据一些实施例的图案化牺牲薄膜950后的结构。如下文将解释,牺牲薄膜950的剩余材料将会在随后的步骤中被导电材料代替,以形成对源极漏极区的接触件。在一些实施例中,利用光刻技术图案化牺牲薄膜950。通常,光刻胶材料(未示出)沉积在牺牲薄膜950上方。光刻胶材料被能量照射(暴露)并显影以便光刻胶的在牺牲薄膜950接触源极/漏极区的区域上方的部分被期望的保留。牺牲薄膜950被保护的部分代表对源极/漏极区的接触件的位置。在一些实施例中,接触件的长度lc小于40nm,例如小于20nm。如图10A至图10C所示,衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746的部分可以在蚀刻工艺过程中被移除。
可以完成牺牲薄膜950的移除以使牺牲薄膜的蚀刻速率大于被暴露的材料的蚀刻速率,例如衬垫、间隔件、栅极掩模以及隔离介电薄膜。蚀刻选择性Sl、Ss、Sgm和Sid可以是牺牲薄膜分别与衬垫介电薄膜230、侧壁间隔件118、栅电极掩模746以及STI 106的蚀刻速率的比率。每个Sl、Ss、Sgm和Sid可以高于3,并且在一些实施例中,可以高于10,例如高于20。在牺牲薄膜950的蚀刻过程中,由于在源极/漏极顶部下方的牺牲薄膜被蚀刻,沿着源极/漏极的顶部的衬垫介电薄膜230可以被移除。在一些实施例中Sl至少近似于Hfin/tl。在一些实施例中Hfin为60nm,并且tl为3nm,并且S1可以至少为20。
例如,在一些实施例中,牺牲薄膜950由多晶硅形成,并且衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅形成。在这样的实施例中,使用干法蚀刻的接触隔离蚀刻工艺可用于避免一些湿法蚀刻行为表现的横向过渡蚀刻。工艺气体可以包括HBr/N2/O2或Cl2/SF6,温度低于200℃(例如,低于100℃),RF功率小于3kW(例如,小于600W),并且压力小于10托(例如,小于3托)。
作为另一个示例,在一些实施例中,牺牲薄膜950由通过旋转涂布形成的SiOC形成,并且衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅形成。在这些实施例中,可以使用各向异性蚀刻工艺移除在接触隔离区中的牺牲薄膜950。工艺气体可以包括N2和H2、或SO2和O2,温度低于200℃(例如,20-100℃),RF功率大于100W(例如,大于300W),并且压力小于3托(例如,小于200毫托)。
作为又一个示例,在一些实施例中,牺牲薄膜950由通过回流CVD形成的氧化硅形成,并且衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅形成。牺牲薄膜950的移除可以使用等离子体蚀刻工艺执行,工艺气体可以包括C4F6或氟基气体,温度低于200℃(例如,低于150℃),RF功率大于50W(例如,大于100W),并且压力小于3托(例如,小于200毫托)。
作为又一个示例,在一些实施例中,牺牲薄膜950由锗形成,并且衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅形成。在这些实施例中,可以使用等离子体蚀刻工艺通过各向异性蚀刻移除牺牲薄膜950。工艺气体可以包括CF4化学成分(例如,CF2Cl2、CF3Br或类似物),或HBr、Cl2或其他卤素气体,温度低于200℃(例如,低于60℃),RF功率大于2000kW(例如,约50W至约300W),并且压力小于10托(例如,小于500毫托)。
现在参照图11A至图11C,根据实施例,层间电介质(ILD)1150被形成。ILD 1150可以包括单层或多层。例如,在一些实施例中,ILD衬垫1152沉积在第一源极/漏极区120、第二源极/漏极区122、侧壁间隔件118以及伪栅极堆叠116的顶部,并且ILD填充材料1154沉积在ILD衬垫1152的上方(ILD衬垫1152和ILD填充材料1154统称为ILD 1150)。在一些实施例中,ILD衬垫1152包括SiO2、SiCN、SiON、Si3N4和SiNxHy,但是也可以使用其他合适的介电材料。ILD衬垫1152可以进一步包括多个层,该层包括上述材料的结合。ILD衬垫1152可以通过诸如PVD、CVD、或ALD的一种或多种工艺沉积,当然可以利用任何可接受的工艺。可以使用其他材料和/或工艺。
在一些实施例中,ILD填充材料1154包括SiO2、SiCN、SiOC、SiON、Si3N4和SiNxHy,但是也可以使用其他合适的介电材料。可以在沉积后固化或处理隔离电介质。例如,固化可以包含使用紫外线照射,并且处理可以包含在N2、O2或H2O环境中以200℃以上的温度范围退火。在固化或处理后,隔离电介质可以具有小于6(例如小于5,或例如小于4)的相对介电常数。例如,隔离电介质可以是通过CVD、PECVD或ALD沉积工艺、PCVD或旋转涂布玻璃工艺形成的SiO2。可以执行诸如CMP工艺的平坦化工艺以移除多余的材料并暴露牺牲薄膜950。
图12A至图12C示出了根据一些实施例的牺牲薄膜950(见图11A至图11C)的移除。如下文将详细描述,牺牲薄膜950被将形成与源极/漏极区接触的导电材料替换。在一些实施例中,牺牲薄膜950可以使用选择性蚀刻工艺被移除。这样,期望为牺牲薄膜950、ILD1150、衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746选择材料,以便高蚀刻速率选择性存在于牺牲薄膜950的材料和ILD 1150、衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746的材料之间。
例如,在一些实施例中,牺牲薄膜950由多晶硅形成,并且ILD衬垫1152、ILD填充材料1154、衬垫介电薄膜230、侧壁间隔件118以及栅电极掩模746由氮化硅和/或氧化硅形成。在这些实施例中,使用各向同性蚀刻工艺的多晶硅的蚀刻速率与氮化硅和氧化硅的蚀刻速率的比率为约30至约50。在使用等离子体蚀刻的情况下,工艺气体可以包括Cl2/NF3/He或者SF6或NF3或CF4或其他合适的基于卤素的蚀刻气体,温度低于200℃(例如,低于100℃),RF功率小于3kW(例如,小于600W),并且压力小于10托(例如,小于3托)。在一些实施例中,湿法蚀刻工艺被用于移除牺牲薄膜950。湿法蚀刻工艺的蚀刻材料可以是NH4OH或TMAH或其他可以移除Si薄膜的材料。作为另一个示例,可以使用氟基气体/NH3以低于200℃(例如,低于100℃)的温度执行干法化学蚀刻工艺。
作为另一个示例,在一些实施例中,牺牲薄膜950由通过旋转涂布涂覆形成的SiOC形成,ILD填充材料1154为通过回流CVD形成的SiO2,ILD衬垫1152可以是ALD氮化硅,并且栅电极掩模746可以是氮化硅。在这些实施例中,使用等离子体蚀刻工艺的SiOC的蚀刻速率与氮化硅和氧化硅蚀刻速率的比率可以大于50,其中,工艺气体可以包括N2和H2、或SO2和O2,温度低于200℃(例如,20-100℃),RF功率大于100W(例如,大于300W),并且压力小于3托(例如,小于200毫托)。
作为又一示例,在一些实施例中,牺牲薄膜950由通过回流CVD形成的氧化硅形成,ILD填充材料1154是通过回流CVD形成的SiO2,ILD衬垫1152可以是氮化硅,并且栅电极掩模746可以是氮化硅。可以使用等离子体蚀刻工艺执行牺牲薄膜950的移除,工艺气体可以包括C4F6或氟基气体,温度低于200℃(例如,低于150℃),RF功率大于50W(例如,大于100W),并且压力小于3托(例如,小于200毫托)。
作为又一示例,在一些实施例中,牺牲薄膜950由锗形成,ILD填充材料1154是SiO2,ILD衬垫1152可以是ALD氮化硅,并且栅电极掩模746可以是氮化硅。在这些实施例中,使用等离子体蚀刻工艺的锗的蚀刻速率与氮化硅和氧化硅蚀刻速率的比率可以大于15,其中,工艺气体可以包括CF4化学成分(例如,CF2Cl2、CF3Br或类似物),或HBr、Cl2或其他卤素气体,温度低于200℃(例如,低于60℃),RF功率大于2000kW(例如,约50W至约300W),并且压力小于10托(例如,小于500毫托)。
移除牺牲薄膜950之后,衬垫介电薄膜230暴露的部分可以被移除以暴露下层的第一源极/漏极区120和第二源极/漏极区122。在衬垫介电薄膜230由氮化硅形成,ILD衬垫1152由氮化硅形成,并且ILD填充材料1154由氧化硅形成的实施例中,衬垫介电薄膜230可以通过氟基蚀刻气体使用干法蚀刻工艺移除。由于材料的不同,衬垫介电薄膜230可以被移除,而无需移除或限制ILD衬垫1152和ILD填充材料1154的移除。
如上文所示,牺牲薄膜950的使用以及与其他材料相比具有高蚀刻速率选择性的能够被选择性蚀刻的材料的选择,接触开口可以使用自对准工艺形成。这样,随着器件按比例缩小以进一步满足市场需求,诸如那些此处公开的实施例允许未对准风险较低的更小的接触面积形成,上述未对准可能引起短路和器件故障问题。另外,侧壁间隔件之间的全部空间可以被使用从而允许较大的接触面积,这可以降低接触电阻并提升器件性能。
现在参照图13A至图13D,示出了根据一些实施例的接触件1358的形成,其中,图13D示出了图13B的一部分的放大图。接触件1358可以包括单层或多层结构。例如,在一些实施例中,接触件1358包括诸如扩散阻挡层、粘合层或类似物的衬垫以及形成在接触衬垫上方在开口中的接触填充物。接触衬垫可以包括由ALD、CVD或类似工艺形成的Ti、TiN、Ta、TaN或类似物。接触填充物可以通过沉积导电材料形成,例如一层或多层Ni、Ta、TaN、W、Co、Ti、TiN、Al、Cu、Au、它们的合金、它们的结合或类似物,但是也可以使用其他合适的金属。可以执行诸如CMP的平坦化工艺,以从ILD填充材料1154的表面移除多余的材料。
如图13D所示,接触件1358表现出锥形接触侧壁轮廓,并且顶部接触平面和接触侧壁之间的角度大于90°。如图13D所示,接触件1358沿接触件1358的顶部的宽度Cw1小于接触件1358沿接触件1358的底部的宽度Cw2。
图14A至图15B示出了根据一些实施例的不同蚀刻轮廓,它们可以在移除牺牲薄膜950的过程中在接触隔离区中获得。在图14A至图15B中示出的工艺设定为先前执行的参照图1A至图10C讨论的工艺,并且参照图11A至图13D讨论的工艺在以下参照图14A至图15B讨论的工艺之后执行。相应地,在执行上文参照图1A至图10C讨论的工艺之后,可以执行额外的蚀刻工艺以横向加宽在接触隔离区上方的开口的上部部分,同时,牺牲薄膜950的在源极/漏极区上方的部分被如以上参照附图10A至图10C讨论的保护。如图14A至图14B所示,第二蚀刻可以横向移除侧壁间隔件118的上部部分以及剩余的栅电极掩模746的部分,从而产生漏斗形开口轮廓。漏斗形开口轮廓允许侧壁间隔件118和栅电极掩模746的一部分被低介电常数材料代替,从而降低栅电极644与接触件1358之间的边缘电容并改善器件性能。
在侧壁间隔件118和栅电极掩模746由氮化硅形成的实施例中,执行横向干法蚀刻等离子体工艺,使用CF4化学成分(例如,CF2Cl2、CF3Br或类似物)作为工艺气体,温度低于250℃(例如,低于150℃),RF功率大于3kW(例如,小于2kW),并且压力小于5托(例如,小于2.5托)。在一些实施例中,高度(HA)和宽度(WA)分别大于4nm和大于2nm。
此后,可以执行诸如上文参照图11A至图11C讨论的工艺,以使用ILD材料(例如ILD衬垫1152和ILD填充物材料1154)填充漏斗形开口,由此产生图15A至图15B中示出的结构。可以执行诸如上文参照图11A至图13D讨论的工艺以完成接触件的形成。
图16A至图17B示出了根据一些实施例的不同蚀刻轮廓,它们可以在移除牺牲薄膜950的过程中在接触区中获得。如上文所讨论的,图14A至图15B示出了可以为开口提供的不同的轮廓,其中ILD 1150形成在开口中。图16A至图17B示出了可以用于形成开口的相似的蚀刻轮廓,其中接触件1358将形成在该开口中。
设定为参照上述图1A至图1C到参照图12A至图12C所讨论的移除牺牲薄膜950的工艺所讨论的在图16A至图17B中示出的工艺,在图16A至图17B所示的工艺之前执行,其中,可以执行额外的蚀刻工艺以横向加宽在源极/漏极区的接触区上方的开口的上部部分。如图16A至图16B所示,第二蚀刻可以横向移除侧壁间隔件118的上部部分以及栅电极掩模746的一部分,从而如图16A至图16B所示地产生漏斗形开口轮廓。如上文参照图12A至图12C所讨论的,ILD衬垫1152可以从源极/漏极区上方移除。
在ILD衬垫1152和栅电极掩模746由氮化硅形成的一些实施例中,可以使用横向干法蚀刻等离子体工艺,使用CF4化学成分(例如,CF2Cl2、CF3Br或类似物)作为工艺气体,温度低于250℃(例如,低于150℃),RF功率大于3kW(例如,小于2kW),并且压力小于5托(例如,小于2.5托)。在一些实施例中,高度(HB)和宽度(WB)分别小于7nm和小于3nm。在一些实施例中,HB和WB可以分别大于HA和WA。然后可以如上文参照图13A至图13D讨论的使用导电材料填充漏斗形开口,由此产生图17A至图17B中示出的接触件。
可以执行其他工艺。例如,在一些实施例中,金属硅化物可以形成在第一源极/漏极区930和第二源极/漏极区932的上方。在一些实施例中,金属硅化物形成工艺在如上文参照图8A至图8C讨论的栅极间薄膜移除工艺之后执行,或在如上文参照图12A至图12C讨论的接触件孔形成之后执行。金属硅化物形成工艺可以在掺杂的源极/漏极区的顶部上形成金属硅化物,以降低掺杂的源极/漏极区与在其后形成的接触金属之间的Rc。金属硅化物形成工艺包括在源极/漏极区的顶部上沉积金属薄膜,热处理以在源极/漏极区之间的界面处形成金属硅化物,以及蚀刻工艺以移除多余的未反应金属。金属硅化物包括TiSix、NiSix、CoSix、NiCoSix以及TaSix,但是也可以使用其他合适的硅化物材料。在一些实施例中,硅化物形成可以执行ILD移除。
需要注意的是,其他实施例可以利用不同的其他步骤或步骤的顺序。例如,图18A至图28D示出了根据一些实施例的制造FinFET的中间阶段的不同的截面图和透视图。在图18A至图28C中,图“A”(例如,图18A、19A等)示出透视图,图“B”(例如,图18B、19B等)示出沿各自图“A”中示出的Y切线的截面图,并且图“C”(例如,图18C、19C等)示出沿各自图“A”中示出的X切线的截面图。
如上文参照图1A至图15B所讨论的,牺牲栅极间薄膜332如图3A至图3C所示地被暂时沉积,并且然后如图8A至图8C所示地被移除并如图9A至图9C所示地被牺牲薄膜950代替。在图18A至图28D所示的实施例中,牺牲栅极间薄膜332被省略。相反地,如下文更详细地描述,牺牲薄膜950在工艺中更早形成。以下段落中参照图18A至图28D对上述工艺更详细的讨论,其中相同的附图标记指代相同的元件。
首先参照图18A至图19C,示出了与上文参照图1A至图2C讨论的相似的工艺和材料,其中相同的附图标记指代相同的元件,并且不再重复。
现在参照图20A至20C,牺牲薄膜950例如使用与上文参照图9A至图9C讨论的相似的材料和工艺形成。
图21A至21C示出了根据一些实施例的牺牲薄膜950的凹陷。如下文更详细地讨论,牺牲薄膜950凹陷并且在凹陷的牺牲薄膜950上方形成掩模以在随后的工艺中保护牺牲薄膜950。在一些实施例中,牺牲薄膜950被凹陷至约以便为后续形成的掩模层提供足够的厚度。
在牺牲薄膜950由多晶硅形成,并且伪栅极掩模116、衬垫介电薄膜230以及侧壁间隔件118由氮化硅/氧化硅形成的实施例中,牺牲薄膜950可以使用定时蚀刻凹陷,例如使用等离子体蚀刻,工艺气体可以是NF3、HBr/N2/O2或Cl2/NF3/He,温度低于200℃(例如,低于100℃),RF功率小于3kW(例如,小于600W),并且压力小于10托(例如,小于3托)。
作为另一个示例,在一些实施例中,牺牲薄膜950由通过旋转涂布涂覆形成的SiOC形成,并且伪栅极掩模116、衬垫介电薄膜230以及侧壁间隔件118由氮化硅/氧化硅形成,牺牲薄膜950可以使用定时蚀刻形成凹陷,例如使用等离子体蚀刻,工艺气体可以包括N2和H2、或SO2和O2,温度低于200℃(例如,20-100℃),RF功率大于100W(例如,大于300W),并且压力小于3托(例如,小于200毫托)。
作为又一个示例,在一些实施例中,牺牲薄膜950由通过回流CVD形成的氧化硅形成,并且伪栅极掩模116、衬垫介电薄膜230以及侧壁间隔件118由氮化硅形成,牺牲薄膜950可以使用定时蚀刻凹陷,例如使用等离子体蚀刻工艺,工艺气体可以包括C4F6或氟基气体,温度低于200℃(例如,低于150℃),RF功率大于50W(例如,大于100W),并且压力小于3托(例如,小于200毫托)。
作为又一个示例,在一些实施例中,牺牲薄膜950由锗形成,并且伪栅极掩模116、衬垫介电薄膜230以及侧壁间隔件118由氮化硅/氧化硅形成,牺牲薄膜950可以使用定时蚀刻凹陷,例如使用等离子体蚀刻,工艺气体可以包括CF4化学成分(例如,CF2Cl2、CF3Br或类似物),或HBr、Cl2或其他卤素气体,温度低于200℃(例如,低于60℃),RF功率大于2000kW(例如,约50W至约300W),并且压力小于10托(例如,小于500毫托)。
可以执行诸如CMP工艺的平坦化工艺以暴露伪栅极掩模117(见图19A至图19C)。在一些实施例中,平坦化工艺可以继续移除伪栅极掩模117并如图21A至图21C所示地暴露伪栅电极114。
此后,与上文参照图5A至图7C讨论的相似的工艺可以如图22A至图24C所示地分别执行。相似的工艺和材料可以如上文描述地使用,并且不再重复。
现在参照图25A至图25C,根据一些实施例,牺牲薄膜950被图案化。牺牲薄膜950可以如上文参照图10A至图10C讨论地被图案化,并且不再重复。需要注意的是,在这些实施例中,上文参照图3和图8(形成并然后去除牺牲栅极间薄膜332以形成牺牲薄膜950)所讨论的工艺可以被省略。
此后,可以执行图26A至图28D所示出的工艺。该工艺可以分别与上文参照图11A至图13D的讨论相似,并且不再重复。
上文参照图14A至图15B讨论的在接触隔离区中形成漏斗形开口的工艺和/或参照图16A至图17B讨论的在接触区中形成漏斗形开口的工艺可以结合至上文参照图18A至图28C所讨论的工艺中。例如,在执行上文参照图18A至图25C讨论的工艺之后,可以执行上文参照图14A至图15B讨论的工艺。相应地,在执行上文参照图18A至图25C讨论的工艺之后,可以执行额外的蚀刻工艺以横向加宽在接触隔离区上方的开口的上部部分,同时牺牲薄膜950的在源极/漏极区上方的部分被以上参照附图25A至图25C讨论地保护。如图14A至图14B所示,第二蚀刻可以横向移除侧壁间隔件118的上部部分以及剩余的栅电极掩模746的部分,从而产生漏斗形开口轮廓。漏斗形开口轮廓允许侧壁间隔件118和栅电极掩模746的一部分被低介电常数材料代替,从而降低栅电极644与接触件1358之间的边缘电容并改善器件性能。
在侧壁间隔件118和栅电极掩模746由氮化硅形成的一些实施例中,可以执行横向干法蚀刻等离子体工艺,使用CF4化学成分(例如,CF2Cl2、CF3Br或类似物)作为工艺气体,温度低于250℃(例如,低于150℃),RF功率大于3kW(例如,小于2kW),并且压力小于5托(例如,小于2.5托)。在一些实施例中,高度(HA)和宽度(WA)分别大于4nm和大于2nm。
此后,可以执行诸如上文参照图26A至图26C讨论的工艺,以使用ILD材料(例如ILD衬垫1152和ILD填充物材料1154)填充漏斗形开口,由此产生图15A至图15B中示出的结构。可以执行诸如上文参照图26A至图28D讨论的工艺以完成接触件的形成。
上文参照图16A至图17B讨论的工艺也可以结合至上文参照图18A至图28C所讨论的工艺中以形成漏斗形接触件。例如,在执行上文参照图18A至图27C讨论的工艺之后,但在移除衬垫介电薄膜230之前,可以执行额外的蚀刻工艺以横向加宽在源极/漏极区的接触区上方的开口的上部部分。如图16A至图16B所示,第二蚀刻可以横向移除侧壁间隔件118的上部部分以及栅电极掩模746的部分,从而如图16A至图16B所示地产生漏斗形开口轮廓。如参照图27A至图27C所讨论的,ILD衬垫1152可以从源极/漏极区上方移除。
在ILD衬垫1152和栅电极掩模746由氮化硅形成的一些实施例中,可以使用横向干法蚀刻等离子体工艺,使用CF4化学成分(例如,CF2Cl2、CF3Br或类似物)作为工艺气体,温度低于250℃(例如,低于150℃),RF功率大于3kW(例如,小于2kW),并且压力小于5托(例如,小于2.5托)。在一些实施例中,高度(HB)和宽度(WB)分别小于7nm和小于3nm。在一些实施例中,HB和WB可以分别大于HA和WA。然后可以如上文参照图28A至图28D讨论地使用导电材料填充漏斗形开口,由此产生图17A至图17B中示出的接触件。
可以执行其他工艺。例如,在一些实施例中,金属硅化物可以形成在第一源极/漏极区930和第二源极/漏极区932的上方。在一些实施例中,金属硅化物形成工艺在如上文参照图8A至图8C讨论的栅极间薄膜的移除工艺之后执行,或在如上文参照图12A至图12C讨论的接触件孔形成之后执行。金属硅化物形成工艺可以在掺杂的源极/漏极区的顶部上形成金属硅化物,以降低掺杂的源极/漏极区与在其后形成的接触金属之间的Rc。金属硅化物形成工艺包括在源极/漏极区的顶部上沉积金属薄膜,热处理以在源极/漏极区之间的界面处形成金属硅化物,以及蚀刻工艺以移除多余的未反应金属。金属硅化物包括TiSix、NiSix、CoSix、NiCoSix以及TaSix,但是也可以使用其他合适的硅化物材料。在一些实施例中,硅化物形成可以执行ILD移除。
在一个实施例中,提供了一种形成半导体器件的方法。该方法包括:在鳍的源极/漏极区和与鳍相邻的隔离区的上方形成牺牲薄膜;移除牺牲薄膜的在隔离区上方的第一部分以形成第一凹口,保留牺牲薄膜的在源极/漏极区上方的第二部分;以及在第一凹口中形成介电层。该方法还包括移除牺牲薄膜的第二部分以形成第二凹口以及在第二凹口中形成导电层。
根据发明的实施例,牺牲薄膜形成在第一栅电极和第二栅电极之间,第一栅极掩模位于第一栅电极上方,并且第二栅极掩模位于第二栅电极上方。
根据发明的实施例,介电层在第一栅极掩模和第二栅极掩模的上方延伸。
根据发明的实施例,第一侧壁间隔件沿第一栅电极和第一栅极掩模的侧壁延伸,并且第二侧壁间隔件沿第二栅电极和第二栅极掩模的侧壁延伸。
根据发明的实施例,进一步包括:在移除牺牲薄膜的第一部分之后,移除第一栅极掩模和第二栅极掩模的上部部分,其中,在第一凹口中形成介电层之后,介电层接触第一栅极掩模。
根据发明的实施例,移除第一栅极掩模的上部部分使第一栅极掩模凹陷大于4nm的距离。
根据发明的实施例,进一步包括:在移除牺牲薄膜的第二部分之后,移除第一栅极掩模和第二栅极掩模的上部部分,其中,在形成导电层之后,导电层接触第一栅极掩模。
根据发明的实施例,移除第一栅极掩模的上部部分使第一栅极掩模凹陷大于7nm的距离。
在另一个实施例中,提供了一种形成半导体器件的方法。该方法包括:在半导体结构上方形成第一栅电极和第二栅电极;在第一栅电极和第二栅电极之间形成第一牺牲薄膜;以及图案化第一牺牲薄膜以使第一牺牲薄膜的剩余部分保留在半导体结构的上方并且使得第一凹口在第一牺牲薄膜的剩余部分的相对侧上形成在第一栅电极和述栅第二电极之间。该方法还包括在第一凹口中形成层间电介质(ILD);移除第一牺牲薄膜的剩余部分以形成第二凹口;以及在第二凹口中形成导电部件。
根据发明的实施例,第一牺牲薄膜为硅。
根据发明的实施例,进一步包括:在形成第一栅电极和第二栅电极之前,形成第一伪栅电极和第二伪栅电极;在形成第一牺牲薄膜之前,在第一伪栅电极和第二伪栅电极之间形成第二牺牲薄膜;在形成第一牺牲薄膜之前,以第一栅电极和第二栅电极代替第一伪栅电极和第二伪栅电极;以及在代替第一伪栅电极和第二伪栅电极之后,移除第二牺牲薄膜。
根据发明的实施例,半导体结构包括半导体鳍、多个半导体鳍、半导体纳米线或多个半导体纳米线。
根据发明的实施例,导电部件具有锥形轮廓以使顶部表面和侧壁表面之间的角度大于90°。
根据发明的实施例,进一步包括:在第一栅电极和第二栅电极上方形成掩模层,其中,使用蚀刻工艺执行第一牺牲薄膜的剩余部分的移除,蚀刻工艺具有大于15的第一牺牲薄膜的材料的蚀刻速率与掩模层的材料的蚀刻速率的比率。
根据发明的实施例,进一步包括:在第一栅电极和第二栅电极上方形成掩模层,其中,使用蚀刻工艺执行第一牺牲薄膜的剩余部分的移除,蚀刻工艺具有大于30的第一牺牲薄膜的材料的蚀刻速率与掩模层的材料的蚀刻速率的比率。
根据发明的实施例,第二凹口的宽度小于20nm。
根据发明的实施例,导电部件具有在第一栅电极和第二栅电极之间沿轴线延伸的宽度,宽度沿顶部表面宽于沿底部表面。
在另一个实施例中,提供了一种半导体器件。该半导体器件包括:在半导体结构上方的栅电极,半导体结构具有第一源极/漏极区、第二源极/漏极区以及介于第一源极/漏极区和第二源极/漏极区之间的沟道区,栅电极位于沟道区上方;在栅电极上方的栅极掩模;沿栅电极和栅极掩模的侧壁的侧壁间隔件,其中,侧壁间隔件的上部表面从栅极掩模的上部表面凹陷。该半导体器件还包括与侧壁间隔件相邻的接触件,接触件电连接至第一源极/漏极区,其中接触件接触栅极掩模的上部部分的侧壁。
根据发明的实施例,接触件具有沿平行于栅电极的轴线的锥形轮廓,以使在接触件远离第一源极/漏极区延伸时接触件的最外侧宽度减小。
根据发明的实施例,进一步包括与接触件相邻的ILD层,ILD层至少在栅极掩模的一部分上方延伸。
上面论述了多个实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域普通技术人员还应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,所述方法包括:
在鳍的源极/漏极区和与所述鳍相邻的隔离区的上方形成牺牲薄膜;
移除所述牺牲薄膜的在所述隔离区上方的第一部分以形成第一凹口,保留所述牺牲薄膜的在所述源极/漏极区上方的第二部分;
在所述第一凹口中形成介电层;
移除所述牺牲薄膜的所述第二部分以形成第二凹口;以及
在所述第二凹口中形成导电层。
2.根据权利要求1所述的方法,其中,所述牺牲薄膜形成在第一栅电极和第二栅电极之间,第一栅极掩模位于所述第一栅电极上方,并且第二栅极掩模位于所述第二栅电极上方。
3.根据权利要求2所述的方法,其中,所述介电层在所述第一栅极掩模和所述第二栅极掩模的上方延伸。
4.根据权利要求2所述的方法,其中,第一侧壁间隔件沿所述第一栅电极和所述第一栅极掩模的侧壁延伸,并且第二侧壁间隔件沿所述第二栅电极和所述第二栅极掩模的侧壁延伸。
5.根据权利要求4所述的方法,进一步包括:在移除所述牺牲薄膜的所述第一部分之后,移除所述第一栅极掩模和所述第二栅极掩模的上部部分,其中,在所述第一凹口中形成所述介电层之后,所述介电层接触所述第一栅极掩模。
6.根据权利要求5所述的方法,其中,移除所述第一栅极掩模的所述上部部分使所述第一栅极掩模凹陷大于4nm的距离。
7.根据权利要求4所述的方法,进一步包括:在移除所述牺牲薄膜的所述第二部分之后,移除所述第一栅极掩模和所述第二栅极掩模的上部部分,其中,在形成所述导电层之后,所述导电层接触所述第一栅极掩模。
8.根据权利要求7所述的方法,其中,移除所述第一栅极掩模的所述上部部分使所述第一栅极掩模凹陷大于7nm的距离。
9.一种形成半导体器件的方法,所述方法包括:
在半导体结构上方形成第一栅电极和第二栅电极;
在所述第一栅电极和所述第二栅电极之间形成第一牺牲薄膜;
图案化所述第一牺牲薄膜以使所述第一牺牲薄膜的剩余部分保留在所述半导体结构的上方并且使得第一凹口在所述第一牺牲薄膜的所述剩余部分的相对侧上形成在所述第一栅电极和所述栅第二电极之间;
在所述第一凹口中形成层间电介质(ILD);
移除所述第一牺牲薄膜的所述剩余部分以形成第二凹口;以及
在所述第二凹口中形成导电部件。
10.一种半导体器件,包括:
在半导体结构上方的栅电极,所述半导体结构具有第一源极/漏极区、第二源极/漏极区以及介于所述第一源极/漏极区和所述第二源极/漏极区之间的沟道区,所述栅电极位于所述沟道区上方;
在所述栅电极上方的栅极掩模;
沿所述栅电极和所述栅极掩模的侧壁的侧壁间隔件,其中,所述侧壁间隔件的上部表面从所述栅极掩模的上部表面凹陷;以及
与所述侧壁间隔件相邻的接触件,所述接触件电连接至所述第一源极/漏极区,其中所述接触件接触所述栅极掩模的上部部分的侧壁。
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