CN107492568A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN107492568A
CN107492568A CN201611040115.9A CN201611040115A CN107492568A CN 107492568 A CN107492568 A CN 107492568A CN 201611040115 A CN201611040115 A CN 201611040115A CN 107492568 A CN107492568 A CN 107492568A
Authority
CN
China
Prior art keywords
nano
layer
thread structure
nano wire
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611040115.9A
Other languages
English (en)
Inventor
冯家馨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107492568A publication Critical patent/CN107492568A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种半导体器件，包括设置在半导体衬底上并且在半导体衬底上的第一方向上延伸的纳米线结构。每个纳米线结构包括沿着第一方向延伸并且布置在第二方向上的多个纳米线，第二方向大致垂直于第一方向。每个纳米线与直接相邻的纳米线隔开。栅极结构在纳米线结构的第一区域上方的第三方向上延伸，第三方向大致垂直于第一方向和第二方向两者。栅极结构包括栅电极。在纳米线结构的第二区域上方设置源极/漏极区，第二区域位于栅极结构的相对侧上。栅电极包裹环绕每个纳米线。当在沿着第三方向截取的截面图中观察时，纳米线结构中的每个纳米线的形状不同于其他纳米线的形状，并且每个纳米线具有与纳米线结构中的其他纳米线大致相同的截面面积。本发明实施例涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体集成电路，且更具体地涉及具有全环栅极结构的半导体器件及其制造工艺。
背景技术
随着半导体产业已步入到纳米技术工艺节点以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战已经引起了诸如包括鳍FET(FinFET)和全环栅极(GAA)FET的多栅极场效应晶体管(FET)的三维设计的发展。在FinFET中，栅电极与沟道区的三个侧面相邻，并且栅极介电层插入在栅电极与沟道区之间。由于栅极结构在三个表面上围绕(包裹)鳍，晶体管本质上具有控制电流通过鳍或沟道区的三个栅极。不幸的是，第四侧，沟道的底部远离栅电极并且因此不在接近栅极控制之下。相反，在GAA FET，栅电极围绕沟道区的所有侧面，这允许在沟道区中更充分地耗尽并且由于急剧的亚阈值电流摆动(SS)和更小的漏致势垒降低(DIBL)导致了更少的短沟道效应。
随着晶体管的尺寸不断按比例缩小到亚20nm-25nm技术节点，需要进一步提高GAAFET。
发明内容
根据本发明的一些实施例，提供了一种半导体器件，包括：至少一个纳米线结构，设置在半导体衬底上并且在所述半导体衬底上以第一方向延伸，其中，每个所述纳米线结构包括沿着所述第一方向延伸并且在第二方向上布置的多个纳米线，所述第二方向垂直于所述第一方向，其中，每个所述纳米线与直接相邻的纳米线间隔开；栅极结构，位于所述纳米线结构的第一区域上方以第三方向延伸，所述第三方向垂直于所述第一方向和所述第二方向，并且所述栅极结构包括栅电极；源极/漏极区，设置在所述纳米线结构的第二区域上方，所述纳米线结构的第二区域位于所述栅极结构的相对两侧上，其中，所述栅电极包裹环绕每个所述纳米线，以及当在沿着所述第三方向截取的截面图中观察时，所述纳米线结构中的每个所述纳米线的形状不同于所述纳米线结构中的其他纳米线的形状，并且所述纳米线结构中的每个所述纳米线具有与所述纳米线结构中的其他所述纳米线相同的截面面积。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：至少一个纳米线结构，设置在半导体衬底上并且在所述半导体衬底上以第一方向延伸，其中，每个所述纳米线结构包括沿着所述第一方向延伸并且在第二方向上布置的多个纳米线，所述第二方向垂直于所述第一方向，其中，每个所述纳米线与其他相邻的纳米线间隔开；栅极结构，在所述纳米线结构的第一区域上方以第三方向延伸，所述第三方向垂直于所述第一方向和所述第二方向，并且所述栅极结构包括栅电极；源极/漏极区，设置在所述纳米线结构的第二区域上方，所述纳米线结构的第二区域位于所述栅极结构的相对两侧上，其中，所述栅电极包裹环绕每个所述纳米线，以及当在沿着所述第二方向截取的截面图中观察时，比相邻的第二纳米线离衬底更远的第一纳米线具有比所述第二纳米线更长的在所述第三方向上延伸的长度，并且所述第一纳米线具有比所述第二纳米线更短的在所述第二方向上延伸的宽度。
根据本发明的又一些实施例，还提供了一种制造半导体器件的方法，包括：在衬底上方形成在第二方向上交替堆叠的第一半导体层和第二半导体层的堆叠结构；将所述堆叠结构图案化成沿着第一方向延伸的鳍结构，所述第一方向垂直于所述第二方向；去除位于相邻的第二半导体层之间的所述第一半导体层的部分以形成纳米线结构；在所述纳米线结构的第一部分上方形成在第三方向上延伸的栅极结构，从而使得所述栅极结构包裹环绕所述第二半导体层，所述第三方向垂直于所述第一方向和所述第二方向；在所述纳米线结构的第二部分上方形成源极/漏极区，所述纳米线结构的第二部分位于所述纳米线结构的相对两侧上，从而使得所述源极/漏极区包裹环绕所述第二半导体层，其中，离所述衬底最远的第二半导体层在所述第二方向上延伸的厚度大于所述纳米线结构中的其他第二半导体层在所述第二方向上延伸的厚度，并且离所述衬底最近的第二半导体层在所述第二方向上延伸的厚度小于所述纳米线结构中的其他第二半导体层在所述第二方向上延伸的厚度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据本发明的GAA FET器件的实施例的平面图。
图2至图17示出根据本发明的实施例的用于制造GAA FET器件的示例性顺序工艺。
图18示出根据本发明的另一实施例的GAA FET器件的示例性结构。
图19至图22示出根据本发明的另一实施例的用于制造GAA FET器件的示例性顺序工艺。
图23是示出本发明的实施例的示出漏致势垒降低(DIBL)与鳍宽度之间的关系的图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸并不限于所公开的范围或者数值，但是可以取决于工艺条件和/或器件的期望性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，可以以不同尺寸任何绘制各个部件。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。另外，术语“由...制成”可以意为“包括”或者“由...组成”。
图1是根据本发明的GAA FET器件的实施例的平面图。
图2至图17示出根据本发明的实施例的用于制造GAA FET器件的示例性顺序工艺。应该理解，可在图2至图17示出的工艺之前、期间和之后提供额外的操作，并且对于本方法的特定实施例，可以替代或消除下面描述的一些操作。可互换操作/工艺的顺序。
图1示出GAA FET器件的平面图。如图1所示，在纳米线结构180上方形成栅电极结构160。虽然在图1中示出两个鳍结构和两个栅极结构，根据本发明GAA FET器件可以包括一个或三个或多个鳍结构和一个或三个或多个栅电极结构。
如图2所示，在衬底10上方形成堆叠的半导体层。堆叠的半导体层包括第一半导体层20和第二半导体层25。图2是沿着图1的线A-A截取的截面图。
在一个实施例中，衬底10包括位于至少其表面部分上的单晶半导体层。衬底10可以包括诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP的单晶半导体材料。在特定的实施例中，衬底10由Si制成。
衬底10可以包括位于其表面区域中的一个或多个缓冲层(未示出)。缓冲层可以用于逐渐改变晶格常数，使晶格常数从衬底的晶格常数改变到源极/漏极区的晶格常数。缓冲层可以由诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP的外延生长的单晶半导体材料形成。在特定实施例中，在硅衬底10上外延生长硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度从用于最底部缓冲层的30％的原子比增加到最顶部缓冲层的70％的原子比。
第一半导体层20和第二半导体层25由具有不同晶格常数的材料制成并且可以包括诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP的一层或多层。
在一些实施例中，第一半导体层20和第二半导体层25由Si、Si化合物、SiGe、Ge或Ge化合物制成。在一个实施例中，第一半导体层20是Si或Si1-yGey，这里y小于约0.4，并且第二半导体层25是Si1-xGex，这里x大于约0.3，或者Ge(x＝1.0)，并且x＞y。在本发明中，“M”化合物或“M”基化学物意味着化合物的大多数是M。
在另一实施例中，第二半导体层25是Si或Si1-xGex，这里x小于约0.4，或Ge，并且第一半导体层20是Si1-yGey，这里y大于约0.4，并且x＜y。
在又一其他实施例中，第二半导体层25由Si1-xGex制成，这里x是在从约0.3至约0.8的范围内，并且第一半导体层20由Si1-yGey制成，这里y是在从约0.1至约0.4的范围，并且x＞y。
在图2中，设置三层第一半导体层20和三层第二半导体层25。然而，层的数目不限于三，并且可以小到1(每层)并且在一些实施例中，形成2层-10层的每个第一半导体层和第二半导体层。通过调整堆叠层的数目，可以调整GAA FET器件的驱动电流。
在衬底10上方外延地形成第一半导体层20和第二半导体层25。在一些实施例中，每个第一半导体层20的厚度可以彼此相等，并且在从约5nm至约50nm的范围内，并且在其他实施例中是在从约10nm至约30nm的范围内。在一些实施例中，底部第一半导体层20(离衬底10最近的层)比其他的第一半导体层更厚。在一些实施例中，底部第一半导体层的厚度为在从约10nm至50nm的范围内，并且在其他实施例中，该厚度在从约20nm至约40nm的范围内。
在一些实施例中，第二半导体层25的厚度在从约5nm至约100nm的范围内，并且在其他的实施例中，该厚度在从约10nm至约50nm的范围内。每个第二半导体层25的厚度随着与衬底10的距离的增加而增加。例如，底部第二半导体层25具有厚度t1。相邻的中间第二半导体层25的厚度t2大于底部第二半导体层的厚度t1，并且顶部第二半导体层的厚度t3大于中间第二半导体层的厚度t2。
接着，如图3所示，在堆叠层上方形成掩模层30。在一些实施例中，掩模层30包括第一掩模层32、第二掩模层34和第三掩模层36。第一掩模层32是由氧化硅制成的焊盘氧化物层，其可以通过热氧化形成。第二掩模层34由氮化硅(SiN)制成，并且第三掩模层36由氧化硅制成，通过包括低压CVD(LPCVD)和等离子体增强CVD(PECVD)的化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或其他合适的工艺形成第二掩模层和第三掩模层两者。如图4所示，通过使用包括光刻和蚀刻的图案化操作将掩模层30图案化成掩模图案38。
接着，如图5所示，是对应于图1的线B-B的截面图，通过使用掩模图案30图案化第一半导体层20和第二半导体层25的堆叠层。通过适当地选择蚀刻技术，图案化第二半导体层25，使得对于每个第二半导体层25，随着与衬底10的距离的增加，每个第二半导体层25的宽度在X方向上减小。例如，如图5所示，最接近衬底10的底部第二半导体层25的宽度W3大于相邻的中间第二半导体层25的宽度W2。中间第二半导体层W2的宽度大于离衬底10最远的顶部第二半导体层25的宽度W1。在一些实施例中，第二半导体层沿着X方向的宽度在从约4nm至约12nm的范围内。如果半导体层25的宽度小于约4nm，引线将太小并且可能断裂。如果半导体层25的宽度大于约12nm，引线将占据太大的间隔。每个鳍结构150包括底层15，底层是蚀刻的衬底的一部分。底层15的宽度W4大于最接近衬底10的第二半导体层25的宽度W3。在特定实施例中，底层15的宽度W4是约12nm并且顶部半导体层25的宽度W1是约4nm。在其他实施例中，底层15的宽度W4是约10nm并且顶部半导体层25的宽度W1是约6nm。鳍结构150沿着Z方向的高度H1在从约30nm至约100nm的范围内。
在特定实施例中，如图5所示，当在截面图中观察时，衬底的最上部第二半导体层25大致是梯形形状，并且较低的第二半导体层25大致是矩形形状。通过一系列光刻和蚀刻操作并且改变光刻和蚀刻参数来形成不同形状的第二半导体层25。例如，在特定的实施例中，对最上部第二半导体层实施各向同性蚀刻并且对较低的第二半导体层实施各向异性蚀刻。在特定实施例中，当在截面图中观察时，每个第二半导体层25具有大致相同的截面面积。在此使用的大致相同的截面面积是指每个第二半导体层25的截面面积在彼此的10％内。
形成鳍结构150后，在衬底上方形成包括一层或多层绝缘材料的隔离绝缘层50，从而使得鳍结构150完全嵌入绝缘层50中。用于绝缘层50的绝缘材料可以包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料。形成绝缘层50后，可实施退火操作。然后，如图6所示，实施诸如化学机械抛光(CMP)方法和/或回蚀刻方法的平坦化操作，从而使得从绝缘材料层暴露焊盘氧化物层32的上表面。在一些实施例中，暴露鳍结构150的上表面。
在一些实施例中，如图6所示，在图5的结构上方形成第一衬垫层42并且在第一衬垫层42上方进一步形成第二衬垫层44。第一衬垫层42由氧化硅或氧化硅基材料制成并且第二衬垫层44由SiN或氮化硅基材料制成。衬垫层42、44在诸如形成层间电介质或浅沟槽隔离的后续操作期间保护半导体层20、25免受氧化。
然后，如图7所示，实施蚀刻操作以凹进隔离绝缘层50以暴露部分鳍结构150。图7是对应于图1的线A-A的截面图。在特定的实施例中，如图7所示，底部第一半导体层20完全从隔离绝缘层暴露。在其他实施例中，底部第一半导体层嵌入隔离绝缘层50中或从隔离绝缘层50部分地暴露。
图8示出在鳍结构150上方形成牺牲栅极结构170后的结构。牺牲栅极结构170包括牺牲栅电极70和牺牲栅极介电层(未示出)。在鳍结构150的将成为沟道区的部分上方形成牺牲栅极结构170。牺牲栅极结构170限定GAA FET的沟道区。
通过在鳍结构150上方第一毯式沉积牺牲栅极介电层来形成牺牲栅极结构170。牺牲栅极介电层包括氧化硅、氮化硅或氮氧化硅的一层或多层。在一些实施例中，牺牲栅极介电层的厚度在从约1nm至约5nm的范围内。然后，在牺牲栅极介电层上和鳍结构10上方毯式沉积牺牲栅电极层，从而使得鳍结构150完全嵌在牺牲栅电极层中。牺牲栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中，牺牲栅电极层的厚度在从约100nm至约200nm的范围内。在一些实施例中，牺牲栅电极层经受平坦化操作。使用包括LPCVD和PECVD、PVD、ALD或其他合适的工艺的CVD沉积牺牲栅极介电层和牺牲栅电极层。
随后，在牺牲栅电极层上方形成掩模层71。掩模层71包括焊盘SiN层72和氧化硅掩模层74。
接着，如图8所示，对掩模层71实施图案化操作并且将牺牲栅电极层图案化成牺牲栅极结构170。通过图案化牺牲栅极结构170，在牺牲栅极结构170的相对侧上暴露第二半导体层25，作为源极/漏极(S/D)区。在本发明中，互换地使用源极和漏极并且源极和漏极的结构大致相同。
如图9所示，在形成牺牲栅极结构170后，去除鳍结构中的第一半导体层20，由此形成纳米线结构180，该纳米线结构180包括布置在Z方向上的第二半导体结构层25的多个堆叠的纳米线。在特定实施例中，当在截面图中观察时，每个堆叠的纳米线具有大致相同的截面面积。
使用相对于第二半导体层25选择性地蚀刻第一半导体层20的蚀刻剂以去除或蚀刻第一半导体层20。
当第一半导体层20是Ge或SiGe并且第二半导体层25是Si时，可使用湿蚀刻剂选择性地去除第一半导体层20，湿蚀刻剂诸如但不限于过氧化氢(H2O2)/氢氧化铵(NH4OH)溶液、硝酸(HNO3)/乙酸(CH3COOH)溶液或氢氟酸(HF)/过氧化氢/乙酸溶液。
当第一半导体层20是Si并且第二半导体层25是Ge或SiGe时，可使用湿蚀刻剂选择性地去除第一半导体层20，湿蚀刻剂诸如但不限于四甲基氢氧化铵(TMAH)溶液、乙二胺邻苯二酚(EDP)溶液或氢氧化钾(KOH)溶液。
在特定实施例中，一种纳米线结构是P型FET的一部分并且相邻的纳米线结构是N型FET的一部分。使用第一半导体层20以形成一种类型的FET的纳米线并且使用第二半导体层25以形成另一类型的FET的纳米线。在处理期间，通过使用合适的蚀刻剂选择性地蚀刻一种鳍结构的第一半导体层以形成一种纳米线结构并且通过诸如光刻胶层或介电层的保护层覆盖相邻的鳍结构。当选择性地蚀刻相邻的鳍结构的第二半导体层以形成第二纳米线结构时，保护层覆盖该一种纳米线结构。
如图10所示，在一些实施例中，通过使用CVD或其他合适的方法共性地形成用于侧壁间隔件的绝缘材料的毯式层77。以共形的方式沉积毯式层77，从而使得毯式层形成为在诸如牺牲栅极结构的侧壁、水平表面和顶部的垂直表面上具有大致相同的厚度。在一些实施例中，毯式层77沉积为具有在从约2nm至约10nm的范围内的厚度。在一个实施例中，毯式层77的绝缘材料是诸如SiN、SiON、SiOCN或SiCN和它们的组合的氮化硅基材料。
此外，如图11所示，在牺牲栅极结构170的相对侧壁上形成侧壁间隔件75。形成毯式层77后，例如，使用反应离子蚀刻(RIE)对毯式层77实施各向异性蚀刻。在各向异性蚀刻工艺期间，从水平表面去除大部分绝缘材料，留下位于诸如牺牲栅极结构的侧壁和暴露的纳米线结构的侧壁的垂直表面上的介电间隔层。可从侧壁间隔件75暴露掩模层74。
如图12所示，在从侧壁间隔件暴露至少纳米线结构180的上部后，在纳米线结构180的暴露的部分上和周围形成源极/漏极(S/D)层80。图12是对应于图1的线C-C的截面图。
用于S/D层80的材料包括用于P型FET的Ge或SiGe的一层或多层，以及用于N型FET的Si、SiP或SiC的一层或多层。
通过使用CVD、ALD或分子束外延(MBE)的外延生长方法形成S/D层80。当形成用于P型FET的S/D层80时，通过诸如SiN的保护层覆盖N型FET的纳米线结构180，并且当形成用于N型FET的S/D层80时，通过保护层覆盖P型FET的纳米线结构180。
图13和图14，对应于图1的线C-C的截面图，示出了在本发明的可选实施例中的源极/漏极区80的图。在图12中，在图9的制造阶段中完全地去除了第一半导体层。S/D层80形成为完全围绕第二半导体层25，并且可以最大化S/D层80的表面面积。在图13中，在图9的制造阶段中，部分地蚀刻第一半导体层20。在这种情况下，维持了通过剩余的第一半导体层20对第二半导体层25施加的应力，同时可以获得S/D层80的相对较大的表面面积。在图14中，在图9的制造阶段中，未蚀刻位于第二半导体层25下面的第一半导体层20。在这种情况下，可以最大化通过剩余的第一半导体层20对第二半导体层25施加的应力。使用各向同性蚀刻以去除图9和图13中的第一半导体层，而使用各向异性蚀刻以形成图14中的结构。
如图15所示，形成S/D层后，在整个结构上方形成层间介电层(ILD)90，并且然后通过CMP操作平坦化层间介电层90的上部，从而暴露牺牲栅电极层70的上表面，去除牺牲栅电极70和牺牲栅极介电层，从形成栅极空间98，因此暴露纳米线结构180，其随后变成FET的沟道层，并且在栅极空间98中形成栅极介电层100。图15是对应于图1的线D-D的截面图。
用于ILD层90的材料包括诸如SiCOH和SiOC的含有Si、O、C和/或H的化合物。诸如聚合物的有机材料可用于ILD层90。此外，在一些实施例中，形成ILD层90之前，在形成ILD层90之前在结构上方形成氧化硅层和氮化硅层。也可以在ILD层90上方形成SiN硬掩模层92。
ILD层50在牺牲栅极结构170的去除期间保护S/D结构80。使用等离子体干蚀刻和/或湿蚀刻可以去除牺牲栅极结构170。当牺牲栅电极70是多晶硅并且ILD层90是氧化硅时，可以使用诸如TMAH溶液的湿蚀刻剂选择性地去除牺牲栅电极70。其后，使用等离子体干蚀刻和/或湿蚀刻去除牺牲栅极介电层。
如图16和图17所示，在围绕每个沟道层(第二半导体层25)形成栅极介电层100后，在栅极介电层100上形成栅电极层110。图16是对应于图1的线D-D的截面图并且图17是对应于图1的线B-B的截面图。
在特定实施例中，栅极介电层100包括一层或多层介电材料，诸如氧化硅、氮化硅或高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层100包括在沟道层和介电材料之间形成的界面层(未示出)。
可通过CVD、ALD或任何其他合适的方法来形成栅极介电层100。在一个实施例中，使用诸如ALD的高度共形的沉积工艺形成栅极介电层100以确保围绕每个沟道层形成的栅极介电层具有均匀的厚度。在一个实施例中，栅极介电层100的厚度在从约1nm至约6nm的范围内。
在栅极介电层100上形成栅电极层110以围绕每个沟道层。栅电极层110包括一层或多层导电材料，诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合。
可以通过CVD、ALD，电镀或其他合适的方法来形成栅电极层110。也在ILD层90的上表面上方沉积栅电极层。然后通过使用例如CMP平坦化在ILD层90上方形成的栅极介电层和栅电极层，直到暴露ILD层90的顶面，以形成栅电极结构160。
在本发明的特定实施例中，可在栅极介电层100与栅电极110之间插入一个或多个功函数调整层(未示出)。功函数调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或者两种以上的这些材料的多层的导电材料制成。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种可用作功函调整层，并且对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函数调整层。可通过ALD、PVD、CVD、电子束蒸发或其他适当的工艺来形成功函数调整层。此外对于可以使用不同的金属层的N型FET和P型FET，可以分别形成功函数调整层。
本发明不限于包括三个堆叠的纳米线的鳍结构。在特定的实施例中，每个纳米线结构180中可以包括额外的纳米线。例如，如图18所示，对应于图1的线C-C的截面图。纳米线结构180中包括四个或更多个纳米线。此外，最上部的纳米线是梯形形状是不必要的。如图18所示，在特定实施例中，最上部纳米线或所有的纳米线大致是矩形形状。在特定实施例中，改变纳米线的长度和宽度，从而使得每个纳米线的截面面积大致相同。
如图19所示，在本发明的一些实施例中，在图6的结构上方形成掩模层60。掩模层60由诸如SiN、SiON或SiCN的氮化硅基材料制成，这些氮化硅基材料相对于绝缘隔离层50具有较高的蚀刻选择性。
随后，如图20所示，图20是对应于图1的线A-A的截面图，通过使用光刻和蚀刻操作图案化掩模层60以制造开口并且通过该开口凹进隔离绝缘层50，从而暴露部分的鳍结构150。鳍结构150的端部掩埋在隔离绝缘层中，因此在后续处理期间形成固定第二半导体层25的固定结构55。
如图21所示，从绝缘隔离层50暴露鳍结构150后，去除鳍结构中的第一半导体层20，因此形成纳米线结构180，该纳米线结构180包括布置在Z方向上的第二半导体结构层25的多个纳米线。在特定实施例中，当在截面图中观察时，每个纳米线具有大致相同的截面面积。在鳍结构150的端部处形成固定结构55，所以当在制造工艺的这个阶段中去除鳍结构150中的第一半导体层20中时，可通过固定结构支撑第二半导体层25的纳米线。通过使用固定结构，在形成源极/漏极层之前制造沟道层(例如，引线)成为可能。
如图22所示，以与图8中的牺牲栅极结构相同的方式，随后在纳米线结构180上方形成牺牲栅极结构170。牺牲栅极结构170包括牺牲栅电极70和牺牲栅极介电层(未示出)。随后以与图10-图17中描述的类似的方式处理图22的结构以形成半导体器件。
应当理解，GAA FET可经历进一步的CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各种部件。
本文描述的各个实施例或实例提供了优于现有技术的一些优势。在GAA FET中，在蚀刻的Si或SiGe堆叠层上完全地或部分地外延生长源极/漏极层，这增加了用于接触件接合的表面面积。本发明通过在鳍结构内提供具有大致相等的截面面积的纳米线实现了性能的提高。根据本发明的GAA FET器件提供了改进的短沟道效应控制。此外，如图23所示，根据本发明的GAA FET提供了对于沿着Z方向垂直布置的每个纳米线的大致恒定的漏致势垒降低(DIBL)。图23示出随着X方向上的纳米线的宽度的增加，诸如图18中所示的四个纳米线布置的相对DIBL。菱形形状表示最上部的纳米线，X形状表示最下部的纳米线，三角形形状表示与最下部纳米线相邻的纳米线，并且正方形形状表示与最上部的纳米线相邻的纳米线。如图18所示，纳米线在X方向上的宽度沿着Z方向减小。如图23所示，当根据本发明将纳米线布置为具有沿着Z方向逐渐减小的宽度，同时在截面中维持大致相同的面积，用于每个纳米线的DIBL是大致恒定的。另一方面，如果每个纳米线的宽度是相同的，对于垂直布置的纳米线中的每个纳米线，DIBL中实质上存在较大的变化。
应该理解，在此不必讨论所有优势，没有特定的优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同的优势。
本发明的实施例是一种半导体器件，该半导体器件包括至少一种纳米线结构，该纳米线结构设置在半导体衬底上并且在半导体衬底上的第一方向上延伸。每个纳米线结构包括沿着第一方向延伸并且在第二方向上布置的多个纳米线，第二方向大致垂直于第一方向。每个纳米线与直接相邻的纳米线隔开。栅极结构在纳米线结构的第一区域上方的第三方向上延伸，并且第三方向大致垂直于第一方向和第二方向两者。栅极结构包括栅电极。在纳米线结构的第二区域上方设置源极/漏极区，纳米线结构的第二区域位于栅极结构的相对侧上。栅电极包裹环绕每个纳米线。当在沿着第三方向截取的截面图中观察时，纳米线结构中的每个纳米线的形状不同于纳米线结构中的其他纳米线的形状，并且该纳米线结构中的每个纳米线具有与纳米线结构中的其他纳米线大致相同的截面面积。
本发明的另一实施例是一种半导体器件，该半导体器件包括至少一种纳米线结构，该纳米线结构设置在半导体衬底上并且在半导体衬底上的第一方向上延伸。每个纳米线结构包括沿着第一方向延伸并且布置在第二方向上的多个纳米线，第二方向大致垂直于第一方向。每个纳米线与其他相邻的纳米线隔开。栅极结构在纳米线结构的第一区域上方的第三方向上延伸，第三方向大致垂直于第一方向和第二方向两者。栅极结构包括栅电极。在纳米线结构的第二区域上方设置源极/漏极区，纳米线结构的第二区域位于栅极结构的相对侧上。栅电极包裹环绕每个纳米线。当在沿着第二方向截取的截面图中观察时，比相邻的第二纳米线进一步远离衬底的第一纳米线具有比第二纳米线更长在第三方向上延伸的长度，并且第一纳米线具有比第二纳米线更短的在第二方向上延伸的宽度。
本发明的另一实施例是一种制造半导体器件的方法。该方法包括在衬底上方的第二方向上形成交替堆叠的第一半导体层和第二半导体层的堆叠结构。将堆叠的结构图案化成沿着第一方向延伸的鳍结构，第一方向大致垂直于第二方向。在相邻的第二半导体层之间去除部分第一半导体层以形成纳米线结构。在纳米线结构的第一部分上方形成在第三方向上延伸的栅极结构，从而使得栅极结构包裹环绕第二半导体层。第三方向大致垂直于第一方向和第二方向两者。在位于纳米线结构的相对侧上的纳米线结构的第二部分上方形成源极/漏极区，从而使得源极/漏极区包裹环绕第二半导体层。在第二方向上延伸的离衬底最远的第二半导体层的厚度大于纳米线结构中的其他第二半导体层的厚度，并且在第二方向上延伸的离衬底最近的第二半导体层的厚度小于纳米线结构中的其他第二半导体层的厚度。
根据本发明的一些实施例，提供了一种半导体器件，包括：至少一个纳米线结构，设置在半导体衬底上并且在所述半导体衬底上以第一方向延伸，其中，每个所述纳米线结构包括沿着所述第一方向延伸并且在第二方向上布置的多个纳米线，所述第二方向垂直于所述第一方向，其中，每个所述纳米线与直接相邻的纳米线间隔开；栅极结构，位于所述纳米线结构的第一区域上方以第三方向延伸，所述第三方向垂直于所述第一方向和所述第二方向，并且所述栅极结构包括栅电极；源极/漏极区，设置在所述纳米线结构的第二区域上方，所述纳米线结构的第二区域位于所述栅极结构的相对两侧上，其中，所述栅电极包裹环绕每个所述纳米线，以及当在沿着所述第三方向截取的截面图中观察时，所述纳米线结构中的每个所述纳米线的形状不同于所述纳米线结构中的其他纳米线的形状，并且所述纳米线结构中的每个所述纳米线具有与所述纳米线结构中的其他所述纳米线相同的截面面积。
在上述半导体器件中，当在截面图中观察时，离所述衬底最远的所述纳米线是梯形形状。
在上述半导体器件中，当在截面图中观察时，离所述衬底最近的所述纳米线是矩形形状。
在上述半导体器件中，当在截面图中观察时，比相邻的第二纳米线离所述衬底更远的第一纳米线具有比所述第二纳米线更长的在所述第二方向上延伸的长度。
在上述半导体器件中，当在截面图中观察时，比相邻的所述第二纳米线离所述衬底更远的第一纳米线具有比所述第二纳米线更短的在所述第三方向上延伸的宽度。
在上述半导体器件中，在所述纳米线结构中直接相邻的纳米线以相同的距离间隔开。
在上述半导体器件中，所述纳米线包括SiGe。
在上述半导体器件中，所述源极/漏极区包裹环绕所述纳米线。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：至少一个纳米线结构，设置在半导体衬底上并且在所述半导体衬底上以第一方向延伸，其中，每个所述纳米线结构包括沿着所述第一方向延伸并且在第二方向上布置的多个纳米线，所述第二方向垂直于所述第一方向，其中，每个所述纳米线与其他相邻的纳米线间隔开；栅极结构，在所述纳米线结构的第一区域上方以第三方向延伸，所述第三方向垂直于所述第一方向和所述第二方向，并且所述栅极结构包括栅电极；源极/漏极区，设置在所述纳米线结构的第二区域上方，所述纳米线结构的第二区域位于所述栅极结构的相对两侧上，其中，所述栅电极包裹环绕每个所述纳米线，以及当在沿着所述第二方向截取的截面图中观察时，比相邻的第二纳米线离衬底更远的第一纳米线具有比所述第二纳米线更长的在所述第三方向上延伸的长度，并且所述第一纳米线具有比所述第二纳米线更短的在所述第二方向上延伸的宽度。
在上述半导体器件中，当在截面图中观察时，离所述衬底最远的纳米线是梯形形状。
在上述半导体器件中，当在截面图中观察时，离所述衬底最近的纳米线是矩形形状。
在上述半导体器件中，在所述纳米线结构中直接相邻的纳米线以相同的距离间隔开。
在上述半导体器件中，所述源极/漏极区包裹环绕所述纳米线。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：在衬底上方形成在第二方向上交替堆叠的第一半导体层和第二半导体层的堆叠结构；将所述堆叠结构图案化成沿着第一方向延伸的鳍结构，所述第一方向垂直于所述第二方向；去除位于相邻的第二半导体层之间的所述第一半导体层的部分以形成纳米线结构；在所述纳米线结构的第一部分上方形成在第三方向上延伸的栅极结构，从而使得所述栅极结构包裹环绕所述第二半导体层，所述第三方向垂直于所述第一方向和所述第二方向；在所述纳米线结构的第二部分上方形成源极/漏极区，所述纳米线结构的第二部分位于所述纳米线结构的相对两侧上，从而使得所述源极/漏极区包裹环绕所述第二半导体层，其中，离所述衬底最远的第二半导体层在所述第二方向上延伸的厚度大于所述纳米线结构中的其他第二半导体层在所述第二方向上延伸的厚度，并且离所述衬底最近的第二半导体层在所述第二方向上延伸的厚度小于所述纳米线结构中的其他第二半导体层在所述第二方向上延伸的厚度。
在上述方法中，在离所述衬底最远的第二半导体层在所述第三方向上的宽度小于所述纳米线结构中的其他第二半导体层在所述第三方向上的宽度，并且在离所述衬底最近的第二半导体层在所述第三方向上的宽度大于所述纳米线结构中的其他第二半导体层在所述第三方向上的宽度。
在上述方法中，将所述堆叠结构图案化成所述鳍结构包括：各向同性地蚀刻离所述衬底最远的第二半导体层；以及各向异性蚀刻离所述衬底较近的另一第二半导体层。
在上述方法中，还包括：在所述鳍结构上方形成隔离绝缘层；在所述隔离绝缘层上方形成覆盖层；图案化所述覆盖层以形成开口和剩余的边界部分；以及通过所述开口凹进所述隔离绝缘层以暴露所述鳍结构的中心区域，从而使得所述鳍结构的端部区域仍然掩埋在所述隔离绝缘层中，以及其中，在相邻的第一半导体层之间去除的所述第一半导体层的所述部分位于所述中心区域中。
在上述方法中，形成所述栅极结构包括：形成包裹环绕所述第二半导体层的共形的栅极介电层；以及在包裹环绕所述第二半导体层的所述栅极介电层上形成栅电极。
在上述方法中，通过各向同性地蚀刻位于相邻的第二半导体层之间的所述第一半导体层，来去除位于相邻的第二半导体层之间的所述第一半导体层的所述部分。
在上述方法中，所述第一半导体层形成为在所述第二方向上具有相同的厚度。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种半导体器件，包括：
至少一个纳米线结构，设置在半导体衬底上并且在所述半导体衬底上以第一方向延伸，
其中，每个所述纳米线结构包括沿着所述第一方向延伸并且在第二方向上布置的多个纳米线，所述第二方向垂直于所述第一方向，
其中，每个所述纳米线与直接相邻的纳米线间隔开；
栅极结构，位于所述纳米线结构的第一区域上方以第三方向延伸，所述第三方向垂直于所述第一方向和所述第二方向，并且所述栅极结构包括栅电极；
源极/漏极区，设置在所述纳米线结构的第二区域上方，所述纳米线结构的第二区域位于所述栅极结构的相对两侧上，
其中，所述栅电极包裹环绕每个所述纳米线，以及
当在沿着所述第三方向截取的截面图中观察时，所述纳米线结构中的每个所述纳米线的形状不同于所述纳米线结构中的其他纳米线的形状，并且所述纳米线结构中的每个所述纳米线具有与所述纳米线结构中的其他所述纳米线相同的截面面积。
CN201611040115.9A 2016-06-10 2016-11-21 半导体器件及其制造方法 Pending CN107492568A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/179,008 US9691851B1 (en) 2016-06-10 2016-06-10 Semiconductor device and manufacturing method thereof
US15/179,008 2016-06-10

Publications (1)

Publication Number Publication Date
CN107492568A true CN107492568A (zh) 2017-12-19

Family

ID=59069619

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611040115.9A Pending CN107492568A (zh) 2016-06-10 2016-11-21 半导体器件及其制造方法

Country Status (2)

Country Link
US (2) US9691851B1 (zh)
CN (1) CN107492568A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110379808A (zh) * 2019-07-17 2019-10-25 上海华力集成电路制造有限公司 Cmos反相器
CN110491942A (zh) * 2018-05-14 2019-11-22 台湾积体电路制造股份有限公司 多栅极半导体装置和其形成方法
CN111199884A (zh) * 2018-11-19 2020-05-26 中芯国际集成电路制造（天津）有限公司 一种半导体器件及其形成方法
CN112951912A (zh) * 2019-12-10 2021-06-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404325B2 (en) * 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
US20170186607A1 (en) * 2015-12-28 2017-06-29 United Microelectronics Corp. Method of forming a semiconductor device
US10535780B2 (en) * 2017-05-08 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including an epitaxial layer wrapping around the nanowires
US10290548B2 (en) 2017-08-31 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with semiconductor wire
US10453736B2 (en) * 2017-10-09 2019-10-22 International Business Machines Corporation Dielectric isolation in gate-all-around devices
US10727320B2 (en) * 2017-12-29 2020-07-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of manufacturing at least one field effect transistor having epitaxially grown electrodes
US10431651B1 (en) * 2018-04-30 2019-10-01 International Business Machines Corporation Nanosheet transistor with robust source/drain isolation from substrate
US11374004B2 (en) 2018-06-29 2022-06-28 Intel Corporation Pedestal fin structure for stacked transistor integration
US11482522B2 (en) 2018-10-08 2022-10-25 Samsung Electronics Co., Ltd. Semiconductor devices including a narrow active pattern
US10868193B2 (en) 2018-11-09 2020-12-15 Samsung Electronics Co., Ltd. Nanosheet field effect transistor cell architecture
US11387362B2 (en) 2018-11-30 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
DE102019115490B4 (de) 2018-11-30 2022-10-20 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleiter-bauelement und verfahren zu dessen herstellung
KR20200135662A (ko) 2019-05-24 2020-12-03 삼성전자주식회사 반도체 장치
KR20200136519A (ko) * 2019-05-27 2020-12-08 삼성전자주식회사 반도체 장치
US11183584B2 (en) * 2020-01-17 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11282838B2 (en) 2020-07-09 2022-03-22 International Business Machines Corporation Stacked gate structures
US11575047B2 (en) * 2021-05-12 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device active region profile and method of forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893492B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
US8722472B2 (en) * 2011-12-16 2014-05-13 International Business Machines Corporation Hybrid CMOS nanowire mesh device and FINFET device
US8735869B2 (en) 2012-09-27 2014-05-27 Intel Corporation Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
US20140151757A1 (en) * 2012-12-03 2014-06-05 International Business Machines Corporation Substrate-templated epitaxial source/drain contact structures
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
US9171843B2 (en) * 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
US9764950B2 (en) 2013-08-16 2017-09-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with one or more semiconductor columns
WO2015050546A1 (en) * 2013-10-03 2015-04-09 Intel Corporation Internal spacers for nanowire transistors and method of fabrication thereof
US9224833B2 (en) 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company Limited Method of forming a vertical device
US9653563B2 (en) 2014-04-18 2017-05-16 Taiwan Semiconductor Manufacturing Company Limited Connection structure for vertical gate all around (VGAA) devices on semiconductor on insulator (SOI) substrate
US9281363B2 (en) * 2014-04-18 2016-03-08 Taiwan Semiconductor Manufacturing Company Ltd. Circuits using gate-all-around technology
US9251888B1 (en) 2014-09-15 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cells with vertical gate-all-round MOSFETs

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491942A (zh) * 2018-05-14 2019-11-22 台湾积体电路制造股份有限公司 多栅极半导体装置和其形成方法
CN111199884A (zh) * 2018-11-19 2020-05-26 中芯国际集成电路制造（天津）有限公司 一种半导体器件及其形成方法
CN111199884B (zh) * 2018-11-19 2023-08-22 中芯国际集成电路制造（天津）有限公司 一种半导体器件及其形成方法
CN110379808A (zh) * 2019-07-17 2019-10-25 上海华力集成电路制造有限公司 Cmos反相器
CN112951912A (zh) * 2019-12-10 2021-06-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112951912B (zh) * 2019-12-10 2024-05-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US9691851B1 (en) 2017-06-27
US10090157B2 (en) 2018-10-02
US20170358646A1 (en) 2017-12-14

Similar Documents

Publication Publication Date Title
US11776852B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
US11798989B2 (en) Strained nanowire CMOS device and method of forming
CN107492568A (zh) 半导体器件及其制造方法
US20240071834A1 (en) Method of manufacturing a semiconductor device and a semiconductor device
CN109427870B (zh) 半导体结构及其形成方法
CN106876275A (zh) 半导体器件及其制造方法
CN109427672A (zh) 半导体器件的制造方法及半导体器件
CN107017205A (zh) 半导体器件及其制造方法
CN106816381A (zh) 半导体装置及其制造方法
CN108122846A (zh) 包括鳍式场效应晶体管的半导体器件及其形成方法
TWI772699B (zh) 半導體元件的製造方法及其元件
CN107464840A (zh) 半导体器件及其制造方法
CN107527801A (zh) 半导体器件及其形成方法
CN108122967A (zh) 一种制造具有多层沟道结构的半导体器件的方法
US11823957B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
US20230411215A1 (en) Method of manufacturing a semiconductor device and a semiconductor device
US11894446B2 (en) Method of manufacturing a semiconductor device
US11973129B2 (en) Semiconductor device structure with inner spacer layer and method for forming the same
TWI764546B (zh) 半導體裝置與其製造方法
US11756997B2 (en) Semiconductor structure and method for forming the same
CN113140511A (zh) 半导体器件及其制造方法
US20230215929A1 (en) Metal gate cap
US20220285512A1 (en) Semiconductor Device With Gate Isolation Features And Fabrication Method Of The Same
TWI748210B (zh) 製造半導體裝置的方法與半導體裝置
US20240105794A1 (en) Field effect transistor with gate electrode having multiple gate lengths

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20171219