CN106816381A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN106816381A
CN106816381A CN201610663504.0A CN201610663504A CN106816381A CN 106816381 A CN106816381 A CN 106816381A CN 201610663504 A CN201610663504 A CN 201610663504A CN 106816381 A CN106816381 A CN 106816381A
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layer
sacrifice
semiconductor layer
semiconductor
fin structure
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CN106816381B (zh
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冯家馨
江国诚
梁英强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供半导体装置及其制造方法。半导体装置包含多个第一通道层设置于基底之上,第一源极/漏极区设置于基底之上,栅极介电层设置于每一个第一通道层之上,且包裹每一个第一通道层,栅极电极层设置于栅极介电层之上且包裹每一个第一通道层,以及衬垫半导体层设置于第一通道层与第一源极/漏极区之间。

Description

半导体装置及其制造方法
技术领域
本公开涉及半导体集成电路,且特别涉及具有环绕式栅极(gate-all-around)结构的半导体装置及其制造方法。
背景技术
随着半导体工业演进至纳米技术工艺节点以追求更高的装置密度、更高的效能与更低的成本,来自于制造与设计问题的挑战进而发展出了三维(three-dimensional)设计,如多栅极场效晶体管(field effect transistor,FET),其包含鳍型场效晶体管(FinFET)及环绕式栅极(gate-all-around,GAA)场效晶体管。在鳍型场效晶体管中,栅极电极相邻于通道区的三个侧面,且具有栅极介电层插入于其间。因栅极结构环绕(包裹)于鳍部的三个侧面上,晶体管基本上具有三个栅极控制通过鳍部或通道区的电流。遗憾的是,第四个侧面通道的底部远离于栅极电极,致使不在栅极的紧密控制之下。反之,在环绕式栅极场效晶体管中,通道区的全部侧面被栅极电极环绕,其允许通道区中更充分的耗尽(depletion),且因为更陡的次临界电流摆幅(sub-threshold current swing,SS)及更小的漏极引发能障降低(drain induced barrier lowering,DIBL)而产生较少的短通道效应(short-channeleffect)。
随着晶体管尺寸持续缩小至次10~15纳米技术工艺节点,需要更进一步改良环绕式栅极场效晶体管。
发明内容
根据本公开的一方面,在半导体装置的制造方法中,于基底之上,沿第一方向形成第一半导体层夹设于第二半导体层之间。图案化第一半导体层与第二半导体层形成鳍结构,使得鳍结构包含由第二半导体层形成的牺牲层及由第一半导体层形成的通道层。形成牺牲栅极结构于鳍结构之上,使得牺牲栅极结构覆盖鳍结构的一部分,且保持露出鳍结构的剩余部分。移除未被牺牲栅极结构覆盖的鳍结构的剩余部分。使牺牲层水平地凹入,使得牺牲层的边缘位于牺牲栅极结构的侧面之下。形成衬垫外延层,至少位于牺牲层的凹入的表面上。形成源极/漏极区。移除牺牲栅极结构。在移除牺牲栅极结构后,移除在鳍结构中的牺牲层,使得通道层露出。形成栅极介电层及栅极电极层,于露出的通道层周围。
在本公开的制造方法的一个实施方式中,通过湿蚀刻分别移除在该鳍结构中的该牺牲层及在该源极/漏极区中的该第一半导体层。
在本公开的制造方法的另一个实施方式中,多个该第一半导体层及所述多个第二半导体层交互地形成于该基底之上;以及在该鳍结构中,所述多个牺牲层及多个该通道层交互地堆叠。
在本公开的制造方法的另一个实施方式中,该通道层由硅或以硅为主的化合物制成。
在本公开的制造方法的另一个实施方式中,该第二半导体层由硅锗(SiGe)制成。
在本公开的制造方法的另一个实施方式中,在通过图案化该第一半导体层及该第二半导体层形成该鳍结构的该步骤中,形成多个鳍结构沿平行于该基底的一表面的一水平方向排列;以及在形成该牺牲栅极结构的该步骤中,该牺牲栅极结构覆盖多个该鳍结构的每一个的一部分。
在本公开的制造方法的另一个实施方式中,该衬垫外延层为未掺杂的硅。
在本公开的制造方法的另一个实施方式中,在该通道层的该凹入的表面上的该衬垫外延层的厚度范围从1纳米至4纳米。
在本公开的制造方法的另一个实施方式中,于使所述多个牺牲层凹入的该步骤中,也使该通道层水平地凹入。
在本公开的制造方法的另一个实施方式中,该牺牲层的一凹入的量大于该通道层的一凹入的量。
在本公开的制造方法的另一个实施方式中,该衬垫外延层也形成于该通道层的该凹入的表面上。
在本公开的制造方法的另一个实施方式中,在该牺牲层的该凹入的表面上的该衬垫外延层的厚度范围从5纳米至10纳米。
在本公开的制造方法的另一个实施方式中,在该通道层的该凹入的表面上的该衬垫外延层的厚度为在该牺牲层的该凹入的表面上的该衬垫外延层的厚度的20%至60%。
在本公开的制造方法的另一个实施方式中,该源极/漏极区与该衬垫外延层接触。
在本公开的制造方法的另一个实施方式中,该衬垫外延层包含硅(Si)、磷化硅(SiP)和碳磷化硅(SiCP)的至少一者。
根据本公开的另一方面,在半导体装置的制造方法中,于基底之上,沿第一方向形成第一半导体层夹设于第二半导体层之间。图案化第一半导体层与第二半导体层形成鳍结构,使得鳍结构包含由第二半导体层形成的牺牲层及由第一半导体层形成的通道层,形成牺牲栅极结构于鳍结构之上,使得牺牲栅极结构覆盖鳍结构的一部分,且保持露出鳍结构的剩余部分。移除未被牺牲栅极结构覆盖的鳍结构的剩余部分。形成衬垫外延层,至少位于牺牲层的凹入的表面上。形成源极/漏极区。移除牺牲栅极结构。在移除牺牲栅极结构后,移除在鳍结构中的牺牲层,使得通道层露出。形成栅极介电层及栅极电极层,于露出的通道层周围。
根据本公开的另一方面,半导体装置包含第一通道层设置于基底之上,第一源极/漏极区设置于基底之上,栅极介电层设置于每一个第一通道层之上,且包裹每一个第一通道层,栅极电极层设置于栅极介电层之上,且包裹每一个第一通道层,以及衬垫半导体层设置于第一通道层与第一源极/漏极区之间。
在本公开的半导体装置的一个实施方式中,所述多个第一通道层由硅或以硅为主的化合物制成。
在本公开的半导体装置的另一个实施方式中,该衬垫半导体层由硅或以硅为主的化合物制成。
在本公开的半导体装置的另一个实施方式中,该衬垫半导体层设置于该栅极介电层与该栅极电极层与该第一源极/漏极区之间。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是,根据本产业的一般作业,图示中的各种特征部件并未必按照比例绘制,而仅用于说明的目的。事实上,可能任意的放大或缩小各种特征部件的尺寸,以做清楚的说明。
图1-图20C显示依据本公开的一实施例的制造环绕式栅极场效晶体管装置的示例性连续工艺。
其中,附图标记说明如下:
10~基底;
11~阱区部;
12~掺杂物;
15~掩模层;
15A~第一掩模层;
15B~第二掩模层;
20~第一半导体层;
25~第二半导体层;
30~鳍结构;
35~第一衬垫层;
40~隔离绝缘层;
41~绝缘层;
50、50'~牺牲栅极结构;
52~牺牲栅极介电层;
53~毯覆层;
54~牺牲栅极电极层;
55~侧壁间隔元件;
56~接垫氮化硅层;
58~氧化硅掩模层;
70~衬垫外延层;
80~源极/漏极外延层;
82~孔洞;
90~第二衬垫层;
95~层间介电层;
102、102B~栅极介电层;
102A~界面层;
104~栅极电极层;
106~盖绝缘层;
110~接触孔;
120~硅化物层;
130~导电材料;
A1~区域;
W1~宽度;
H1~高度;
X1-X1、Y1-Y1~线段;
D1、D2~深度;
T1、T2~厚度;
D3、T3~差异。
具体实施方式
要了解的是本说明书以下的公开内容提供许多不同的实施例或范例,以实施本发明的不同特征部件。而本说明书以下的公开内容是叙述各个构件及其排列方式的特定范例,以求简化本发明的说明。当然,这些特定的范例并非用以限定本发明。例如,元件的尺寸并未局限于公开的范围或数值,而取决于装置的工艺条件及/或需求性质,此外,本说明书以下的公开内容叙述了将一第一特征部件形成于一第二特征部件之上或上方,即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例,亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间,而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外,为了简化与清晰的目的,各种特征部件可任意地以不同比例绘示。
再者,为了方便描述附图中一元件或特征部件与另一(复数)元件或(复数)特征部件的关系,可使用空间相关用语,例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外,空间相关用语涵盖使用或操作中的装置的不同方位。所述装置也可被另外定位(例如旋转90度或者位于其他方位),并对应地解读所使用的空间相关用语的描述。此外,用语”由…制成”可表示”包括”或”由..组成”。
图1-图20C显示依据本公开的一实施例的制造环绕式栅极场效晶体管(GAA FET)装置的例示性连续工艺。可理解的是,于图1-图20C描述的各阶段之前、之中及/或之后,可提供一些附加操作。以下描述的一些操作可依据附加的实施例方法被代替或消除,操作/工艺的顺序为可互换的。
如图1所示,杂质离子(impurity ion)(掺杂物(dopant))12注入于硅基底10中,以形成阱区部。实施此离子注入(ion implantation)以避免贯穿效应(punch-througheffect)。
在一实施例中,基底10包含单结晶半导体层至少于其表面部分上。基底10可包括单结晶半导体材料例如,但不限于,硅(Si)、锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化镓铟(InGaAs)、锑磷化镓(GaSbP)、锑砷化镓(GaAsSb)和磷化铟(InP)。在这个实施例中,基底10由硅(Si)制成。
基底10可包含一或多层的缓冲层(未绘示)在其表面区内。缓冲层可提供从基底到源极/漏极区逐渐改变的晶格常数(lattice constant)。缓冲层可由外延成长的单结晶半导体材料形成例如,但不限于,硅(Si)、锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化镓铟(InGaAs)、锑磷化镓(GaSbP)、锑砷化镓(GaAsSb)、氮化镓(GaN)、磷化镓(GaP)和磷化铟(InP)。在一特定的实施例中,基底10包括外延成长于硅基底10之上的硅锗(SiGe)缓冲层。硅锗缓冲层的锗浓度可由最底部缓冲层的30原子百分比(atomic%)的锗增加到最顶部缓冲层的70原子百分比的锗。
基底10可包含已合适地掺杂杂质(例如p型或n型导电性)的各种区域,掺杂物12为例如n型鳍型场效晶体管的硼(BF2)及p型鳍型场效晶体管的磷。
在图2中,堆叠的半导体层形成于基底10之上,堆叠的半导体层包含第一半导体层20及第二半导体层25。再者,掩模层15形成于堆叠的层之上。
第一半导体层20及第二半导体层25由具有不同晶格常数的材料制成,且可包含一或多层的硅(Si)、锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化镓铟(InGaAs)、锑磷化镓(GaSbP)、锑砷化镓(GaAsSb)或磷化铟(InP)。
在一些实施例中,第一半导体层20及第二半导体层25由硅、硅化合物、硅锗(SiGe)、锗或锗化合物制成。在一实施例中,第一半导体层20为Si1-xGex,其中x为大于约0.3或Ge(x=1),且第二半导体层25为Si或Si1-yGey,其中y为小于约0.4且x大于y。在这个公开中,”M”化合物”或”以M为主的化合物”表示化合物中大多数为M。
在其他实施例中,第二半导体层25为Si1-yGey,其中y为大于约0.3或Ge,且第一半导体层20为Si或Si1-xGex,其中x为小于约0.4且x小于y。在另一些其他实施例中,第一半导体层20由Si1-xGex制成,其中x是在从大约0.3到大约0.8的范围,且第二半导体层25由Si1- xGex制成,其中x是在从大约0.1到大约0.4的范围。
在图2中,设置五层的第一半导体层20和六层的第二半导体层25。然而,层数并不局限于五层,可小至一层(每层),且于一些实施例中,每一个第一半导体层及第二半导体层形成二到十层。通过调整堆叠的层的数量,可调整环绕式栅极场效晶体管(GAA FET)装置的驱动电流(driving current)。
第一半导体层20及第二半导体层25外延地(epitaxially)形成于基底10之上。第一半导体层20的厚度可相等或大于第二半导体层25的厚度,且在一些实施例中,第一半导体层20的厚度范围从大约5纳米至大约50纳米之间,在其他一些实施例中,第一半导体层20的厚度范围从大约10纳米至大约30纳米之间。在一些实施例中,第二半导体层25的厚度范围从大约5纳米至大约30纳米,在其他一些实施例中,第二半导体层25的厚度范围从大约10纳米至大约20纳米。第一半导体层20的每一个的厚度可相同或可不同。
在一些实施例中,第一半导体层的底部(最靠近基底10的层)比其余的第一半导体层更厚。在一些实施例中,第一半导体层的底部的厚度范围从大约10纳米至大约50纳米。在其他一些实施例中,第一半导体层的底部的厚度范围从大约20纳米至大约40纳米。
在一些实施例中,掩模层15包含第一掩模层15A及第二掩模层15B。第一掩模层15A由氧化硅制成的接垫氧化物层(pad oxide layer),且可通过热氧化(thermal oxidation)形成。第二掩模层15B由氮化硅(SiN)制成,且通过化学气相沉积(chemical vapordeposition,CVD)包含低压化学气相沉积(lowpressure CVD,LPCVD)及等离子体增强化学气相沉积(plasma enhanced CVD,PECVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)或其他适合的工艺形成。通过图案化操作包含微影(photo-lithography)和蚀刻(etching)工艺,将掩模层15图案化形成掩模图案。
接着,如图3所示,通过使用图案化掩模层,将第一半导体层20及第二半导体层25的堆叠的层图案化,使堆叠的层形成沿X方向延伸的鳍结构30。在图3中,两个鳍结构30沿Y方向排列,但鳍结构的数量并不被局限,可少至如一个或三个或更多。在一些实施例中,一或多个虚设鳍结构形成于鳍结构30的两侧,以在图案化操作中提升图案逼真度(fidelity)。
如图3所示,鳍结构30具有由堆叠的半导体层20及25和阱区部11构成的上部分。
在一些实施例中,鳍结构的上部分沿Y方向的宽度W1范围介于大约10纳米至大约40纳米。在其他一些实施例中,宽度W1范围介于大约20纳米至大约30纳米。鳍结构沿Z方向的高度H1范围介于大约100纳米至大约200纳米。
鳍结构形成之后,包含一或多层的绝缘材料的绝缘层41形成于基底之上,使得鳍结构完全地嵌入绝缘层41中。绝缘层41的绝缘材料可包含氧化硅、氮化硅、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)、氮碳化硅(SiCN)、掺氟硅玻璃(fluorinated silicateglass,FSG)或低介电常数(low-k)的介电材料,通过低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(plasma-CVD)或流动式化学气相沉积(flowable CVD)形成。形成绝缘层41之后,可实施退火(anneal)操作,接着实施平坦化操作例如化学机械研磨(chemicalmechanical polishing,CMP)工艺及/或回蚀刻(etch-back)工艺,使最上面的第二半导体层25的上表面从绝缘层41露出,如图4所示。
如图4所示,在一些实施例中,在形成绝缘层41之前,形成第一衬垫层35于图3所示的结构上。第一衬垫层35由氮化硅(SiN)或其他以氮化硅为主的材料(例如氮氧化硅(SiON)、氮碳化硅(SiCN)或氮碳氧化硅(SiOCN))制成。
接着,如图5所示,使绝缘材料层41凹入以形成隔离绝缘层40,使得鳍结构30之上部分露出。通过这个操作,鳍结构30通过隔离绝缘层40亦被称为浅沟槽绝缘(shallowtrench isolation,STI)互相电性隔离。
在图5所示的实施例,使绝缘材料层41凹入至第一半导体层20的最底部露出。在一些其他实施例中,阱区部11之上部分也部分地露出。第一半导体层20为后续被部分移除的牺牲层,而第二半导体层25后续形成了环绕式栅极场效晶体管的通道层。
如图6所示,在隔离绝缘层40形成之后,形成牺牲栅极介电层52。牺牲栅极介电层52包含一或多层的绝缘材料,例如以氧化硅为主的材料。在一实施例中,使用通过化学气相沉积(CVD)形成的氧化硅。在一些实施例中,牺牲栅极介电层52的厚度范围从大约1纳米至大约5纳米。
图7绘示在牺牲栅极结构50形成于露出的鳍结构30之上之后的结构。牺牲栅极结构包含牺牲栅极电极层54及牺牲栅极介电层52。牺牲栅极结构50形成于之后作为通道区的一部分鳍结构之上,牺牲栅极结构定义出环绕式栅极场效晶体管的通道区。
如图7所示,牺牲栅极结构50通过先毯覆沉积牺牲栅极介电层52于鳍结构之上而形成。牺牲栅极电极层接着毯覆沉积于牺牲栅极介电层上与鳍结构之上,使得鳍结构完全地嵌入牺牲栅极电极层中。牺牲栅极电极层包含硅例如多晶(polycrystalline)硅或非晶(amorphous)硅。在一些实施例中,牺牲栅极电极层的厚度范围介于大约100纳米至大约200纳米。在一些实施例中,牺牲栅极电极层受到平坦化操作。牺牲栅极介电层和牺牲栅极电极层通过化学气相沉积(CVD)包含低压化学气相沉积(LPCVD)和等离子体增加化学气相沉积(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)或其他适合的工艺沉积。接着,形成掩模层于牺牲栅极电极层之上,掩模层包含接垫氮化硅层56及氧化硅掩模层58。
接着,如图7所示,实施图案化操作于掩模层上,且图案化牺牲栅极电极层以形成牺牲栅极结构50。牺牲栅极结构包含牺牲栅极介电层52、牺牲栅极电极层54(例如多晶硅)、接垫氮化硅层56及氧化硅掩模层58。通过图案化牺牲栅极结构,如图7所示,第一半导体层及第二半导体层的堆叠的层于牺牲栅极结构的相对侧上部分地露出,藉此定义源极/漏极(S/D)区。在这个公开中,源极和漏极为可交换使用且其结构大致上相同。于图7中,形成一个牺牲栅极结构,但牺牲栅极结构的数量并不局限于一个。在一些实施例中,两个或更多牺牲栅极结构沿X方向排列。在特定一些实施例中,一或多个虚设牺牲栅极结构形成于牺牲栅极结构的两侧,以提升图案逼真度。
如图8所示,形成牺牲栅极结构之后,作为侧壁间隔元件55的绝缘材料的毯覆层53通过化学气相沉积(CVD)或其他适合的工艺顺应地形成。毯覆层53以顺应的方式沉积,使其在牺牲栅极结构的垂直表面例如侧壁、水平表面及顶部具有大致上相同厚度。在一些实施例中,毯覆层53沉积至大约2纳米至大约10纳米的厚度范围。在一实施例中,毯覆层53的绝缘材料是以氮化硅为主的材料,例如氮化硅(SiN)、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)或氮碳化硅(SiCN)及前述的组合。
再者,如图9A-图9C所示,侧壁间隔元件55形成于牺牲栅极结构的相对侧壁上,且接续使源极/漏极(S/D)区的鳍结构向下凹入至隔离绝缘层40的上表面之下。图9B是对应图9A的区域A1及线段X1-X1的剖面图,且图9C是对应图9A的线段Y1-Y1的剖面图。于图9B中,绘示一个牺牲栅极结构50及相邻的牺牲栅极结构50’的底部部分的剖面图。
形成毯覆层53之后,使用例如反应离子刻蚀(reactive ion etching,RIE)于毯覆层53上实施异向性(anisotropic)蚀刻。在异向性蚀刻过程中,从水平表面移除大部分的绝缘材料,留下介电间隔元件层于垂直表面上,例如牺牲栅极结构的侧壁及露出的鳍结构的侧壁。掩模层58可从侧壁间隔元件露出。在一些实施例中,可接续实施等向性(isotropic)蚀刻,以从露出的鳍结构30的源极/漏极(S/D)区之上部分移除绝缘材料。
接着,通过干蚀刻(dry etching)及/或湿蚀刻(wet etching)将源极/漏极(S/D)区的鳍结构30向下凹入至隔离绝缘层40的上表面之下。如图9A及图9C所示,形成于露出的鳍结构的源极/漏极(S/D)区的侧壁间隔元件55部分留下。然而,在其他一些实施例中,形成于露出的鳍结构的源极/漏极(S/D)区的侧壁间隔元件55全部被移除。在这个步骤,如图9B所示,于牺牲栅极结构之下的第一半导体层20及第二半导体层25的堆叠的层的末端部分具有与间隔元件55齐平的大致上平坦的表面。在一些实施例中,水平地轻微蚀刻第一半导体层20及第二半导体层25的堆叠的层的末端部分。
接着,如图10A-图10C所示,使第一半导体层20水平地凹入(蚀刻),使得第一半导体20的边缘大致上位于牺牲栅极电极层54的侧表面之下。如图10B所示,于牺牲栅极结构之下的第一半导体层20末端部分(边缘)大致上齐平于牺牲栅极电极层54的侧面。在这里「大致上齐平」表示相对位置之间的差异小于大约1纳米。
如图10B所示,于图9A-图9C描述的第一半导体层20的凹入蚀刻(recessetching)及/或第一半导体层及第二半导体层的凹入蚀刻的过程中,第二半导体层25的末端部分也被水平地蚀刻。第一半导体层20凹入的量大于第二半导体层25凹入的量。
在一些实施例中,从包含一个侧壁间隔元件的平面,第一半导体层20凹入的深度D1范围从大约5纳米至大约10纳米,从包含一个侧壁间隔元件的平面,第二半导体层25凹入的深度D2范围从大约1纳米至大约4纳米。在一些实施例中,深度D1与深度D2的差异D3范围从大约1纳米至大约9纳米。
在特定一些实施例中,并没有蚀刻(水平地凹入)第一及第二半导体层。在其他一些实施例中,第一半导体层及第二半导体层蚀刻的量大致上相同(差异小于大约0.5纳米)。
如图11A-图11C所示,第一半导体层20水平地凹入之后,形成衬垫外延层70于第一半导体层20及第二半导体层25凹入的表面上。衬垫外延层70也形成于源极/漏极(S/D)区的凹入的鳍结构11上。
在一些实施例中,衬垫外延层70为未掺杂的硅。在其他一些实施例中,衬垫外延层包含一或多层的硅、磷化硅(SiP)及碳磷化硅(SiCP)。在特定一些实施例中,衬垫外延层70由一或多层的硅锗(SiGe)和锗制成。在一些实施例中,在第一半导体层20凹入的表面上的衬垫外延层70的厚度范围从大约5纳米至大约10纳米。在一些实施例中,在第二半导体层25凹入的表面上的衬垫外延层70的厚度范围从大约1纳米至大约4纳米。在特定一些实施例中,在第二半导体层25凹入的表面上的衬垫外延层70的厚度为在第一半导体层20凹入的表面上的衬垫外延层70的厚度的大约20%至大约60%。衬垫外延层70选择性地长于半导体层上。
如图12所示,在形成衬垫外延层70之后,形成源极/漏极(S/D)外延层80。源极/漏极(S/D)外延层80包含一或多层的硅、磷化硅(SiP)、碳化硅(SiC)及碳磷化硅(SiCP)用于n通道场效晶体管,或者硅、硅锗(SiGe)、锗用于p通道场效晶体管。源极/漏极层80通过外延成长方法使用化学气相沉积(CVD)、原子层沉积(ALD)或分子束外延(molecular beamepitaxy,MBE)形成。
如图12所示,源极/漏极外延层从形成在两个鳍结构的底部11的各自表面上的衬垫外延层70成长。在一些实施例中,成长的源极/漏极外延层合并于隔离绝缘层40上,且形成孔洞82。
接着,如图13所示,形成第二衬垫层90且接着形成层间介电(interlayerdielectric,ILD)层95。第二衬垫层90由以氮化硅为主的材料(如氮化硅)制成,且在接下来的蚀刻操作中作为接触蚀刻停止层。
层间介电层95的材料包含的化合物包括硅、氧、碳及/或氢,例如氧化硅、氢氧碳化硅(SiCOH)及碳氧化硅(SiOC)。有机材料如聚合物可使用于层间介电层95。
形成层间介电层95之后,实施平坦化(planarization)操作例如化学机械研磨(CMP),使牺牲栅极电极层54的顶部部分露出。
接着,如图14所示,移除牺牲栅极电极层54与牺牲栅极介电层52,藉此露出鳍结构。
在移除牺牲栅极结构过程中,层间介电层95保护源极/漏极结构80。牺牲栅极结构可使用等离子体(plasma)干蚀刻及/或湿蚀刻移除。当牺牲栅极电极层54为多晶硅且层间介电层95为氧化硅时,可用湿蚀刻剂例如氢氧化四甲铵(TMAH)溶液,以选择性地移除牺牲栅极电极层54。牺牲栅极介电层52则在之后使用等离子体干工艺及/或湿工艺移除。
如图15A及图15B所示,在移除牺牲栅极结构之后,移除鳍结构中的第一半导体层20,藉此形成第二半导体层25的导线,图15B是沿鳍结构的剖面图。
使用可选择性蚀刻第一半导体层20而不蚀刻第二半导体层25的蚀刻剂移除或蚀刻第一半导体层20。
当第一半导体层20为锗或硅锗(SiGe),且第二半导体层25为硅,第一半导体层20可选择性地通过湿蚀刻剂例如但不限于氨水(ammonium hydroxide,NH4OH)、氢氧化四甲铵(tetramethylammonium hydroxide,TMAH)、乙二胺邻苯二酚(ethylenediaminepyrocatechol,EDP)或氢氧化钾(potassium hydroxide,KOH)溶液移除。
当第一半导体层20为硅,且第二半导体层25为锗或硅锗(SiGe),第一半导体层20可选择性地通过湿蚀刻剂例如但不限于氨水(ammonium hydroxide,NH4OH)、氢氧化四甲铵(tetramethylammonium hydroxide,TMAH)、乙二胺邻苯二酚(ethylenediaminepyrocatechol,EDP)或氢氧化钾(potassium hydroxide,KOH)溶液移除。
在这个公开中,由于衬垫外延层70(例如硅)已形成,第一半导体层20(例如硅锗(SiGe))的蚀刻停止在衬垫外延层70。当第一半导体层20由硅制成,衬垫外延层70可为硅锗(SiGe)或锗。由于第一半导体层20的蚀刻停止在衬垫外延层70,可避免栅极电极与源极/漏极(S/D)外延层接触或桥接(bridging)。
形成第二半导体层25的导线之后,栅极介电层102形成于每个通道层(第二半导体层25的导线)的周围,且栅极电极层104形成于栅极介电层102之上,如图16所示。
在特定一些实施例中,栅极介电层102包含一或多层的介电材料例如氧化硅、氮化硅或高介电常数(high-k)的介电材料、其他适合的介电材料及/或前述的组合,高介电常数的介电材料的范例包含二氧化铪(HfO2)、硅氧化铪(HfSiO)、碳氧硅化铪(HfSiON)、氧钽化铪(HfTaO)、氧钛化铪(HfTiO)、氧锆化铪(HfZrO)、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适合的高介电常数的介电材料及/或前述的组合。在一些实施例中,栅极介电层102包含形成于通道层与介电材料之间的界面层(interfacial layer)。
栅极介电层102可通过化学气相沉积(CVD)、原子层沉积(ALD)或其他适合的工艺形成。在一实施例中,栅极介电层102使用高顺应性(conformal)的沉积工艺例如原子层沉积(ALD)形成,以确保形成的栅极介电层于每个通道层周围具有一致的厚度。在一实施例中,栅极介电层102的厚度范围从大约1纳米至大约6纳米。
栅极电极层104形成于栅极介电层102之上,以围绕每个通道层。栅极电极层104包含一或多层的导电材料,例如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、氮化钛(TiN)、氮化钨(WN)、钛铝(TiAl)、氮化铝钛(TiAlN)、碳氮化钽(TaCN)、碳化钽(TaC)、氮硅化钽(TaSiN)、金属合金、其他适合的材料及/或前述的组合。
栅极电极层104可通过化学气相沉积(CVD)、原子层沉积(ALD)、电镀(electro-plating)或其他适合的工艺形成。栅极电极层也沉积于层间介电层95的上表面之上。接着使用例如化学机械研磨(CMP)将形成于层间介电层95之上的栅极介电层与栅极电极层平坦化,直到层间介电层95的顶部表面露出。
如图16所示,平坦化操作之后,使栅极电极层104凹入,且形成盖绝缘层106于凹入的栅极电极104之上。盖绝缘层106包含一或多层的以氮化硅为主的材料例如氮化硅。盖绝缘层106可通过于平坦化操作之后沉积绝缘材料形成。
在本公开的特定一些实施例中,一或多个功函数调整层(未绘示)插入于栅极介电层102与栅极电极层104之间。功函数调整层由导电材料制成,例如单层的氮化钛(TiN)、氮化钽(TaN)、碳化钽铝(TaAlC)、碳化钛(TiC)、碳化钽(TaC)、钴(Co)、铝(Al)、钛铝(TiAl)、铪钛(HfTi)、硅化钛(TiSi)、硅化钽(TaSi)或碳化钛铝(TiAlC),或多层的两种或更多的上述材料。在n通道场效型晶体管中,使用氮化钽(TaN)、碳化钽铝(TaAlC)、氮化钛(TiN)、碳化钛(TiC)、钴(Co)、钛铝(TiAl)、铪钛(HfTi)、硅化钛(TiSi)和硅化钽(TaSi)中的一或多个作为功函数调整层,在p通道场效型晶体管中,使用碳化钛铝(TiAlC)、铝(Al)、钛铝(TiAl)、氮化钽(TaN)、碳化钽铝(TaAlC)、氮化钛(TiN)、碳化钛(TiC)和钴(Co)中的一或多个作为功函数调整层。功函数调整层可通过原子层沉积(ALD)、物理气相沉积(PVD)、化学气相沉积(CVD)、电子束蒸镀法(e-beam evaporation)或其他适合的工艺形成。再者,功函数调整层可于使用不同的金属层的n通道场效型晶体管及p通道场效型晶体管中分开地形成。
接着,如图17所示,使用干蚀刻形成接触孔110于层间介电层95中。在一些实施例中,蚀刻源极/漏极外延层80之上部分。
如图18所示,硅化物层120形成于源极/漏极外延层80之上。硅化物层120包含一或多个的硅钨(WSi)、硅钴(CoSi)、硅镍(NiSi)、硅钛(TiSi)、硅钼(MoSi)及硅钽(TaSi)。接着,如图19所示,导电材料130形成于接触孔中。导电材料130包含一或多个的钴(Co)、镍(Ni)、钨(W)、钛(Ti)、钽(Ta)、铜(Cu)、铝(Al)、氮化钛(TiN)及氮化钽(TaN)。
图20A-图20C显示图19绘示的结构的剖面图。图20A显示沿Y方向切割栅极的剖面图,图20B显示沿X方向切割栅极的剖面图,且图20C显示沿Y方向切割源极/漏极区的剖面图。
如图20A所示,由第二半导体层25制成的导线堆叠于Z方向。可理解的是,当移除第一半导体层20时,也可蚀刻第二半导体层25,因此第二半导体层25的角落为圆的。界面层102A包裹每个导线的周围,且栅极介电层102B覆盖界面层102A。虽然在图20A中包裹一个导线周围的栅极介电层102B接触相邻导线的栅极介电层102B,但结构并不局限于图20A。在其他一些实施例中,栅极电极104也包裹被界面层102A与栅极介电层102B覆盖的每个导线周围。
如图20B所示,衬垫外延层70形成于源极/漏极外延层80与导线(第二半导体层25)之间。在一些实施例中,位于导线之间部分的衬垫外延层70的厚度T1范围从大约5纳米至大约10纳米,位于导线末端的衬垫外延层70凹入的厚度T2范围从大约1纳米至大约4纳米。在一些实施例中,厚度T1与厚度T2的差异T3范围从大约1纳米至大约9纳米。在特定一些实施例中,厚度T2是厚度T1的大约20%至大约60%,且在其他一些实施例中为大约小于40%。
可理解的是,环绕式栅极(GAA)场效晶体管经历更多CMOS工艺,以形成不同特征部件,如接触/导孔(contact/via)、内连线金属层(interconnect metal layer)、介电层、钝化层(passivation layer)等等。
前述各种实施例或范例提供超越现有技术各种优点,例如于本公开中,由于第一半导体层20的蚀刻停止在衬垫外延层70,可避免栅极电极与源极/漏极(S/D)外延层接触或桥接。此外,可调整源极/漏极(S/D)外延层与通道层之间的接近程度(proximity)。
可以理解的是,并不是所有的优点都已于此描述中讨论,不需要有特定的优点对应所有的实施例或范例,且其他一些实施例或范例可提供不同的优点。
根据本公开的一方面,在半导体装置的制造方法中,于基底之上,沿第一方向形成第一半导体层夹设于第二半导体层之间。图案化第一半导体层与第二半导体层形成鳍结构,使得鳍结构包含由第二半导体层形成的牺牲层及由第一半导体层形成的通道层。形成牺牲栅极结构于鳍结构之上,使得牺牲栅极结构覆盖鳍结构的一部分,且保持露出鳍结构的剩余部分。移除未被牺牲栅极结构覆盖的鳍结构的剩余部分。使牺牲层水平地凹入,使得牺牲层的边缘位于牺牲栅极结构的侧面之下。形成衬垫外延层,至少位于牺牲层的凹入的表面上。形成源极/漏极区。移除牺牲栅极结构。在移除牺牲栅极结构后,移除在鳍结构中的牺牲层,使得通道层露出。形成栅极介电层及栅极电极层,于露出的通道层周围。
根据本公开的另一方面,在半导体装置的制造方法中,于基底之上,沿第一方向形成第一半导体层夹设于第二半导体层之间。图案化第一半导体层与第二半导体层形成鳍结构,使得鳍结构包含由第二半导体层形成的牺牲层及由第一半导体层形成的通道层,形成牺牲栅极结构于鳍结构之上,使得牺牲栅极结构覆盖鳍结构的一部分,且保持露出鳍结构的剩余部分。移除未被牺牲栅极结构覆盖的鳍结构的剩余部分。形成衬垫外延层,至少位于牺牲层的凹入的表面上。形成源极/漏极区。移除牺牲栅极结构。在移除牺牲栅极结构后,移除在鳍结构中的牺牲层,使得通道层露出。形成栅极介电层及栅极电极层,于露出的通道层周围。
根据本公开的另一方面,半导体装置包含第一通道层设置于基底之上,第一源极/漏极区设置于基底之上,栅极介电层设置于每一个第一通道层之上,且包裹每一个第一通道层,栅极电极层设置于栅极介电层之上,且包裹每一个第一通道层,以及衬垫半导体层设置于第一通道层与第一源极/漏极区之间。
以上概略说明了本公开数个实施例的特征部件,使本领域普通技术人员对于本公开的概念可更为容易理解。本领域普通技术人员应了解到本说明书可作为其他结构或工艺的变更或设计基础,以实现相同于本公开实施例的目的及/或获得相同的优点。本领域普通技术人员也可理解与上述等同的结构或工艺并未脱离本公开的精神及保护范围内,且可在不脱离本公开的精神及范围内,当可作更动、替代与润饰。

Claims (10)

1.一种半导体装置的制造方法,包括:
于一基底之上,沿一第一方向形成一第一半导体层夹设于多个第二半导体层之间;
图案化该第一半导体层与所述多个第二半导体层形成一鳍结构,使得该鳍结构包含由所述多个第二半导体层形成的多个牺牲层及由该第一半导体层形成的一通道层;
形成一牺牲栅极结构于该鳍结构之上,使得该牺牲栅极结构覆盖该鳍结构的一部分,且保持露出该鳍结构的多个剩余部分;
移除未被该牺牲栅极结构覆盖的该鳍结构的所述多个剩余部分;
使所述多个牺牲层水平地凹入,使得所述多个牺牲层的多个边缘位于该牺牲栅极结构的一侧面之下;
形成一衬垫外延层,至少位于所述多个牺牲层的该凹入的表面上;
形成一源极/漏极区;
移除该牺牲栅极结构;
在移除该牺牲栅极结构后,移除在该鳍结构中的该牺牲层,使得该通道层露出;以及
形成一栅极介电层及一栅极电极层,于露出的该通道层周围。
2.如权利要求1所述的半导体装置的制造方法,其中通过湿蚀刻分别移除在该鳍结构中的该牺牲层及在该源极/漏极区中的该第一半导体层。
3.如权利要求1所述的半导体装置的制造方法,其中:
多个该第一半导体层及所述多个第二半导体层交互地形成于该基底之上;以及
在该鳍结构中,所述多个牺牲层及多个该通道层交互地堆叠。
4.如权利要求1所述的半导体装置的制造方法,其中该通道层由硅或以硅为主的化合物制成,且其中该第二半导体层由硅锗(SiGe)制成。
5.如权利要求1所述的半导体装置的制造方法,其中:
在通过图案化该第一半导体层及该第二半导体层形成该鳍结构的该步骤中,形成多个鳍结构沿平行于该基底的一表面的一水平方向排列;以及
在形成该牺牲栅极结构的该步骤中,该牺牲栅极结构覆盖多个该鳍结构的每一个的一部分。
6.如权利要求1所述的半导体装置的制造方法,其中于使所述多个牺牲层凹入的该步骤中,也使该通道层水平地凹入。
7.如权利要求6所述的半导体装置的制造方法,其中该牺牲层的一凹入的量大于该通道层的一凹入的量。
8.如权利要求6所述的半导体装置的制造方法,其中该衬垫外延层也形成于该通道层的该凹入的表面上。
9.一种半导体装置的制造方法,包括:
于一基底之上,沿一第一方向形成一第一半导体层夹设于多个第二半导体层之间;
图案化该第一半导体层与所述多个第二半导体层形成一鳍结构,使得该鳍结构包含由所述多个第二半导体层形成的多个牺牲层及由该第一半导体层形成的一通道层;
形成一牺牲栅极结构于该鳍结构之上,使得该牺牲栅极结构覆盖该鳍结构的一部分,且保持露出该鳍结构的多个剩余部分;
移除未被该牺牲栅极结构覆盖的该鳍结构的所述多个剩余部分;
形成一衬垫外延层,至少位于所述多个牺牲层的一凹入的表面上;
形成一源极/漏极区;
移除该牺牲栅极结构;
在移除该牺牲栅极结构后,移除在该鳍结构中的该牺牲层,使得该通道层露出;以及
形成一栅极介电层及一栅极电极层,于露出的该通道层周围。
10.一种半导体装置,包括:
多个第一通道层,设置于一基底之上;
一第一源极/漏极区,设置于该基底之上;
一栅极介电层,设置于每一个所述第一通道层之上,且包裹每一个所述第一通道层;
一栅极电极层,设置于该栅极介电层之上,且包裹每一个所述第一通道层;以及
一衬垫半导体层,设置于所述多个第一通道层与该第一源极/漏极区之间。
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