TW202008437A - 製造半導體裝置的方法與半導體裝置 - Google Patents

製造半導體裝置的方法與半導體裝置 Download PDF

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TW202008437A
TW202008437A TW108126053A TW108126053A TW202008437A TW 202008437 A TW202008437 A TW 202008437A TW 108126053 A TW108126053 A TW 108126053A TW 108126053 A TW108126053 A TW 108126053A TW 202008437 A TW202008437 A TW 202008437A
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layer
semiconductor
fin structure
silicon
germanium
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TW108126053A
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TWI748210B (zh
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鄭兆欽
陳奕升
江宏禮
陳自強
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台灣積體電路製造股份有限公司
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Abstract

一種製造半導體裝置的方法包含：形成鰭片結構，其中包含鍺的多個第一半導體層與多個第二半導體層交替地層疊於該鰭片結構的底部上；增加第一半導體層中的鍺濃度；於鰭片結構上形成犧牲閘極結構；於鰭片結構的源極/汲極區上形成源極/汲極磊晶層；移除犧牲閘極結構；移除於通道區中的第二半導體層，從而釋放鍺濃度增加的第一半導體層；以及在第一半導體層周圍形成閘極結構，其中鍺濃度增加。

Description

製造半導體裝置的方法與半導體裝置
隨著半導體工業已經發展至奈米技術製程節點以追求更高元件密度、更高效能及更低成本，發展三維設計無論是在製造及設計方面皆面臨挑戰，其中三維設計諸如多閘極場效電晶體(field effect transistor，FET)(包含鰭式場效電晶體(FinFET)及全繞閘極場效電晶體(gate-all-around(GAA)FET)等。在鰭式場效電晶體中，閘極電極相鄰於通道區之三個側表面，其中閘極介電層插入於閘電極與此三個側表面之間。由於閘極結構在三個表面上環繞(纏繞)鰭片，因此電晶體基本上具有控制藉由鰭片或通道區之電流之三個閘極。令人遺憾地，通道之第四側、底部部分遠離閘極電極且因此不受閘極嚴密地控制。相反地，在全繞閘極場效電晶體中，通道區之所有側表面皆被閘極電極環繞，此允許通道區中具有較完整的空乏，且由於陡峭的次臨界電流擾動(steeper sub-threshold current swing)以及較低的汲極引致能障下降(drain induced barrier lowering(DIBL)，可降低的短通道效應。由於電晶體尺寸 持續按比例縮減至10至15奈米的技術節點，因此需要進一步改良全繞閘極場效電晶體。
10‧‧‧基板
11、11A、11B‧‧‧鰭片結構之底部
12‧‧‧摻雜物
15、15A、15B‧‧‧遮罩層
20‧‧‧第一半導體層
22‧‧‧縮合後的第一半導體層
25‧‧‧第二半導體層
25A‧‧‧半導體鰭片
30、30A、30B、108A、108B‧‧‧鰭片結構
35、35A、35B‧‧‧鰭式襯層
40‧‧‧隔離絕緣層
41‧‧‧絕緣材料層
42、57、59、87、89‧‧‧保護層
44‧‧‧氧化膜
50‧‧‧犧牲閘極結構
52‧‧‧犧牲閘極介電層
53‧‧‧毯覆層
54‧‧‧犧牲閘極電極
55‧‧‧閘極側壁間隔物
56‧‧‧遮罩層
62、64‧‧‧介電內間隔物
80A、80B‧‧‧源極/汲極(S/D)磊晶層
85‧‧‧襯層
90‧‧‧層間介電質層
102‧‧‧介面層
104‧‧‧閘極介電層
106‧‧‧功函數調變層
108‧‧‧閘極電極層
108A、108B‧‧‧閘極結構
H1‧‧‧高度
H11、H21‧‧‧厚度
S11、S21‧‧‧間隔
W11、W21‧‧‧寬度
X、Y、Z‧‧‧方向
X1-X1、X2-X2、Y1-Y1、Y2-Y2‧‧‧線
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界的標準實務，各特徵並未依比例繪示。事實上，為了使討論更為清楚，各特徵的尺寸都可任意地增加或減少。
[圖1]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的視圖。
[圖2]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的視圖。
[圖3]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的視圖。
[圖4]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的視圖。
[圖5]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的視圖。
[圖6A]至[圖6D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖7A]至[圖7D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖8A]至[圖8D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖9A]至[圖9D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖10A]至[圖10D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖11A]至[圖11D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖12A]至[圖12D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖13A]至[圖13D]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖14A]至[圖14E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖15A]至[圖15E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖16A]至[圖16E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖17A]至[圖17E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖18A]至[圖18E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖19A]至[圖19E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖20A]至[圖20E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖21A]至[圖21E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖22A]至[圖22E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖23A]至[圖23E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖24A]至[圖24E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖25A]至[圖25E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖26A]至[圖26E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖27A]至[圖27E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖28A]至[圖28E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖29A]至[圖29E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖30A]至[圖30E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖31A]至[圖31E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖32A]至[圖32E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖33A]至[圖33C]係繪示根據本揭露的一些實施例之全繞閘極場效電晶體的各種視圖。
[圖34A]至[圖34E]係繪示根據本揭露的一些實施例之全繞閘極場效電晶體的各種視圖。
[圖35A]至[圖35E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖36A]至[圖36E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
[圖37A]至[圖37E]係繪示根據本揭露的實施例之用於全繞閘極場效電晶體的順序製造製程的各個階段之一的各種視圖。
應理解，以下揭示內容提供用於實施本揭露之不同特徵之諸多不同實施例或實例。下文描述組件及排列之特定實施例或實例以簡化本揭露。當然，此等僅係示例性且並非意欲為限制性。舉例而言，部件之尺寸不限於所揭示範圍或值，而是可取決於元件之製程條件及/或所期望性質。此外，隨後之描述中在第二特徵上方或在第二特徵上形 成第一特徵可包含其中第一特徵及第二特徵直接接觸形成之實施例且亦可包含其中可插入第一特徵及第二特徵地形成額外特徵以使得第一特徵及第二特徵可不直接接觸之實施例。為簡單且清晰起見，各特徵可按不同比例而任意繪製。
進一步而言，為了便於描述，本文可使用諸如「下面」、「下方」、「下部」、「上方」、「上部」及類似者等空間相對性術語來描述如圖中所圖示之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了圖中所描繪之定向外，空間相對性術語意欲囊括使用或操作中之元件之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。另外，術語「由…製成」可意指「包括」或「由…組成」。在本揭露中，用語「A、B與C之一」表示「A、B和/或C」(即：A，B，C，A與B，A與C，B與C，或，A與B與C)，除非另有說明，否則並不表示來自A的一個元件、來自B的一個元件以及來自C的一個元件。
在以下的實施例中，除非另有說明，否則可在另一實施例中採用一個實施例的材料、設置、尺寸、操作和/或過程，並可以省略其詳細說明。
已研究高遷移率之通道材料與裝置架構來延長摩爾定律近十年的壽命。具有高鍺濃度的純鍺與矽鍺(SiGe)由於具有更高的本質電洞與電子遷移率的材料特性而成為這種材料的有希望的候選者。對於閘極長度(gate length，Lg)小於12奈米之回火良好的裝置，將採用奈米線 或奈米片結構來提供更佳的短通道控制。因此，鍺或矽鍺奈米線裝置被認為是進一步縮小邏輯元件應用的有希望與潛在的候選者。
為了製造具有矽基通道、矽鍺基通道或鍺基通道(半導體線)的全繞閘極場效電晶體，矽、矽鍺或鍺的堆疊層形成於基板上，將堆疊層圖案化成鰭片結構，且在閘極更替過程中移除其中一層以釋放所述通道。一般而言，矽乃是用於N型通道全繞閘極場效電晶體，矽鍺或鍺乃是用於P型通道全繞閘極場效電晶體。在矽鍺P型通道全繞閘極場效電晶體的情況下，更高的鍺濃度可提高電晶體性能。
然而，當形成矽與矽鍺的堆疊層來製造N型通道全繞閘極場效電晶體與P型通道全繞閘極場效電晶體時，具有較高鍺濃度的矽鍺層可能引起一些問題。舉例來說，當矽鍺層中的鍺濃度為大約50原子比(atomic%)時，矽與矽鍺之間的晶格不匹配變大，且在矽鍺層上磊晶形成的矽層的臨界厚度變小，這可能會降低具有矽通道的N型通道全繞閘極場效電晶體的性能。相對而言，當矽鍺層中的鍺濃度僅為大約30-40atomic%時，具有矽鍺通道的P型通道全繞閘極場效電晶體的性能可能不足。儘管可為N型通道全繞閘極場效電晶體與P型通道全繞閘極場效電晶體形成不同的堆疊層，但製程成本會增加。
在本揭露中，提出一種裝置結構與其製造方法，以解決上述之問題。
圖1至圖32E係示出根據本揭露的實施例之用 於製造全繞閘極場效電晶體的製程順序。應理解，額外之操作可在圖1至圖32E的製程之前、期間以及之後實施，且對於所述方法的額外實施例，可取代或省略下文所描述的操作的一些部分。操作/製程的順序係可互換的。
如圖1所示，將雜質離子(摻雜物)12植入至矽基板10中以形成井區(well region)。執行離子植入是為了避免穿隧效應(punch-through effect)。在一些實施例中，基板10包含至少在其表面部分上之單晶半導體層。基板10可包含單晶半導體材料，例如但不限於：矽(Si)、鍺(Ge)、矽鍺(SiGe)、砷化鎵(GaAs)、銻化銦(InSb)、磷化鎵(GaP)、銻化鎵(GaSb)、砷化銦鋁(InAlAs)、砷化銦鎵(InGaAs)、銻磷化鎵(GaSbP)、砷銻化鎵(GaAsSb)以及磷化銦(InP)。在一實施例中，基板10係由結晶矽所製成。
基板10可包含在其表面區域中之一個或多個緩衝層(圖未示)。緩衝層可用於逐漸地將晶格常數從基板的晶格常數改變為源極/汲極區的晶格常數。緩衝層可由磊晶生長的單晶半導體材料來形成，所述單晶半導體材料例如但不限於：矽(Si)、鍺(Ge)、鍺錫(GeSn)、矽鍺(SiGe)、砷化鎵(GaAs)、銻化銦(InSb)、磷化鎵(GaP)、銻化鎵(GaSb)、砷化銦鋁(InAlAs)、砷化銦鎵(InGaAs)、銻磷化鎵(GaSbP)、砷銻化鎵(GaAsSb)、氮化鎵(GaN)及磷化銦(InP)。在特定實施例中，基板10包含磊晶生長於矽基板10上的多個矽鍺緩衝層。所述矽鍺緩衝層的鍺濃度可從最底部緩衝層之30atomic%的鍺原子濃度增加至最頂部緩衝層之 70atomic%的鍺原子濃度。基板10可包含已適當摻雜雜質(例如使其帶P型或N型電性)的各種區域。舉例來說，摻雜物12係用於N型鰭式場效電晶體的硼(二氟化硼(BF2))與用於P型鰭式場效電晶體的磷。
如圖2所示，於基板10上形成堆疊的半導體層。堆疊的半導體層包括第一半導體層20與第二半導體層25。此外，於堆疊層上形成遮罩層15。第一半導體層20與第二半導體層25係由彼此具有不同晶格常數之材料所製成，且可包括一個或多個層，所述一個或多個層可由以下材料製成：矽(Si)、鍺(Ge)、矽鍺(SiGe)、鍺錫(GeSn)、矽鍺錫(SiGeSn)、砷化鎵(GaAs)、銻化銦(InSb)、磷化鎵(GaP)、銻化鎵(GaSb)、砷化銦鋁(InAlAs)、砷化銦鎵(InGaAs)、磷化鎵銻(GaSbP)、砷銻化鎵(GaAsSb)或磷化銦(InP)。
在一些實施例中，第一半導體層20與第二半導體層25係由矽、矽化合物、矽鍺、鍺或鍺化合物所製成。在特定實施例中，第一半導體層20為矽鍺合金(Si1-xGex)，其中0.35≦x≦0.45，而第二半導體層25為矽(Si)。於其他實施例中，第二半導體層25係由矽鍺合金(Si1-yGey)製成，其中y等於或小於約0.2且x>y。
在圖2中，設置五層的第一半導體層20與五層的第二半導體層25。然而，層的數量將不限制於五層，亦可少至一層(第一半導體層20與第二半導體層25)，且在一些實施例中，形成兩層至二十層的第一半導體層20與第二 半導體層25。藉由調整堆疊層的數量，可調整全繞閘極場效電晶體裝置的驅動電流。
於基板10上磊晶形成第一半導體層20與第二半導體層25。第一半導體層20的厚度可等於或小於第二半導體層25的厚度，且在一些實施例中，第一半導體層20之厚度範圍約2奈米(nm)至約10nm，且在其他實施例中，第一半導體層20之厚度範圍約3nm至約5nm。在一些實施例中，第二半導體層25之厚度範圍約5nm至約20nm，且在其他實施例中，第二半導體層25之厚度範圍約7.5nm至約12.5nm。第一半導體層20與第二半導體層25之每一者的厚度可為相同，或不相同。
在一些實施例中，於底部之第一半導體層(最靠近基板10的半導體層)係厚於其餘第一半導體層。在一些實施例中，於底部之第一半導體層之厚度範圍約10nm至約50nm。在其他實施例中，於底部之第一半導體層之厚度範圍約20nm至約40nm。
在一些實施例中，遮罩層15包括第一遮罩層15A與第二遮罩層15B。第一遮罩層15A為由二氧化矽製成的襯墊氧化層，其可藉由熱氧化形成。第二遮罩層15B由氮化矽(SiN)製成，其可藉由化學氣相沉積(chemical vapor deposition，CVD)形成，化學氣相沉積包含低壓化學氣相沉積(low pressure CVD，LPCVD)、電漿輔助化學氣相沉積(plasma enhanced CVD，PECVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)或其他適合之製程。藉由使用包含光微影及蝕刻的圖案化操作來將遮罩層15圖案化為遮罩圖案。
接著，如圖3所示，藉由使用圖案化之遮罩層來圖案化第一半導體層20與第二半導體層25的堆疊層，藉此，堆疊層形成為沿著Y方向延伸並沿著X方向設置的鰭片結構30。
可以藉由任意適合的方法來圖案化鰭片結構30。舉例來說，可使用一個或多個光微影製程，包含雙重圖案化或多重圖案化製程，來圖案化鰭片結構30。一般而言，雙重圖案化或多重圖案化製程結合了光微影製程與自我對齊製程，允許創造具有例如比使用單個、直接的光微影製程而可獲得的間距更小的間距的圖案。舉例來說，在一實施例中，於基板上形成犧牲層且使用光微影製程來圖案化犧牲層。使用自我對齊製程來於圖案化的犧牲層旁邊形成間隔物。接著，移除犧牲層，且可接著使用剩餘的間隔物或心軸(mandrels)來圖案化鰭片結構。
在圖3中，兩個鰭片結構排列在X方向。但鰭片結構30的數量不限定於此，鰭片結構30的數量可少至一個，以及三個或更多個。在一些實施例中，於鰭片結構30的兩側形成一個或多個虛設(dummy)鰭片結構，以在圖案化操作中改善圖案保真度(pattern fidelity)。如圖3所示，鰭片結構30具有由堆疊的半導體層20與25所構成的上部以及井部(well portion)11，其相應於鰭片結構之底部。
在一些實施例中，沿著X方向之鰭片結構30之上部的寬度W1之範圍約5nm至30nm。在其他實施例中，寬度W1之範圍約7.5nm至15nm。鰭片結構30之沿著Z方向的高度H1之範圍約50nm至200nm。
如圖4所示，在鰭片結構30形成之後，於基板上形成包含一層或多層的絕緣材料層41，使得鰭片結構完全嵌入至絕緣材料層41中。用於絕緣材料層41的絕緣材料可為二氧化矽、氮化矽、氮氧化矽(SiON)、碳氮氧化矽(SiOCN)、碳氮化矽(SiCN)、摻氟矽酸鹽玻璃(fluorine-doped silicate glass，FSG)，或藉由低壓化學氣相沉積(LPCVE)、電漿輔助化學氣相沉積(PECVD)，或可流動化學氣相沉積所形成之低介電常數材料。在絕緣材料層41形成之後，可執行退火操作。然後，可執行平坦化操作，例如化學機械研磨(chemical mechanical polishing，CMP)方法和/或回蝕方法，使得最上層之第二半導體層25之頂面暴露於絕緣材料層41之外，如圖4所示。
在一些實施例中，在形成絕緣材料層41之前，在圖3的結構上形成一個或多個鰭式襯層35，如圖4所示。鰭式襯層35係由氮化矽(SiN)或氮化矽基材料(例如氮氧化矽(SiON)、碳氮化矽(SiCN)或氮碳氧化矽(SiOCN))所製成。在一些實施例中，鰭式襯層35包含形成於基板10上且形成在鰭片結構之底部11的側面的第一鰭式襯層35A以及形成於第一鰭式襯層35A上的第二鰭式襯層35B。在一些實施例中每個襯層具有範圍約1nm至20nm之厚度。在一些實 施例中，第一鰭式襯層35A包含二氧化矽且具有範圍約0.5nm至5nm之厚度，第二鰭式襯層35B包含氮化矽且具有範圍約0.5nm至5nm之厚度。可透過使用例如物理氣相沉積(PVD)、化學氣相沉積(CVD)或原子層沉積(ALD)的一個或多個製程來沉積鰭式襯層35，但也可使用任何可接受的製程。
接著，如第5圖所示，凹陷絕緣材料層41以形成隔離絕緣層40，使得鰭片結構30的上部曝露。藉由此操作，鰭片結構30藉由隔離絕緣層40彼此電性隔離，亦可稱為淺溝槽絕緣(shallow trench isolation，STI)。在圖5所示的實施例中，凹陷絕緣材料層41直到最底層的第一半導體層20暴露。在其他實施例中，井層11的上部也部分地暴露。第一半導體層20為隨後被部分地移除的犧牲層，第二半導體層25隨後形成為全繞閘極場效電晶體之通道層。
在如下所解釋的圖6A至圖13D中，圖號中有“A”者(例如圖6A、圖7A、...、圖13A)為透視圖，圖號中有“B”者(例如圖6B、圖7B、...、圖13B)為沿著X方向而對應於圖6A的線X1-X1的剖視圖，圖號中有“C”者(例如圖6C、圖7C、...、圖13C)為沿著Y方向而對應於圖6A的線Y1-Y1(切割鰭片結構30A)的剖視圖，圖號中有“D”者(例如圖6D、圖7D、...、圖13D)為沿著Y方向而對應於圖6A的線Y2-Y2(切割鰭片結構30B)的剖視圖。
圖6A至圖6D示出了在鰭片結構30的上部暴露之後的結構。圖6A與圖5實質上相同。如圖6A至圖6D所 示，在鰭片結構之底部11A與11B上分別沉積第一鰭片結構30A與第二鰭片結構30B。在一些實施例中，第一鰭片結構30A係用於N型通道場效電晶體，且第二鰭片結構30B係用於P型通道場效電晶體。在其他實施例中，第一鰭片結構30A與第二鰭片結構30B係用於相同型態的場效電晶體。
接著，如圖7A至圖7D所示，在圖6A至圖6D所示的結構上形成第一保護層42。在一些實施例中，第一保護層42包含氮化矽基材料，例如氮化矽、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)與其組合，其透過包含低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程所形成。在特定實施例中，第一保護層42係由氮化矽製成。
接著，如圖8A至圖8D所示，透過使用一個或多個微影與蝕刻操作來圖案化第一保護層42，以暴露第二鰭片結構30B及其周圍區域。
接著，如圖9A至圖9D所示，在圖7A至圖7D所示的結構上形成氧化膜44。在一些實施例中，氧化膜44包含透過包含低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程所形成的二氧化矽。
隨後，如圖10A至圖10D所示，執行熱製程來氧化第一半導體層20。在一些實施例中，熱製程在包括氧 氣(O2)和/或臭氧(O3)的氧化環境中執行。在特定實施例中，熱製程在溫度為攝氏800度(℃)至1000℃的範圍中執行。在用於氧化以矽鍺製成的第一半導體層20的熱製程期間，矽鍺中的矽原子被更多地捕獲在氧化物層中，而在第一半導體層20的非氧化部分內縮合(condense)矽鍺中的鍺原子(矽鍺縮合製程)。更具體地來說，在矽鍺縮合製程期間，表面矽原子的優先氧化產生富含二氧化矽的氧化物層。同時，表面鍺原子不僅被推入矽鍺層內，而且由於熱預算高，表面鍺原子向外擴散進入上矽層與下矽層。矽鍺縮合與向外擴散之結合製程導致在矽鍺塊層與以鍺擴散的矽層內的鍺濃度的重新分佈。在縮合後所得到的鍺分佈曲線決定了矽鍺線形狀，如下所述(例如狗骨形狀)。
因此，在矽鍺縮合製程之前，第一半導體層的非氧化部分22具有比第一半導體層20更高的鍺濃度。在一些實施例中，在矽鍺縮合製程之後，縮合後的第一半導體層22的鍺濃度的範圍約為45atomic%至55atomic%(Si1-zGez，其中0.45≦z≦0.55)。再者，在縮合製程期間，第一半導體層20的厚度增加。在縮合製程期間，以矽製成的第二半導體層25也被輕微地氧化。第一半導體層20的氧化量大於第二半導體層25的氧化量。
在其他實施例中，在不形成氧化膜44的情況下執行縮合製程。
在縮合製程之後，透過適合的蝕刻操作，例如濕式蝕刻，來移除氧化膜44與第二鰭片結構30B的氧化部 分，如圖11A至圖11D所示。在一些實施例中，將縮合製程重複兩次或更多次，以在縮合後的第一半導體層22中獲取所需的鍺濃度。
在一些實施例中，在縮合製程之後，縮合後的第一半導體層22的寬度小於縮合後的第一半導體層22的厚度。在其他實施例中，縮合後的第一半導體層22的寬度大於縮合後的第一半導體層22的厚度。
隨後，使用一個或多個蝕刻操作來移除第一保護層42，如圖12A至圖12D所示。
在第一保護層42移除之後，形成犧牲閘極介電層52，如圖13A至圖13D所示。犧牲閘極介電層52包含一層或多層絕緣材料，其中絕緣材料例如二氧化矽基材料。在一個實施例中，透過使用化學氣相沉積(CVD)來形成二氧化矽。在一些實施例中，犧牲閘極介電層52的厚度的範圍約1nm至5nm。
在如下所解釋的圖14A至圖32E中，圖號中有“A”者(例如圖14A、圖15A、...、圖32A)為透視圖，圖號中有“B”者(例如圖14B、圖15B、...、圖32B)為沿著X方向而對應於圖14A的線X1-X1(切割閘極區)的剖視圖，圖號中有“C”者(例如圖14C、圖15C、...、圖32C)為沿著X方向而對應於圖14A的線X2-X2(切割源極/汲極區)的剖視圖，圖號中有“D”者(例如圖14D、圖15D、...、圖32D)為沿著Y方向而對應於圖14A的線Y1-Y1(切割鰭片結構30A)的剖視圖，圖號中有“E”者(例如圖14E、圖15E、...、 圖32E)為沿著Y方向而對應於圖14A的線Y2-Y2(切割鰭片結構30B)的剖視圖。
圖14A至圖14E示出了在暴露的鰭片結構30A與30B上形成犧牲閘極結構50之後的結構。犧牲閘極結構50包含犧牲閘極電極54與犧牲閘極介電層52。在將成為通道區的閘極結構的一部分上形成犧牲閘極結構50。犧牲閘極結構50定義了全繞閘極場效電晶體的通道區。
犧牲閘極結構50之形成乃是藉由先在鰭片結構30A與30B上毯覆沉積(blanket depositing)犧牲閘極介電層52，接著在犧牲閘極介電層上與鰭片結構30上覆蓋沉積犧牲閘極電極層，使得鰭片結構30完全地嵌入於犧牲閘極電極層中。犧牲閘極電極層包含矽，例如多晶矽或非晶矽。在一些實施例中，犧牲閘極電極層的厚度的範圍約為100nm至200nm。在一些實施例中，犧牲閘極電極層經受平坦化操作。使用包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程來沉積犧牲閘極介電層與犧牲閘極電極層。隨後，在犧牲閘極電極層上形成遮罩層56。遮罩層56包含一層或多層的氮化矽層與二氧化矽層。
接著，在遮罩層與犧牲閘極電極層上執行圖案化操作以將其圖案化成為犧牲閘極結構50，如圖14A至圖14E所示。犧牲閘極結構包含犧牲閘極介電層52、犧牲閘極電極層54(例如多晶)與遮罩層56。藉由圖案化犧牲閘極結 構，第一半導體層與第二半導體層的堆疊層部分地暴露在犧牲閘極結構的相對兩側上，從而定義源極/汲極(source/drain，S/D)區，如圖14A至圖14E所示。在本揭露中，源極與汲極可互換使用，且其結構基本上相同。在圖14A至圖14E中，形成一個犧牲閘極結構50，但犧牲閘極結構的數量不限於一個。在一些實施例中，兩個或更多個犧牲閘極結構沿著Y方向排列。在特定實施例中，在犧牲閘極結構的兩側上形成一個或多個虛設(dummy)犧牲閘極結構以改善圖案保真度(pattern fidelity)。
在犧牲閘極結構50形成之後，藉由使用化學氣相沉積(CVD)或其他適合的方法來共形地形成用於閘極側壁間隔物55的絕緣材料的毯覆層53，如圖15A至圖15E所示。以共形方法來沉積毯覆層53，使得其形成為在垂直表面上具有基本上相同的厚度，所述垂直表面例如為側壁、水平表面與犧牲閘極結構的頂部。在一些實施例中，毯覆層53沉積為約2nm至10nm的厚度。在一些實施例中，毯覆層53的絕緣材料為氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合。在特定實施例中，絕緣材料為氮氧化矽(SiON)、氮碳氧化矽(SiOCN)與碳氮化矽(SiCN)之一。
再者，如圖16A至圖16E所示，透過非等向性蝕刻來於犧牲閘極結構的相對側壁上形成閘極側壁間隔物55。在毯覆層53形成之後，使用例如反應離子蝕刻(reactive ion etching，RIE)來於毯覆層53上執行非等向 性蝕刻。在非等向性蝕刻製程期間，從水平表面移除大部分的絕緣材料，將介電間隔層留在垂直表面上，所述垂直表面例如為犧牲閘極結構的側壁與暴露的鰭片結構的側壁。遮罩層56可從側壁間隔物暴露。在一些實施例中，可於隨後執行等向性蝕刻製程以從暴露的鰭片結構30的源極/汲極(S/D)區的上部移除絕緣材料。
隨後，形成第二保護層57以覆蓋相應於第二鰭片結構30B(對於P型通道區而言)的區域，如圖17A至圖17E所示。
在一些實施例中，第二保護層57包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合，且其透過包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程而形成。在特定實施例中，第二保護層57係以氮化矽製成。在毯覆層形成之後，透過使用一個或多個微影與蝕刻操作來形成第二保護層57。
接著，移除第一鰭片結構30A的源極/汲極(S/D)區的第一半導體層20。再者，水平地凹陷(蝕刻)第一半導體層20，因此第一半導體層20的邊緣基本上位於閘極側壁間隔物55下方。在一些實施例中，第一半導體層20的端部(邊緣)具有例如V形或U形的凹形。第一半導體層20從包括一個閘極側壁間隔物55的平面而凹陷的深度的範圍約 為5nm至10nm。第一半導體層20的蝕刻包含濕蝕刻和/或乾蝕刻。可使用例如氫氧化銨(ammonium hydroxide，NH4OH)溶液的濕蝕刻劑來選擇性地蝕刻第一半導體層20。
接著，形成介電材料層，且執行一個或多個蝕刻操作以在凹陷的第一半導體層20的端面上形成介電內間隔物62，如圖18A至圖18E所示。在一些實施例中，介電內間隔物62包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合且不同於閘極側壁間隔物55的材料。在特定實施例中，介電內間隔物62係以氮化矽製成。可使用包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程來形成介電材料層。在特定實施例中，蝕刻為等向性蝕刻。在一些實施例中，介電內間隔物62之沿著Y方向的最大厚度的範圍為約0.5nm至5nm。
接著，如圖19A至圖19E所示，第一源極/汲極(S/D)磊晶層80A形成環繞在源極/汲極(S/D)區的第二半導體層25周圍。第一源極/汲極(S/D)磊晶層80A包含用於N型通道場效電晶體的單層或多層的矽、磷化矽(SiP)、碳化矽(SiC)與碳磷化矽(SiCP)。藉由磊晶生長方法，使用化學氣相沉積(CVD)、原子層沉積(ALD)或分子束磊晶(molecular beam epitaxy，MBE)來形成第一源極/汲極(S/D)磊晶層80A。在第一源極/汲極(S/D)磊晶層80A形成之後，移除第二保護層57。
隨後，形成第三保護層59以覆蓋相應於第一鰭片結構30A(對於N型通道區而言)的區域，如圖20A至圖20E所示。在一些實施例中，第三保護層59包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合，且其透過包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程而形成。在特定實施例中，第三保護層59係以氮化矽製成。在毯覆層形成之後，透過使用一個或多個微影與蝕刻操作來形成第三保護層59。
接著，移除第二鰭片結構30B的源極/汲極(S/D)區的第二半導體層25。再者，水平地凹陷(蝕刻)第二半導體層25，因此第二半導體層25的邊緣基本上位於閘極側壁間隔物55下方。在一些實施例中，第二半導體層25的端部(邊緣)具有例如V形或U形的凹形。第二半導體層25從包括一個閘極側壁間隔物55的平面而凹陷的深度的範圍約為5nm至10nm。第二半導體層25的蝕刻包含濕蝕刻和/或乾蝕刻。可使用例如四甲基氫氧化銨(tetramethylammonium hydroxide，TMAH)溶液的濕蝕刻劑來選擇性地蝕刻第二半導體層25。
接著，形成介電材料層，且執行一個或多個蝕刻操作以在凹陷的第二半導體層25的端面上形成介電內間隔物64，如圖21A至圖21E所示。在一些實施例中，介電內 間隔物64包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合且不同於閘極側壁間隔物55的材料。在特定實施例中，介電內間隔物64係以氮化矽製成。可使用包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程來形成介電材料層。在特定實施例中，蝕刻為等向性蝕刻。在一些實施例中，介電內間隔物64之沿著Y方向的最大厚度的範圍為約0.5nm至5nm。
接著，如圖22A至圖22E所示，第二源極/汲極(S/D)磊晶層80B形成環繞在源極/汲極(S/D)區的縮合的第一半導體層22周圍。第二源極/汲極(S/D)磊晶層80B包含用於P型通道場效電晶體的單層或多層的矽、矽鍺(SiGe)與磷矽鍺(SiGeP)。藉由磊晶生長方法，使用化學氣相沉積(CVD)、原子層沉積(ALD)或分子束磊晶(MBE)來形成第二源極/汲極(S/D)磊晶層80B。如圖22A至圖22E所示，介電材料層的一部分保留在第二源極/汲極(S/D)磊晶層與鰭片結構的底部11B之間。在第二源極/汲極(S/D)磊晶層80B形成之後，移除第三保護層59，如圖23A至圖23E所示。
隨後，形成襯層85，且接著形成層間介電質(interlayer dielectric，ILD)層90，如圖24A至圖24E所示。襯層85係以例如氮化矽的氮化矽基材料製成，且在隨後的蝕刻操作中作為接觸蝕刻停止層(contact etch stop layer，CESL)。用於層間介電質層90的材料包括含有矽、 氧、碳和/或氫的化合物，例如二氧化矽、摻碳氫氧化矽(SiCOH)與碳氧化矽(SiOC)。例如聚合物的有機材料可用於層間介電質層90。在層間介電質層90形成之後，執行例如化學機械研磨(CMP)的平坦化操作，因此暴露犧牲閘極電極層54，如圖24A至圖24E所示。
接著，如圖25A至圖25E所示，移除犧牲閘極電極層54與犧牲閘極介電層52，從而暴露鰭片結構的通道區。在移除犧牲閘極結構的期間，層間介電質層90保護第一源極/汲極(S/D)磊晶層80A與第二源極/汲極(S/D)磊晶層80B。可使用電漿乾蝕刻和/或濕蝕刻來移除犧牲閘極結構。當犧牲閘極電極層54為多晶矽且層間介電質層90為二氧化矽，可使用例如四甲基氫氧化銨(TMAH)溶液的濕蝕刻劑來選擇性地移除犧牲閘極電極層54。隨後使用電漿乾蝕刻和/或濕蝕刻來移除犧牲閘極介電層52。
隨後，形成第四保護層87以覆蓋相應於第一鰭片結構30A(對於N型通道區而言)的區域，如圖26A至圖26E所示。圖26A為暴露通道區的透視圖。在一些實施例中，第四保護層87包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合，且其透過毯覆沉積而形成，所述毯覆沉積例如為包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程。在特定實施例中，第四保護層87係以氮化矽製成。在毯覆層形成之後，透過使 用一個或多個微影與蝕刻操作來形成第四保護層87。
在第四保護層87形成之後，移除第一鰭片結構30A的通道區的第一半導體層20，從而形成第二半導體層25的半導體線，如圖27A至圖27E所示。
可使用能夠選擇性地蝕刻第一半導體層20的蝕刻劑來移除或蝕刻第一半導體層20。第一半導體層20的蝕刻包含濕蝕刻和/或乾蝕刻。可使用例如氫氧化銨(NH4OH)溶液的濕蝕刻劑來選擇性地蝕刻第一半導體層20。
接著，移除第四保護層87，且形成第五保護層89以覆蓋相應於第一鰭片結構30A(對於N型通道區而言)的區域，如圖28A至圖28E所示。在一些實施例中，第五保護層89包含氮化矽基材料，例如氮化矽(SiN)、氮氧化矽(SiON)、氮碳氧化矽(SiOCN)或碳氮化矽(SiCN)及其組合，且其透過毯覆沉積而形成，所述毯覆沉積例如為包含低壓化學氣相沉積(LPCVD)與電漿輔助化學氣相沉積(PECVD)的化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適合的製程。在特定實施例中，第五保護層89係以氮化矽製成。在毯覆層形成之後，透過使用一個或多個微影與蝕刻操作來形成第五保護層89。
在第五保護層89形成之後，移除第二鰭片結構30B的通道區的第二半導體層25，從而形成縮合的第一半導體層22的半導體線，如圖29A至圖29E所示。
可使用能夠選擇性地蝕刻第二半導體層25的 蝕刻劑來移除或蝕刻第二半導體層25。第二半導體層25的蝕刻包含濕蝕刻和/或乾蝕刻。可使用例如四甲基氫氧化銨(TMAH)溶液的濕蝕刻劑來選擇性地蝕刻第二半導體層25。接著，移除第五保護層89，如圖30A至圖30E所示。
在縮合的第一半導體層22的線形成之後，圍繞第一鰭片結構30A中的第二半導體層25的線與第二鰭片結構30B中的縮合的第一半導體層22的線來形成閘極介電層104，如圖31A至圖31E所示。在一些實施例中，閘極介電層104包含一層或多層的介電材料，例如二氧化矽、氮化矽、高介電係數(high-k)介電材料、其他適合的介電材料和/或其組合。例示的高介電係數介電材料包含二氧化鉿(HfO2)、矽酸鉿(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、二氧化鋯、氧化鋁、二氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的高介電係數介電材料和/或其組合。在一些實施例中，在通道層與閘極介電層104之間形成介面層102。閘極介電層104可透過化學氣相沉積(CVD)、原子層沉積(ALD)或其他適合的方法而形成。在一實施例中，使用例如原子層沉積(ALD)的高度共形沉積製程來形成閘極介電層104，以確保在每個通道層周圍形成的閘極介電層具有均勻厚度。在一實施例中，閘極介電層104的厚度的範圍為約1nm至6nm。
再者，於閘極介電層104上形成閘極電極層108，如圖32A至圖32E所示。在一些實施例中，閘極電極 層108形成在閘極介電層104上方以圍繞每個通道層。閘極電極層108包含一層或多層的導電材料，例如多晶矽、鋁(Al)、銅(Cu)、鈦(Ti)、鉭(Ta)、鎢(W)、鈷(Co)、鉬(Mo)、氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、氮化鈦(TiN)、氮化鎢(WN)、鈦化鋁(TiAl)、氮化鋁鈦(TiAlN)、氮碳化鉭(TaCN)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、金屬合金、其他適合的材料和/或其組合。閘極電極層108之形成可透過化學氣相沉積(CVD)、原子層沉積(ALD)、電鍍或其他適合的方法。也在層間介電質層90的上表面上沉積閘極電極層。接著透過使用例如化學機械研磨(CMP)來平坦化形成在層間介電質層90上的閘極介電層與閘極電極層，直到暴露層間介電質層90。
在特定實施例中，一層或多層功函數調變層106插入在閘極介電層104與閘極電極層108之間。功函數調變層106係以導電材料製成，所述導電材料例如為單層的氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、鋁(Al)、鈦化鋁(TiAl)、鈦鉿(HfTi)、鈦化矽(TiSi)、鉭化矽(TaSi)、碳化鈦鋁(TiAlC)或這些材料中的其中兩種或多種的多層。對於N型通道場效電晶體而言，使用氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)、鈷(Co)、鈦化鋁(TiAl)、鈦鉿(HfTi)、鈦化矽(TiSi)與鉭化矽(TaSi)的其中一者或多者作為功函數調變層。功函數調變層106之形成係透過原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣 相沉積(CVD)、電子束蒸鍍(e-beam evaporation)或其他適合的製程。再者，功函數調變層106可分別形成以用於使用不同金屬層的N型通道場效電晶體與P型通道場效電晶體。
應理解，全繞閘極場效電晶體經過進一步的互補式金屬氧化物半導體(CMOS)製程而形成各種特徵，例如接觸/介層窗(contacts/vias)、互連金屬層、介電層、鈍化層等等。
圖33A是圖32B的放大圖。在第一鰭式結構30A上形成N型通道全繞閘極場效電晶體，在第二鰭式結構30B上形成P型通道全繞閘極場效電晶體。在一些實施例中，N型通道全繞閘極場效電晶體的每個通道(第一通道)係以矽製成(第一半導體層25)，P型通道全繞閘極場效電晶體的每個通道(第二通道)係以矽鍺(SiGe)製成，其中矽鍺(SiGe)的鍺濃度在如上所述的製造操作期間增加(縮合的第二半導體層22)。在特定實施例中，P型通道全繞閘極場效電晶體的第二通道係以矽鍺合金(Si1-zGez)製成，其中0.40≦z≦0.50。
在一些實施例中，第一通道的厚度H11的範圍為約5nm至10nm，相鄰的第一通道之間的間隔S11的範圍為約5nm至10nm，且第一通道的寬度W11的範圍為約3nm至8nm。在一些實施例中，第二通道的厚度H21的範圍為約5nm至10nm，相鄰的第二通道之間的間隔S21的範圍為約5nm至10nm，且第二通道的寬度W21的範圍為約3nm至 8nm。在特定實施例中，H11≧5nm≧S11且H21≧5nm≧S21。再者，在一些實施例中，W11≧W21≧3nm。在特定實施例中，W21<H21。在特定實施例中，S11<H21且H11>S21，同時S11+H11基本上相同於S21+H21。在X-Y剖面的每個通道的中心測量厚度、寬度與間隔。
如圖33A所示，在一些實施例中，第一通道(25)的剖面具有帶圓角的矩形形狀。在其他實施例中，第一通道的剖面具有橢圓形或帶圓角的方形。在一些實施例中，第二通道(22)的剖面具有帶圓角的矩形形狀、橢圓形或帶圓角的方形。在其他實施例中，如圖33B與圖33C所示，第二通道(22)的剖面具有狗骨形狀或線軸(thread-spool)(或捲線軸(bobbin))形狀。在圖33B中，兩邊是凹形的，且在圖33C中，四邊是凹形的。如上所述，執行後續熱退火製程，即矽鍺縮合製程，其增加矽鍺層內的鍺濃度且還造成鍺向外擴散到用於P型通道場效電晶體的矽層。靠近矽鍺介面的矽塊層具有例如20-30%的鍺之鍺汙染；靠近矽鍺介面的矽表層具有更高的鍺濃度，例如30-40%的鍺，這是因為縮合與向外擴散效應；且在縮合製程之後，矽鍺塊層具有最高的鍺濃度，例如40-50%的鍺。所得到的鍺分佈影響了矽鍺線形成的輪廓。由於具有較低鍺濃度的矽鍺區域的蝕刻率高，所以矽鍺線變為狗骨形狀。
圖34A至圖34E示出根據本揭露的實施例之各種全繞閘極場效電晶體的剖視圖。在圖33A中，藉由N型通道全繞閘極場效電晶體與P型通道全繞閘極場效電晶體來 共用一個閘極結構。在其他實施例中，如圖34A與圖34B所示，分別為N型通道全繞閘極場效電晶體與P型通道全繞閘極場效電晶體提供單獨的閘極結構108A與108B，同時在相同基板上提供N型通道全繞閘極場效電晶體與P型通道全繞閘極場效電晶體。
再者，在一些實施例中，如圖34C至圖34E所示的各種P型通道場效電晶體以及如圖32A、圖34A和/或圖34B所示的全繞閘極場效電晶體一起提供在相同基板上。在圖34C中，通道是從底部鰭片結構11連續突出的半導體鰭片25A。在圖34D中，通道包含第一半導體層20與第二半導體層25的堆疊結構。可透過不執行縮合製程且不從通道區移除第二半導體層來形成這種結構。在圖34E中，通道包含縮合的第一半導體層20與第二半導體層25的堆疊結構。可透過執行縮合製程且不從通道區移除第二半導體層來形成這種結構。如圖34C所示的場效電晶體可為N型場效電晶體。
在一些實施例中，如圖32A所示的全繞閘極場效電晶體為CMOS裝置且用於半導體裝置的核心區域，其包含以最小設計規則形成的場效電晶體。在一些實施例中，如圖34C至圖34E所示的場效電晶體用於半導體裝置的輸入輸出(I/O)區域。
圖35A至圖37E示出根據本揭露的其他實施例之製造全繞閘極場效電晶體裝置的製程順序。應理解，額外之操作可在圖35A至圖37E的製程之前、期間以及之後實施，且對於所述方法的額外實施例，可取代或省略下文所描 述的操作的一些部分。操作/製程的順序係可互換的。
在形成如圖16A至圖16E所示的結構之後，透過使用乾蝕刻和/或濕蝕刻，鰭片結構30A與30B的源極/汲極(S/D)區向下凹陷至相等於或低於絕緣隔離層40的上表面，如圖35A至圖35E所示。在此階段，在犧牲閘極結構下方的第一半導體層20與第二半導體層25的堆疊層的端部具有與側壁間隔物55齊平的基本平坦的面，如圖35D與圖35E所示。在一些實施例中，略微水平地蝕刻第一半導體層20與第二半導體層25的堆疊層的端部。
隨後，透過使用與前述實施例相同或相似的製程來形成如圖36A至圖36E所示的第一源極/汲極(S/D)磊晶層80A與第二源極/汲極(S/D)磊晶層80B。如上所述，分別形成第一源極/汲極(S/D)磊晶層80A與第二源極/汲極(S/D)磊晶層80B。
接著，透過使用與前述實施例相同或相似的製程，閘極結構包含閘極介電層104與閘極電極層108，如圖37A至圖37E所示。
應理解，全繞閘極場效電晶體經過進一步的CMOS製程而形成各種特徵，例如接觸/介層窗(contacts/vias)、互連金屬層、介電層、鈍化層等等。
本文所描述的各種實施例或示例提供優於現有技術的幾個優點。舉例來說，在本揭露中，在矽/矽鍺堆疊層中的矽鍺層起初具有相對低的鍺濃度，以減輕矽與矽鍺之間的晶格不匹配。因此，可增加在矽鍺層上形成的矽磊晶層 的厚度。再者，透過採用鍺縮合製程來增加之後的鍺濃度，可改善矽鍺P型通道全繞閘極場效電晶體的性能。
應理解，並非所有優點皆於本文中討論到，所有實施例或示例並不存在某些特定優點，且其他實施例或示例可以具有不同的優點。
根據本揭露的一態樣，提出一種製造半導體裝置的方法，包含：形成鰭片結構，其中包含鍺的多個第一半導體層與多個第二半導體層交替地層疊於鰭片結構的底部上；增加所述第一半導體層中的鍺濃度；於鰭片結構上形成犧牲閘極結構；於鰭片結構的源極/汲極區上形成源極/汲極磊晶層；移除犧牲閘極結構；移除於通道區中的所述第二半導體層，從而釋放鍺濃度增加的所述第一半導體層；以及在鍺濃度增加的所述第一半導體層周圍形成閘極結構。在一個或多個的前述與以下實施例中，係藉由氧化所述第一半導體層來增加鍺濃度。在一個或多個的前述與以下實施例中，增加鍺濃度係透過：於鰭片結構上形成氧化層；以及執行熱處理，從而氧化所述第一半導體層。在一個或多個的前述與以下實施例中，熱處理係於800℃至1000℃之間執行。在一個或多個的前述與以下實施例中，於熱處理之後，移除氧化層。在一個或多個的前述與以下實施例中，形成氧化層、執行熱處理以及移除氧化層係重複進行的。在一個或多個的前述與以下實施例中，第一半導體層係以矽鍺製成，且鍺濃度增加之後的第一半導體層的鍺濃度的範圍係從45atomic%至55atomic%。在一個或多個的前述與以下實施例中，第 二半導體層係以矽製成，且鍺濃度增加之前的第一半導體層的鍺濃度的範圍係從35atomic%至45atomic%。在一個或多個的前述與以下實施例中，當犧牲閘極結構形成於鰭片結構上時，所述第一半導體層的寬度係小於所述第二半導體層的寬度。在一個或多個的前述與以下實施例中，當犧牲閘極結構形成於鰭片結構上時，所述第一半導體層的寬度係小於所述第一半導體層的厚度。
根據本揭露的另一態樣，提出一種製造半導體裝置的方法，包含：形成第一鰭片結構與第二鰭片結構，其中包含鍺的多個第一半導體層與多個第二半導體層交替地層疊於第一鰭片結構與第二鰭片結構之每一者的底部上；在保護第一鰭片結構的同時，增加第二鰭片結構的所述第一半導體層中的鍺濃度；於第一鰭片結構與第二鰭片結構上形成犧牲閘極結構；於第一鰭片結構的源極/汲極區上形成第一源極/汲極磊晶層；於第二鰭片結構的源極/汲極區上形成第二源極/汲極磊晶層；移除犧牲閘極結構；移除於第一鰭片結構的通道區中的所述第一半導體層，從而釋放所述第二半導體層；移除於第二鰭片結構的通道區中的所述第二半導體層，從而釋放鍺濃度增加的所述第一半導體層；以及在被釋放的所述第一半導體層與被釋放的所述第二半導體層周圍形成閘極結構。在一個或多個的前述與以下實施例中，係藉由氧化所述第一半導體層來增加鍺濃度。在一個或多個的前述與以下實施例中，增加鍺濃度係透過：於第二鰭片結構上形成氧化層；以及執行熱處理，從而氧化所述第一半導體 層。在一個或多個的前述與以下實施例中，熱處理係於800℃至1000℃之間執行。在一個或多個的前述與以下實施例中，於熱處理之後，移除氧化層。在一個或多個的前述與以下實施例中，形成氧化層、執行熱處理以及移除氧化層係重複進行的。在一個或多個的前述與以下實施例中，第一半導體層係以矽鍺製成，且在鍺濃度增加之後的第一半導體層的鍺濃度的範圍係從45atomic%至55atomic%。在一個或多個的前述與以下實施例中，第二半導體層係以矽製成，且在鍺濃度增加之前的第一半導體層的鍺濃度的範圍係從35atomic%至45atomic%。
根據本揭露的另一態樣，提出一種製造半導體裝置的方法，包含：形成第一鰭片結構與第二鰭片結構，其中包含鍺的多個第一半導體層與多個第二半導體層交替地層疊於第一鰭片結構與第二鰭片結構之每一者的底部上；在保護第一鰭片結構的同時，增加第二鰭片結構的所述第一半導體層中的鍺濃度；於第一鰭片結構與第二鰭片結構上形成犧牲閘極結構；於第一鰭片結構的源極/汲極區上形成第一源極/汲極磊晶層；於第二鰭片結構的源極/汲極區上形成第二源極/汲極磊晶層；移除犧牲閘極結構；移除於第一鰭片結構的通道區中的所述第一半導體層，從而釋放所述第二半導體層；移除於第二鰭片結構的通道區中的所述第二半導體層，從而釋放鍺濃度增加的所述第一半導體層；以及在被釋放的所述第一半導體層周圍形成第一閘極結構且在被釋放的所述第二半導體層周圍形成第二閘極結構。在一個或多個 的前述與以下實施例中，係藉由氧化所述第一半導體層來增加鍺濃度。
根據本揭露的一態樣，提出一種半導體裝置，包含：多條半導體線、源極/汲極磊晶層以及閘極結構。多條半導體線係垂直地設置，每一所述半導體線具有通道區。源極/汲極磊晶層連接至所述半導體線。閘極結構形成於所述半導體線周圍。所述半導體線係以矽鍺合金(Si1-xGex)製成，其中0.45≦x≦0.55。在一個或多個的前述與以下實施例中，所述半導體線的寬度係小於所述半導體線的厚度。在一個或多個的前述與以下實施例中，所述半導體線的寬度係大於相鄰半導體線之間的間隔。在一個或多個的前述與以下實施例中，所述半導體線的剖面具有狗骨形狀或線軸形狀。在一個或多個的前述與以下實施例中，半導體裝置為P型通道場效電晶體。在一個或多個的前述與以下實施例中，源極/汲極磊晶層環繞在所述半導體線的源極/汲極區之周圍。在一個或多個的前述與以下實施例中，半導體裝置更包含設置於閘極結構與源極/汲極磊晶層之間的多個介電內間隔物。在一個或多個的前述與以下實施例中，半導體裝置更包含多個閘極側壁間隔物，其中閘極側壁間隔物係由與介電內間隔物不同的材料所製成。在一個或多個的前述與以下實施例中，介電內間隔物的材料為氮化矽。在一個或多個的前述與以下實施例中，側壁間隔物的材料為碳氧化矽(SiOC)、碳氮氧化矽(SiOCN)與碳氮化矽(SiCN)之一。
根據本揭露的另一態樣，提出一種半導體裝 置，包含：N型通道場效電晶體與P型通道場效電晶體。N型通道場效電晶體包含多條第一半導體線以及第一源極/汲極磊晶層。所述第一半導體線係垂直地設置，每一所述第一半導體線具有通道區。第一源極/汲極磊晶層連接至所述第一半導體線。P型通道場效電晶體包含多條第二半導體線以及第二源極/汲極磊晶層。所述第二半導體線係垂直地設置，每一所述第二半導體線具有通道區。第二源極/汲極磊晶層連接至所述第二半導體線。所述第二半導體線係以矽鍺合金(Si1-xGex)製成，其中0.45≦x，且所述第一半導體線係以矽或矽鍺合金(Si1-yGey)製成，其中0<y≦0.2。在一個或多個的前述與以下實施例中，所述第二半導體線係以矽鍺合金(Si1-xGex)製成，其中0.45≦x≦0.55，且所述第一半導體線係以矽製成。在一個或多個的前述與以下實施例中，所述第二半導體線的寬度係小於所述第一半導體線的寬度。在一個或多個的前述與以下實施例中，所述第二半導體線的寬度係小於所述第一半導體線的厚度。在一個或多個的前述與以下實施例中，第一源極/汲極磊晶層環繞在所述第一半導體線的源極/汲極區之周圍，且第二源極/汲極磊晶層環繞在所述第二半導體線的源極/汲極區之周圍。在一個或多個的前述與以下實施例中，第一源極/汲極磊晶層形成於所述第一半導體線的端面上。在一個或多個的前述與以下實施例中，所述第二半導體線的剖面具有狗骨形狀或線軸形狀。在一個或多個的前述與以下實施例中，所述第一半導體線的剖面具有帶圓角或橢圓形的矩形形狀。在一個或多個的 前述與以下實施例中，半導體裝置更包含閘極電極層，閘極電極層形成於所述第一半導體線周圍以及所述第二半導體線周圍。
根據本揭露的另一態樣，提出一種半導體裝置，包含：第一P型通道場效電晶體與第二P型通道場效電晶體。第一P型通道場效電晶體包含多條第一半導體線、第一源極/汲極磊晶層以及第一閘極結構。所述第一半導體線係垂直地設置，每一所述第一半導體線具有通道區。第一源極/汲極磊晶層連接至所述第一半導體線。第一閘極結構形成於所述第一半導體線周圍。第二P型通道場效電晶體包含多條第二半導體線、多條第三半導體線、第二源極/汲極磊晶層以及第二閘極結構。所述第二半導體線與所述第三半導體線係交替地堆疊。所述第二半導體線與所述第三半導體線之每一者係具有通道區。第二源極/汲極磊晶層連接至所述第二半導體線與所述第三半導體線。第二閘極結構形成於所述第二半導體線周圍。所述第一半導體線與所述第二半導體線係以矽鍺合金(Si1-xGex)製成，其中0.45≦x，且所述第三半導體線係以矽或矽鍺合金(Si1-yGey)製成，其中0<y≦0.2。
以上概述了數個實施例的特徵，因此熟習此技藝者可以更了解本揭露的態樣。熟習此技藝者應了解到，其可輕易地把本揭露當作基礎來設計或修改其他的製程與結構，藉此實現和在此所介紹的這些實施例相同的目標及/或達到相同的優點。熟習此技藝者也應可明白，這些等效的建 構並未脫離本揭露的精神與範圍，並且他們可以在不脫離本揭露精神與範圍的前提下做各種的改變、替換與變動。
10‧‧‧基板
11A、11B‧‧‧鰭片結構之底部
22‧‧‧縮合後的第一半導體層
25‧‧‧第二半導體層
35A、35B‧‧‧鰭式襯層
40‧‧‧隔離絕緣層
80A、80B‧‧‧源極/汲極(S/D)磊晶層
85‧‧‧襯層
90‧‧‧層間介電質層
X、Z‧‧‧方向

Claims (20)

  1. 一種製造半導體裝置的方法，包含：形成一鰭片結構，其中包含鍺的複數個第一半導體層與複數個第二半導體層交替地層疊於該鰭片結構的一底部上；增加該些第一半導體層中的一鍺濃度；於該鰭片結構上形成一犧牲閘極結構；於該鰭片結構的一源極/汲極區上形成一源極/汲極磊晶層；移除該犧牲閘極結構；移除於一通道區中的該些第二半導體層，從而釋放該鍺濃度增加的該些第一半導體層；以及在該鍺濃度增加的該些第一半導體層周圍形成一閘極結構。
  2. 如申請專利範圍第1項所述之方法，其中係藉由氧化該些第一半導體層來增加該鍺濃度。
  3. 如申請專利範圍第2項所述之方法，其中增加該鍺濃度係透過：於該鰭片結構上形成一氧化層；以及執行一熱處理，從而氧化該些第一半導體層。
  4. 如申請專利範圍第3項所述之方法，其中該熱處理係於攝氏800度(℃)至1000℃之間執行。
  5. 如申請專利範圍第3項所述之方法，其中於該熱處理之後，移除該氧化層。
  6. 如申請專利範圍第5項所述之方法，其中形成該氧化層、執行該熱處理以及移除該氧化層係重複進行的。
  7. 如申請專利範圍第1項所述之方法，其中：該第一半導體層係以矽鍺(SiGe)製成，且該鍺濃度增加之後的該第一半導體層的該鍺濃度的範圍係從45原子比(atomic%)至55atomic%。
  8. 如申請專利範圍第7項所述之方法，其中：該第二半導體層係以矽製成，且該鍺濃度增加之前的該第一半導體層的該鍺濃度的範圍係從35atomic%至45atomic%。
  9. 如申請專利範圍第1項所述之方法，其中當該犧牲閘極結構形成於該鰭片結構上時，該些第一半導體層的一寬度係小於該些第二半導體層的一寬度。
  10. 如申請專利範圍第1項所述之方法，其中當該犧牲閘極結構形成於該鰭片結構上時，該些第一半導體層的一寬度係小於該些第一半導體層的一厚度。
  11. 一種製造半導體裝置的方法，包含：形成一第一鰭片結構與一第二鰭片結構，其中包含鍺的複數個第一半導體層與複數個第二半導體層交替地層疊於該第一鰭片結構與該第二鰭片結構之每一者的一底部上；在保護該第一鰭片結構的同時，增加該第二鰭片結構的該些第一半導體層中的一鍺濃度；於該第一鰭片結構與該第二鰭片結構上形成一犧牲閘極結構；於該第一鰭片結構的一源極/汲極區上形成一第一源極/汲極磊晶層；於該第二鰭片結構的一源極/汲極區上形成一第二源極/汲極磊晶層；移除該犧牲閘極結構；移除於該第一鰭片結構的一通道區中的該些第一半導體層，從而釋放該些第二半導體層；移除於該第二鰭片結構的一通道區中的該些第二半導體層，從而釋放該鍺濃度增加的該些第一半導體層；以及在被釋放的該些第一半導體層與被釋放的該些第二 半導體層周圍形成一閘極結構。
  12. 如申請專利範圍第11項所述之方法，其中係藉由氧化該些第一半導體層來增加該鍺濃度。
  13. 如申請專利範圍第12項所述之方法，其中增加該鍺濃度係透過：於該第二鰭片結構上形成一氧化層；以及執行一熱處理，從而氧化該些第一半導體層。
  14. 如申請專利範圍第13項所述之方法，其中該熱處理係於800℃至1000℃之間執行。
  15. 如申請專利範圍第13項所述之方法，其中於該熱處理之後，移除該氧化層。
  16. 如申請專利範圍第15項所述之方法，其中形成該氧化層、執行該熱處理以及移除該氧化層係重複進行的。
  17. 如申請專利範圍第11項所述之方法，其中：該第一半導體層係以矽鍺製成，且在該鍺濃度增加之後的該第一半導體層的該鍺濃度 的範圍係從45atomic%至55atomic%。
  18. 如申請專利範圍第17項所述之方法，其中：該第二半導體層係以矽製成，且在該鍺濃度增加之前的該第一半導體層的該鍺濃度的範圍係從35atomic%至45atomic%。
  19. 一種半導體裝置，包含：複數條半導體線，垂直地設置，其中每一該些半導體線具有一通道區；一源極/汲極磊晶層，連接至該些半導體線；以及一閘極結構，形成於該些半導體線周圍，其中：該些半導體線係以矽鍺合金(Si 1-xGe x)製成，其中0.45≦x≦0.55。
  20. 如申請專利範圍第19項所述之半導體裝置，其中該些半導體線的一寬度係小於該些半導體線的一厚度。
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