TWI772699B - 半導體元件的製造方法及其元件 - Google Patents

半導體元件的製造方法及其元件 Download PDF

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TWI772699B
TWI772699B TW108138724A TW108138724A TWI772699B TW I772699 B TWI772699 B TW I772699B TW 108138724 A TW108138724 A TW 108138724A TW 108138724 A TW108138724 A TW 108138724A TW I772699 B TWI772699 B TW I772699B
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layer
fin structure
semiconductor
gate
semiconductor layers
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TW108138724A
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TW202038338A (zh
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鄭兆欽
陳奕升
江宏禮
陳自強
張開泰
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件的製造方法，形成鰭結構，具有下鰭結構和設置在下鰭結構上的上鰭結構。上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層。第一半導體層被部分地蝕刻以減少第一半導體層的寬度。形成氧化物層在上鰭結構上。形成犧牲閘極結構在具有氧化物層的上鰭結構上。形成源極/汲極磊晶層在鰭結構的源極/汲極區域上。去除犧牲閘極結構以形成閘極空間。去除氧化物層以暴露閘極空間中的第二半導體層。形成閘極結構在閘極空間中的第二半導體層的周圍。

Description

半導體元件的製造方法及其元件
本揭露係關於一種半導體元件的製造方法及其元件。
隨著半導體工業逐步發展為奈米技術節點以追求更高的元件密度，更高的性能和更低的成本，來自製造和設計問題的挑戰導致三維設計的發展，例如多閘極場效電晶體(Field effect transistor，FET)，包括鰭式場效電晶體(FinFET)以及環繞式閘極(Gate-all-around，GAA)場效電晶體。在鰭式場效電晶體中，在鄰近閘極電極的通道區域與閘極介電層之間插入三個側表面。因為閘極結構在三個表面上圍繞(包裹)鰭，所以電晶體實質上具有三個閘極，控制經由鰭或通道區域的電流。遺憾地，第四側，其遠離閘電極位於通道的底部，因此不受閘極控制。相反地，在一個環繞式閘極場效電晶體(GAA FET)中，通道區域的所有側表面被閘極電極圍繞，由於更陡峭的次臨限擺動(Sub-threshold current swing,SS)和較小的汲極能障降低(DIBL)，允許在通道區域實現更充分的耗盡 (Depletion)以及減少短通道效應(Short-channel effects)。隨著電晶體尺寸不斷縮小到次10-15奈米技術節點，需要進一步改進GAA FET。
一種半導體元件的製造方法，包括：形成鰭結構，具有下鰭結構以及設置在下鰭結構上的上鰭結構，上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層；部分地蝕刻第一半導體層以減小第一半導體層的多個寬度；形成氧化物層在上鰭結構上；形成犧牲閘極結構在具有氧化物層的上鰭結構上；形成源極/汲極磊晶層在鰭結構的源極/汲極區域上；去除犧牲閘極結構以形成閘極空間；去除氧化物層以暴露閘極空間中的第二半導體層；以及形成閘極結構在閘極空間中的第二半導體層的周圍。
一種半導體元件的製造方法，包括：形成鰭結構，具有下鰭結構以及設置在下鰭結構上的上鰭結構，上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層；部分地蝕刻第一半導體層以減小第一半導體層的多個寬度；形成氧化物層在上鰭結構上；形成犧牲閘極結構在具有氧化物層的上鰭結構上；形成源極/汲極磊晶層在鰭結構的源極/汲極區域上；去除犧牲閘極結構以形成閘極空間；去除閘極空間中的氧化物層以暴露閘極空間中的第二半導體層；形成第三半導體層在每個暴露的第二半導體層上；藉由混合第三半導體層和第二半導體層形成多個通道線；以及形成閘極結構在閘極空間中的通道線的周圍。
一種半導體元件，包括：下鰭結構、多個半導體線、閘極結構、多個閘極側壁間隔物以及源極/汲極磊晶層。下鰭結構設置在基板上；多個半導體線設置在下鰭結構上；閘極結構設置在半導體線的多個通道區域上；多個閘極側壁間隔物設置在閘極結構之多個相對的側面上；並且介電層係由與閘極側壁間隔物不同的材料製成，包裹在閘極側壁間隔物之下的半導體線的周圍。
10:基板
12:雜質離子
11:下鰭結構
11A:下鰭結構
11B:下鰭結構
15:掩模層
15A:第一掩模層
15B:第二掩模層
20:第一半導體層
25:第二半導體層
26:第三半導體層
27:合金半導體層
29:氣隙
30:鰭結構
30A:鰭結構
30B:鰭結構
35A:第一鰭襯墊層
35B:第二鰭襯墊層
40:隔離絕緣層
45:氧化物層
50:犧牲閘極結構
54:犧牲閘極電極層
55:閘極側壁間隔物
56:掩模層
60A:第一源極/汲極磊晶層
60B:第二源極/汲極磊晶層
62:源極/汲極磊晶層
63:第一絕緣襯墊層
65:層間介電質(ILD)層
102:界面層
104:閘極介電層
106:功函數調整層
108:閘電極層
110:第二絕緣襯墊層
115:第二ILD層
120:主體層
122:襯墊層
D1:蝕刻度
H1:高度
W1:寬度
本揭露內容從後續實施例以及附圖可以更佳理解。應注意的是，根據本產業的標準作業，許多構件未按照比例繪製。事實上，許多構件之尺寸可以任意地放大或縮小以清楚論述。
圖1繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖2繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖3A和圖3B繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖4A和圖4B繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖5繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖6A，圖6B，圖6C和圖6D繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖7A，圖7B，圖7C和圖7D繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖8A，圖8B，圖8C和圖8D繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖9A，圖9B，圖9C，圖9D和圖9E繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖10A，圖10B，圖10C，圖10D，圖10E和圖10F繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖11A，圖11B，圖11C，圖11D，圖11E，圖11F和圖11G繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖12A，圖12B，圖12C，圖12D和圖12E繪示根據本揭露之一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖13A繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖13B繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖13C繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的視圖。
圖14A，圖14B，圖14C，圖14D，圖14E和圖14F繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各 個階段之一的各種視圖。
圖15A，圖15B，圖15C，圖15D，圖15E和圖15F繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖16A，圖16B，圖16C，圖16D和圖16E繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖17A，圖17B，圖17C和圖17D繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖18A，圖18B，圖18C和圖18D繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖19A，圖19B，圖19C，圖19D和圖19E繪示根據本揭露之另一實施例的GAA FET元件的連續製程的各個階段之一的各種視圖。
圖20A，圖20B，圖20C和圖20D繪示根據本揭露之一些實施例的GAA FET元件的各種視圖。
應理解，以下的揭露內容提供許多不同實施例或範例，以實施本揭露內容的不同結構。以下敘述構件及排列方式的特定實施例或範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本揭露內容。舉例來說，構 件尺寸並未限定於所揭露的範圍或數值，而是根據製程條件及/或元件的期望特性。再者，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件上或上方，即表示其包含了上述第一特徵部件與上述第二特徵部件形成直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使得上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。為達簡化及明確目的，不同特徵部件可隨意繪構成不同尺寸。為求簡化，在所附圖式中，可省略一些層別/特徵部件。
再者，在空間上的相關用語，例如”之下”、”以下”、”下”、”以上”、”上”等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位(旋轉90度或其他方位)且此處所使用的空間上的相關符號同樣有相應的解釋。此外，”由...所構成”一詞可意味”包含”或”僅包含”。再者，在以下製程中，可於所述操作中或之間進行一或多個額外的操作，且可更改操作順序。在此揭露中"A，B及C中的一個"一詞意味A，B及/或C(A，B，C，A及B，A及C，B及C或A，B及C)，並不表示A中的一個元素，B中的一個元素以及C中的一個元素，除非另有說明。
在以下的實施例中，除非另有說明，否則可以在另一實施例中採用一個實施例的材料，配置，尺寸，操作 及/或過程，並且可以省略其詳細說明。
具有奈米尺寸之通道的環繞式閘極(GAA)場效電晶體，例如奈米線或奈米片，在半導體積體電路之進一步的技術節點中，被視為具有前景的元件，以實現較低的操作電源，較高的元件性能，較高的元件密度，以及較低的製程成本等。以上述準則來看，如何優化製程流程是關鍵挑戰。在GAA FET製造流程中，用於通道磊晶(channel epitaxy)、內側間隔(inner spacer)、形成奈米線(nanowire)，以及形成具有高k(介電常數)介電質的金屬閘極之製程為常見的製程瓶頸。
在本揭露中，提出了解決上述問題的元件結構及其製造方法。
圖1至圖12E繪示根據本揭露之一實施例之製造GAA FET元件的連續製程。應當理解，可以在圖1至圖12E所示的操作之前，期間和之後提供額外操作，以及如下所述的一些操作可被替換或消除，對於該方法的額外實施例，其操作/過程的順序是可互換的。
如圖1所示，將雜質離子(摻雜劑)12植入矽基板10中以形成井區域。執行離子植入係為預防擊穿效應(punch-through effect)。在一些實施例中，基板10至少在其表面部分上包括單晶半導體層。基板10可以包括單晶半導體材料，例如但不限於Si，Ge，SiGe，GaAs，InSb，GaP，GaSb，InAlAs，InGaAs，GaSbP，GaAsSb和InP。在一個實施例中，基板10由結晶矽製成。
基板10可包括在其表面區域中一或多個緩衝層(未繪示)。緩衝層可用於逐漸地將晶格常數從基板的晶格常數變化為源極/汲極區域的晶格常數。緩衝層可以由磊晶生長的單晶半導體材料形成，例如但不限於Si，Ge，GeSn，SiGe，GaAs，InSb，GaP，GaSb，InAlAs，InGaAs，GaSbP，GaAsSb，GaN，GaP和InP。在一個具體的實施例中，基板10包括在矽基板10上磊晶生長的矽鍺(SiGe)緩衝層。SiGe緩衝層的Ge濃度可以從最底部緩衝層的30atomic%鍺增加到最頂部緩衝層的70atomic%鍺。基板10可以包括已經適當地摻雜雜質(例如，p型或n型導電性)的各種區域。舉例來說，摻雜劑12係為用於n型FinFET的硼(BF2)和用於p型FinFET的磷。
如圖2所示，在基板10上形成堆疊的半導體層。堆疊的半導體層包括第一半導體層20和第二半導體層25。再者，在堆疊層上形成掩模層15。第一半導體層20及第二半導體層25係由具有不同晶格常數的材料所製成，並且可包括一或多個層的Si，Ge，SiGe，GeSn，SiGeSn，GaAs，InSb，GaP,GaSb，InAlAs，InGaAs，GaSbP，GaAsSb或InP。
在一些實施例中，第一半導體層20和第二半導體層25係由Si，Si化合物，SiGe，Ge或Ge化合物製成。在特定實施例中，第一半導體層20為Si1-xGex，其中0.15
Figure 108138724-A0305-02-0010-1
x
Figure 108138724-A0305-02-0010-2
0.5，並且第二半導體層25為Si。在一些實施例中，0.15
Figure 108138724-A0305-02-0010-4
x
Figure 108138724-A0305-02-0010-6
0.25，在其它實施例中，第二半導體層25由 Si1-yGey製成，其中y是等於或小於約0.2，以及x>y。
如圖2所示，設置五層第一半導體層20以及五層第二半導體層25。然而，這些層的數目不限於五個，也可以小到為1(每一層)，在一些實施例中，形成2-20層的每個第一與第二半導體層。藉由調整堆疊層的數量，可以調整GAA FET元件的驅動電流。
磊晶地形成第一半導體層20和第二半導體層25在基板10上。第一半導體層20的厚度可等於或小於第二半導體層25的厚度，在一些實施例中，第一半導體層20的厚度在約2nm至約10nm的範圍內，在其他實施方案中，在約3nm至約5nm的範圍內。在一些實施例中，第二半導體層25的厚度在至約5nm至約20nm的範圍內，在其他實施方案中，在約7.5nm至約12.5nm的範圍內。第一半導體層和第二半導體層中的每一個的厚度可以相同，或者可以變化。
在一些實施例中，底部第一半導體層(最接近基板10的層)的厚度大於其他的第一半導體層的厚度。在一些實施方案中，底部第一半導體層的厚度在約10nm至約50nm的範圍內，或者在其他實施例中，其在20nm至40nm的範圍內。
在一些實施例中，掩模層15包括第一掩模層15A和第二掩模層15B。第一掩模層15A是由氧化矽製成的襯墊氧化物層，其可以藉由熱氧化形成。第二掩模層15B係由氮化矽(SiN)製成，其藉由化學氣相沉積(CVD)形成，包括低壓化學氣相沈積(LPCVD)和電漿增強化學氣相 沉積(PECVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他合適的方法。使用圖案操作包括微影和蝕刻，將掩模層15圖案化為掩模圖案。
接著，如圖3A和圖3B所示，藉由圖案化的掩模層圖案化第一和第二半導體層20、25的堆疊層，從而使堆疊層形成為鰭結構30，鰭結構30在Y方向上延伸，並且沿著X方向佈置。
可以藉由任何合適的方法來圖案化鰭結構30。例如，可以使用一或多個微影製程來圖案化鰭結構，包括雙重圖案化或多重圖案化製程。通常，雙重圖案化或多重圖案化製程結合微影和自對準製程，從而允許產生具有較小間距的圖案，例如，小於相對於使用單個、直接光微影製程所獲得的間距。舉例來說，在一個實施例中，在基板上形成並使用微影製程圖案化犧牲層。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。然後去除犧牲層，接著可以使用剩餘的間隔物或心軸來圖案化鰭結構。
如圖3A及圖3B所示，兩個鰭結構30A和30B沿X方向佈置。但鰭結構的數量不限於兩個，並且可以小到一個以及三個或更多。在一些實施例中，形成一或多個虛設鰭結構在鰭結構30的兩側上，以改善圖案化操作中的圖案逼真度。如圖3A和圖3B所示，鰭結構30具有由堆疊的半導體層20、25構成的上部和井部分，其對應於下鰭結構11。在一些實施例中，鰭結構30A用於p通道GAA FET，鰭結構30B用於n通道GAA FET。如圖4A所示，鰭結構30A和30B 分別設置在下鰭結構11A和11B上。在其他實施例中，鰭結構用於相同類型的場效電晶體。
在一些實施例中，鰭結構30之上部的寬度W1沿X方向在約5nm至約30nm的範圍內。在其他實施例中，在約7.5nm至約15nm的範圍內。沿著Z方向上該鰭結構30的高度H1在約5nm至約200nm的範圍內。
形成鰭結構之後，如圖4A和圖4B所示，橫向地部分地蝕刻第一半導體層20。在一些實施例中，相對於第二半導體層25，使用電漿乾蝕刻選擇性地蝕刻第一半導體層20，然後使用緩衝HF(Buffered HF)進行濕式清潔製程。在一些實施例中，電漿源氣體包括O2。在其它實施例中，濕蝕刻製程用於選擇性地蝕刻第一半導體層20。蝕刻液(蝕刻劑)包括NH4OH的水溶液、H2O2和H2O及/或H2SO4、H2O2和H2O的水溶液。在其它實施例中，濕式蝕刻劑包括氫氧化四甲銨(TMAH)溶液。在一些實施例中，使用緩衝HF進行額外的濕式清洗製程。在特定實施例中，電漿乾蝕刻和濕式蝕刻皆有使用。在一些實施例中，蝕刻量D1在約1nm至約10nm的範圍內，在一些實施例中，在約2nm至約5nm的範圍內。如圖4B所示，經蝕刻的第一半導體層20之橫截面的形狀具有狗骨形狀或線捲軸(或繞線管)形狀。
部分蝕刻第一半導體層20之後，在基板上形成包括一或多層絕緣材料的絕緣材料層，使得鰭結構30A和30B完全嵌入絕緣層中。絕緣層的絕緣材料可包括氧化矽， 氮化矽，氧氮化矽(SiON)，SiOCN，SiCN，氟矽玻璃(FSG)，或低介電常數介電材料，可由LPCVD(低壓化學氣相沉積)、電漿式化學氣相沉積或可流動式化學氣相沉積而形成。可以在形成絕緣層之後執行退火操作。接著，執行平坦化操作例如化學機械拋光(CMP)方法及/或回蝕方法，使得最上面的第二半導體層25之上表面從絕緣材料層暴露出來。
如圖5所示，在一些實施例中，在形成絕緣材料層之前，形成一或多個鰭襯墊層35。鰭襯墊層35由SiN或氮化矽基材料(例如，SiON，SiCN或SiOCN)製成。在一些實施例中，鰭襯墊層35包括形成第一鰭襯墊層35A於基板10與下鰭結構11的側面上，以及形成第二鰭襯墊層35B在第一鰭襯墊層35A上。在一些實施例中，每個襯墊層的厚度為約1nm和約20nm之間。在一些實施例中，第一鰭襯墊層35A包括氧化矽，並且具有在約0.5nm至約5nm之間的厚度，以及第二鰭襯墊層35B包括氮化矽，並且具有約0.5nm至約5nm之間的厚度。鰭襯墊層35可經由一或多個製程沉積而成，舉例來說，物理氣相沉積(PVD)、化學氣相沉積(CVD)或原子層沉積(ALD)，也可使用任何可接受的製程。
接著，如圖5所示。凹陷化絕緣材料層以形成隔離絕緣層40，使得鰭結構30的上部暴露出來。藉此操作，鰭結構30藉由隔離絕緣層40彼此電氣隔離，這也稱為淺溝槽隔離(STI)。在圖5所示的實施例中，凹陷化絕緣材料 層直到下鰭結構11的頂部暴露出來。第一半導體層20是犧牲層，隨後被部分地去除，以及第二半導體層25隨後形成GAA FET的通道層。在其他實施例中，在形成隔離絕緣層40之後，部分地蝕刻第一半導體層20。
如圖6A至圖6D所示，在形成隔離絕緣層40之後，在鰭結構30A和30B的上部上形成氧化物層45。圖6A繪示的立體圖，圖6B繪示沿X方向的橫剖面圖。圖6C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖6D繪示沿Y方向的切割鰭結構30B橫剖面圖。
在一些實施例中，藉由熱氧化製程氧化第一半導體層20和第二半導體層25以形成氧化物層45。在一些實施例中，熱氧化製程包括在O2及/或O3的氧化環境中進行。在特定實施例中，在一溫度下約800℃至約1000℃執行熱製程。在其它實施例中，使用濕氧化製程。在特定實施例中，執行化學氧化製程。
在一些實施例中，藉由熱氧化，第一半導體層20完全地被氧化成氧化物層45。在其他實施例中，保留第一半導體層20的一部分在鰭結構中。在一些實施例中，剩餘的第一半導體層20的寬度在約0.5nm至約2nm的範圍內。在一些實施例中，氧化物層45的厚度在約1nm至約5nm的範圍內。
當第一半導體層20由SiGe製成，並且第二半導體層25由Si製成時，氧化物層45包括在相應部分的矽-鍺氧化物部分和氧化矽部分。在一些實施例中，矽-鍺氧化物部 分主要設置在相鄰的第二半導體層25之間。在一些實施例中，氧化矽部分主要設置在第二半導體層25的側面上。
在一些實施例中，在形成氧化物層45之後，執行退火操作。在一些實施例中，在一溫度下約800℃至約1000℃執行退火製程。
如圖7A至圖7D所示，形成氧化物層45之後，形成犧牲閘極結構50在具有氧化物層45的鰭結構30A和30B上。圖7A繪示一立體圖，圖7B繪示沿X方向切割犧牲閘極結構的橫剖面圖。圖7C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖7D繪示沿Y方向切割鰭結構30B的橫剖面圖。
犧牲閘極結構50包括犧牲閘極電極層54。在一些實施例中，未形成犧牲閘極介電層。形成犧牲閘極結構50在鰭結構之一部分的上方，其將成為通道區域。犧牲閘極結構50界定GAA FET的通道區域。
形成犧牲閘極結構50，首先藉由在鰭結構30A和30B的上方以毯覆式沉積犧牲閘極電極層，使得鰭結構完全嵌入犧牲閘極電極層。犧牲閘極電極層包括矽，例如，多晶矽或非晶矽。在一些實施例中，犧牲閘極電極層的厚度在約100nm至約200nm的範圍內。在一些實施例中，犧牲閘極電極層經受平坦化操作。藉由化學氣相沉積(CVD)，包括低壓化學氣相沈積(LPCVD)、電漿增強化學氣相沉積(PECVD)、物理氣相沈積(PVD)、原子層沉積(ALD)、或其它合適的製程來沉積犧牲閘極電極層。隨後，在犧牲閘 極電極層上形成掩模層56。掩模層56包括一或多個氮化矽(SiN)層和氧化矽層。
接著，對掩模層執行圖案化操作以及將犧牲閘極電極層圖案化為犧牲閘極結構50，如圖7A至7D所示。犧牲閘極結構50包括犧牲閘極電極層54(例如，多晶矽)和掩模層56。
如圖7A至圖7D所示，藉由圖案化犧牲閘極結構，在犧牲閘極結構50的相對側上，部分地暴露出具有第二半導體層25的鰭結構之上部份以及氧化物層45，從而界定源極/汲極(S/D)區域。在本揭露中，源極和汲極可互換使用，並且其結構基本上相同。在圖7A至7D中，形成一個犧牲閘極結構50，但犧牲閘極結構的數量不限於一個。在特定實施例中，在Y方向上佈置兩個或更多的犧牲閘極結構。在特定實施例中，在犧牲閘極結構的兩側上形成一或多個虛設犧牲閘極結構，以改善圖案逼真度。
如圖8A至圖8D所示，形成犧牲閘極結構50之後，形成閘極側壁間隔物55。圖8A繪示一立體圖，圖8B繪示沿X方向切割犧牲閘極結構50的橫剖面圖。圖8C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖8D繪示沿Y方向C切割鰭結構30B的橫剖面圖。
為了形成閘極側壁間隔物55，藉由CVD或其他合適的方法保角地形成係為絕緣材料的毯覆層。以保角式方法沉積毯覆層，使得其在垂直表面上具有實質上相同的厚度，例如側壁，水平表面，和犧牲閘極結構的頂部。在一些 實施例中，沉積毯覆層至厚度為約2nm至約20nm。在一些實施例中，毯覆層的絕緣材料為氮化矽基材料，例如SiN，SiON，SiOCN或SiCN以及上述組合。在特定實施例中，絕緣材料是SiOC，SICON及SiCN中的一者。
更進一步，如圖8A至8D所示。在犧牲閘極結構的相對側壁上藉由異向蝕刻形成閘極側壁間隔物55。在形成毯覆層之後，對毯覆層執行異向蝕刻，例如，使用反應式離子蝕刻(RIE)。在異向蝕刻操作期間，從水平表面移除大部分的絕緣材料，留下介電隔離層在垂直表面上，例如，犧牲閘極結構的側壁及被暴露之鰭結構的側壁。掩模層56可從側壁間隔物暴露出。在一些實施例中，隨後可以執行等向蝕刻以去除暴露的鰭結構30之上部份的S/D區域的絕緣材料。
隨後，藉由適當的乾式及/或濕式蝕刻操作去除形成在源極/汲極區域中的第二半導體層25周圍的氧化物層45。
接著，如圖9A至9E所示，形成源極/汲極磊晶層60A和60B。圖9A繪示一立體圖，圖9B繪示沿X方向切割犧牲閘極結構50的橫剖面圖。圖9C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖9D繪示沿Y方向切割鰭結構30B和圖2的橫剖面圖。圖9E繪示沿X方向切割源極/汲極區域的橫剖面圖。
形成包裹在鰭結構30A的S/D區域之第二半導體層25周圍的第一S/D磊晶層60A。第一S/D磊晶層60A包 括用於p通道FET的一或多層的Si，SiGe和SiGeP。藉由CVD、ALD或分子束磊晶(MBE)的磊晶生長方法形成第一S/D磊晶層60A。在一些實施例中，第一S/D磊晶層60A包含硼(B)。形成包裹在鰭結構30B的S/D區域之第二半導體層第25周圍的第二S/D磊晶層60B。第二S/D磊晶層60B包括用於n通道FET的一或多層的Si，SiP，SiC和SiCP。藉由CVD、ALD或分子束磊晶(MBE)的磊晶生長方法形成第二S/D磊晶層60B。在一些實施例中，分別形成用於p通道FET的第一源極/汲極(S/D)磊晶層60A以及用於n通道FET的第二S/D磊晶層60B。
接著，如圖10A至圖10F所示，形成第一絕緣襯墊層63，然後形成層間介電質(ILD)層65，然後去除犧牲閘極結構50。圖10A繪示一立體圖。圖10B繪示沿X方向切割通道區域的橫剖面圖。圖10C繪示了沿Y方向切割鰭結構30A的橫剖面圖。圖10D繪示沿Y方向切割鰭結構30B的橫剖面圖。圖10E繪示沿X方向切割源極/汲極區域的橫剖面圖。圖10F繪示沿X方向切割閘極側壁間隔物55的橫剖面圖。
第一絕緣襯墊層63由氮化矽基材料製成，例如氮化矽，並且在隨後的蝕刻操作中作為第一接觸蝕刻停止層(CESL)。用於第一ILD層65的材料包括包含Si，O，C及/或H的化合物，如氧化矽，SICOH和SiOC。有機材料，例如聚合物，可用於第一ILD層65。形成第一ILD層65之後，執行平坦化操作，例如CMP，從而暴露犧牲閘極電極 層54。
接著，如圖10A至圖10F所示，去除犧牲閘極電極層54，並且進一步去除氧化物層45，從而暴露第二半導體層25(半導體奈米線)的通道區域。在去除犧牲閘極結構期間，第一ILD層65保護第一和第二S/D磊晶層60A及60B。可以使用電漿乾蝕刻及/或濕蝕刻去除犧牲閘極結構。當犧牲閘極電極層54為多晶矽且第一ILD層65為氧化矽，濕蝕刻劑例如TMAH溶液，可用於選擇性地去除犧牲閘極電極層54。隨後可以使用電漿乾蝕刻及/或濕蝕刻去除氧化物層45。
如圖10C，圖10D和圖10F所示，在一些實施例中，氧化物層45的一部分殘留在閘極側壁間隔物55之下，作為內側間隔。在一些實施例中，剩餘氧化物層45的厚度在約0.2nm至約2nm的範圍內。
如圖11A至圖11G所示，在暴露第二半導體層25的線之後，在鰭結構30A與鰭結構30B中的第二半導體層25之線的周圍形成閘極介電層104。圖11A繪示一立體圖。圖11B繪示沿X方向切割通道區域的橫剖面圖。圖11C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖11D繪示沿Y方向切割鰭結構30B中的橫剖面圖。圖11E繪示沿X方向切割源極/汲極區域的橫剖面圖。圖11F繪示沿X方向切割閘極側壁間隔物55的橫剖面圖。圖11G繪示通道區域的放大視圖。
在一些實施例中，閘極介電層104包括一或多個層的介電材料，例如氧化矽，氮化矽，或高k介電材料， 其他合適的介電材料，及/或上述組合。高k介電材料的實例包括HfO2，HfSiO，HfSiON，HfTaO，HfTiO，HfZrO，氧化鋯，氧化鋁，氧化鈦，二氧化鉿-氧化鋁(HfO2-Al2O3)合金，其他合適的高k值介電材料及/或其組合。在一些實施例中，在通道層和閘極介電層104之間形成界面層102。可以藉由CVD，ALD或任何合適的方法形成閘極介電層104。在一個實施例中，使用一個高度保角沉積製程形成閘極介電層104，例如ALD，以確保形成的閘極介電層具有圍繞每個通道的均勻厚度。在一個實施例中，閘極介電層104的厚度在約1nm至約6nm範圍內。
更進一步，在閘極介電層104上形成一個閘電極層108如圖11A至圖11G所示。在一些實施例中，在閘極介電層104上方形成一個閘電極層108以圍繞每個通道層。閘電極層108包括導電材料的一或多個層，例如多晶矽，鋁，銅，鈦，鉭，鎢，鈷，鉬，氮化鉭，矽化鎳，矽化鈷，TiN，WN，TiAl，TiAlN，TaCN，TaC，TaSiN，金屬合金，其他合適的材料及/或上述組合。可使用CVD、ALD、電鍍、或其他合適的方法形成閘電極層108。閘電極層也沉積在第一ILD層65的上表面上。形成閘極介電層和閘電極層在第一ILD層65上，然後使用平坦化，例如，CMP，直到第一ILD層65露出。
在特定實施例中，一或多個功函數調整層106設置在閘極介電層104和閘電極層108之間。功函數調整層106由導電材料製成，例如單層TiN，TaN，TaAlC，TiC， TaC，Co，Al，TiAl，HfTi，TiSi，TaSi或TiAlC，或者這些材料的兩層或更多層的複層。對於n通道FET，使用TaN，TaAlC，TiN，TiC，Co，TiAl，HfTi，TiSi和TaSi中的一或多者作為功函數調整層。可以藉由ALD，PVD，CVD，電子束蒸發或其他合適的製程形成功函數調整層106。再者，可使用不同的金屬層分別形成用於n通道FET和p通道FET的功函數調整層106。
隨後，在第一ILD層65上形成第二絕緣襯墊層110，並且在第二絕緣襯墊層110上形成第二ILD層115，如圖12A至圖12E所示。圖12A繪示一立體圖。圖12B繪示沿X方向切割通道區域的橫剖面圖。圖12C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖12D繪示沿Y方向切割鰭結構30B的橫剖面圖，以及圖12E繪示沿X方向切割源極/汲極區域的橫剖面圖。
第二絕緣襯墊層110由含矽氮化物的材料製成，例如氮化矽，並且在隨後的蝕刻操作用作第二CESL。用於第二ILD層115的材料包括Si，O，C及/或H的化合物，例如氧化矽，SiCOH和SiOC。有機材料例如聚合物，可以用於第二絕緣襯墊層110。在形成第二絕緣襯墊層110之後，執行平坦化操作，例如CMP。
接著，如圖12A至圖12E所示，形成接觸開口以分別暴露源極/汲極磊晶層60A和60B。接觸開口中填充有一或多個層的導電材料，從而形成S/D接觸。在接觸開口中和接觸開口上形成一或多層的導電材料，然後執行平坦化 操作，例如CMP操作，以形成S/D接觸。在一些實施例中，S/D接觸包括襯墊層122和主體層120。襯墊層122是阻擋層及/或膠(粘合)層。在一些實施例中，在源極/汲極磊晶層60A和60B上形成Ti層，並且在Ti層上形成TiN或TaN層，作為襯墊層122。主體層120包括一或多層Co，Ni，W，Ti，Ta，Cu和Al，或任何其他合適的材料。如圖12A與12E所示，S/D導電接觸分別環繞源極/汲極磊晶層60A和60B。
在一些實施例中，當第一半導體層由SiGe製成且第二半導體層由Si製成時，在閘極側壁間隔物55下方，氧化物層45包括矽-鍺氧化物部分和氧化矽部分。在一些實施例中，在閘極側壁間隔物55下方，矽-鍺氧化物部分主要設置在相鄰的第二半導體層25之間，並且氧化矽部分主要設置在第二半導體層25的側面上。
在一些實施例中，在閘極側壁間隔物下方，第二半導體層25具有橫截面，該橫截面具有兩個垂直側面，V形底側與反V形頂側。在其他實施例中，在閘極側壁間隔物下方，第二半導體層25具有橫截面，該橫截面具有兩個垂直側面，向上突出的頂側和向下突出的底側。在一些實施例中，在閘極側壁間隔物下方，第二半導體層25中最上面的一個具有橫截面，該橫截面具有兩個垂直側面，平坦的頂側和向下突出的底側。
應當理解的是，GAA FETs經歷進一步的互補式金氧半場效電晶體(CMOS)製程以形成各種特徵，例如接觸/通孔，互連金屬層，介電層，鈍化層等。
圖13A至圖16E繪示根據本揭露另一實施例之用於製造GAA FET元件的連續製程。應當理解，可以在圖13A至圖16E所示的過程之前，期間和之後提供附加操作。對於該方法的額外實施例，如下所述的部分之操作可以被替換或消除。操作/過程的順序可以是可互換的。
形成如圖9A至圖9E所示的結構之後，n通道區域包括被掩模層所覆蓋的鰭結構30A，掩模層可為，例如氮化矽層，以保護n通道區域。然後，類似於在圖10A至圖10E說明的操作，第二半導體層25在通道區域中暴露出來。圖13A繪示用於p通道FET的通道區域中之第二半導體層25的放大視圖。然後，如圖13B所示，在第二半導體層25上方形成第三半導體層26。在一些實施例中，第三半導體層由Si1-zGez製成，其中0.2
Figure 108138724-A0305-02-0024-7
z
Figure 108138724-A0305-02-0024-8
1.0。在其它實施例中，0.3
Figure 108138724-A0305-02-0024-9
z
Figure 108138724-A0305-02-0024-10
0.5。在一些實施例中，第三半導體層26的厚度在約0.2nm至約2nm的範圍內。
在形成第三半導體層26之後，執行熱製程以形成第二半導體層25(例如，Si)和第三半導體層26(例如，矽鍺)的合金半導體層27。合金半導體層27為Si1-wGew，其中0.3
Figure 108138724-A0305-02-0024-11
w
Figure 108138724-A0305-02-0024-12
0.7在一些實施例中，以及0.4
Figure 108138724-A0305-02-0024-13
z
Figure 108138724-A0305-02-0024-14
0.6在其它實施例中。在一些實施例中，在900℃至100C℃下執行熱製程。在一些實施例中，使用快速熱退火(RTA)。在特定實施例中，使用激光退火。
在一些實施例中，在熱製程之前，形成氧化物覆蓋層於第三半導體層26上，以及熱製程之後，去除氧化 物覆蓋層。
隨後，藉由蓋層保護具有合金半導體層27的p通道區域，然後加工n通道區域以暴露出通道區域中的第二半導體層25。接著，去除p通道區域的蓋層，從而獲得如圖14A至圖14F所示的結構。圖14A繪示一立體圖，圖14B繪示沿X方向切割通道區域的橫剖面圖。圖14C繪示沿Y方向的切割鰭結構30A的橫剖面圖。圖14D繪示沿Y方向切割鰭結構30B的橫剖面圖，圖14E繪示沿X方向切割源極/汲極區域的橫剖面圖。圖14F繪示沿X方向切割閘極側壁間隔物55的橫剖面圖。如圖14B至圖14F所示，在源極/汲極區域與閘極側壁間隔物下面，保留第二半導體層25。
如圖15A至圖15F所示，類似於圖11A至圖11G，第二半導體層25的線在p通道區域和n通道區域中暴露之後，在第二半導體層25的線之周圍形成閘極介電層104。圖15A繪示一立體圖。圖15B繪示沿X方向切割通道區域的橫剖面圖。圖15C繪示一個沿Y方向的切割鰭結構30A的橫剖面圖。圖15D繪示沿Y方向切割鰭結構30B的橫剖面圖，圖15E顯示沿X方向切割源極/汲極區域的橫剖面圖，以及圖15F繪示沿X方向切割閘極側壁間隔物55的橫剖面圖。
隨後，類似於圖12A至圖12E，如圖16A至圖16E所示，形成主體層120。圖16A繪示一立體圖。圖16B繪示沿X方向切割通道區域的橫剖面圖。圖16C繪示沿Y方向切割鰭結構30A的橫剖面圖，圖16D繪示沿Y方向切割鰭 結構30B的橫剖面圖，以及圖16E繪示沿X方向切割源極/汲極區域的橫剖面圖。
在一些實施例中，在閘極側壁間隔物55下方，氧化物層45環繞半導體線25的Si部分。
應當理解的是，GAA FETs經歷進一步的CMOS製程以形成各種特徵，例如接觸/通孔，互連金屬層，介電層，鈍化層等。
圖17A至圖19E繪示根據本揭露另一實施例的用於製造GAA FET元件的連續製程。應當理解，可以在圖17A至圖19E所示的製程之前，期間和之後提供額外操作。對於該方法的額外實施例，如下所述部分之操作可以被替換或消除。操作/過程的順序可以是可互換的。
形成如圖8A至8D所示的結構之後，如圖17A至圖17D所示，鰭結構的源極/汲極區域包括被移除的第二半導體層25和氧化物層45。圖17A繪示一立體圖。圖17B繪示沿X方向切割通道區域的橫剖面圖。圖17C繪示一個沿Y方向切割鰭結構30A的橫剖面圖。圖17D繪示沿Y方向切割鰭結構30B的橫剖面圖。
接著，如圖18A至圖18D所示，形成源極/汲極磊晶層62A和62B。圖18A繪示一立體圖，圖18B繪示沿X方向切割犧牲閘極結構50的橫剖面圖。圖18C繪示沿著Y方向切割鰭結構30A的橫剖面圖。圖18D繪示沿著Y方向切割鰭結構30B的橫剖面圖。
在鰭結構30A的S/D區域中之第二半導體層25 的端面(End faces)上形成第一S/D磊晶層62A。第一S/D磊晶層62A包括用於p通道FET的一或多個層的Si，SiGe和SiGeP。藉由CVD、ALD或分子束磊晶(MBE)的磊晶生長法形成第一S/D磊晶層62A。在一些實施例中，第一S/D磊晶層62A包含硼(B)。在鰭結構30B的S/D區域中之第二半導體層25的端面上形成第二S/D磊晶62B。第二S/D磊晶層62B包括用於n通道FET的一或多層的Si，SiP，SiC和SiCP。藉由CVD、ALD或分子束磊晶(MBE)的磊晶生長方法形成第二S/D磊晶層62B。在一些實施例中，分別形成用於p通道FET的第一源極/汲極(S/D)磊晶層62A以及用於n通道FET的第二S/D磊晶層62B。
隨後，藉由如圖10A至圖12E所示之相同或類似的操作，形成主體層120如圖19A至圖19E所示。圖19A繪示一立體圖。圖19B繪示沿X方向切割通道區域的橫剖面圖。圖19C繪示沿Y方向切割鰭結構30A的橫剖面圖。圖19D繪示沿Y方向切割鰭結構30B的橫剖面圖，圖19E繪示沿X方向切割源極/汲極區域的橫剖面圖。
應當理解的是，GAA FETs經歷進一步的CMOS製程以形成各種特徵，例如接觸/通孔，互連金屬層，介電層，鈍化層等。
圖20A至圖20D繪示閘極側壁間隔物55下方之鰭結構的各種結構。在一些實施例中，在第一半導體層20的氧化製程中，第一半導體層20未被完全氧化並且保留第一半導體層20的一部分。因此，在形成閘極結構之後，第 一半導體層20的剩餘部分存在閘極側壁間隔物55之下，如圖20A所示。氧化物層45連續地設置在第二半導體層25和剩餘的第一半導體層20的側面上。
在其他實施例中，當在閘極空間中去除氧化物層45時，實質上完全去除第二半導體層25之間的氧化物層。因此，如圖20B所示，在形成閘極結構之後，在閘極側壁間隔物55下方的第二半導體層之間形成氣隙29。氧化物層45非連續地設置在第二半導體層25的側面上。
再者，如圖20C所示，在一些實施例中，在氣隙填充一或多個介電材料。在特定實施例中，在第二半導體層25或合金半導體層27的上表面和下表面上形成界面層102，以及閘極介電層104填充在界面層102之間的空間如圖20C所示。在其他實施例中，如圖20D所示，界面層102連接相鄰的第二半導體層25，以及在界面層102上形成閘極介電層104。氧化物層45非連續地設置在第二半導體層25的側面上。
與現有製程相比，本文所描述各種實施例或示例提供了多種優點。例如，可以藉由自對準的方式形成內側間隔。此外，藉由單通道磊晶製程形成Si奈米線(nano-wire)通道和SiGe奈米線通道。因此，可以改善GAA FETs的性能並降低製造成本。
應當理解的是，並不是所有的優點都已經在本揭示內容中被討論，且對於所有的實施例也不需要特定的優點，並且其它實施例或示例可以提供不同的優點。
根據本揭露內容實施例，一種半導體元件的製造方法，形成鰭結構，具有下鰭結構及設置在下鰭結構上的上鰭結構。上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層。部分地蝕刻第一半導體層以減小第一半導體層的寬度。形成氧化物層在上鰭結構上。形成犧牲閘極結構在具有氧化物層的上鰭結構上。形成源極/汲極磊晶層在鰭結構的源極/汲極區域上。去除犧牲閘極結構以形成閘極空間。去除氧化物層以暴露閘極空間中的第二半導體層，以及形成閘極結構在閘極空間中的第二半導體層的周圍。在前述和以下實施例中的一或多個中，藉由熱氧化形成氧化物層。在前述和以下實施例中的一或多個中，在熱氧化之後，執行退火操作。在前述和以下實施例中的一或多個中，在800℃至1000℃下執行退火操作。在前述和以下實施例中的一或多個中，藉由熱氧化使經蝕刻的第一半導體層完全地氧化。在前述和以下實施例中的一或多個中，藉由熱氧化使經蝕刻的第一半導體層部分地氧化。在前述和以下實施例中的一或多個中，在閘極空間中去除氧化物層之後，在閘極空間中去除第一半導體層。在前述和以下實施例中的一或多個中，在形成源極/汲極磊晶層之前，去除源極/汲極區域中的氧化物層。在前述和以下實施例中的一或多個中，源極/汲極磊晶層環繞源極/汲極區域中的第二半導體層。在前述和以下實施例中的一或多個中，保留氧化物層的一部分在源極/汲極磊晶層與閘極結構之間。在前述和以下實施例中的一或多個中，在部分蝕刻第一半導體層之後，形成隔離絕緣層 在下鰭結構的周圍。在前述和以下實施例中的一或多個中，犧牲閘極結構包括犧牲閘極電極，以及犧牲閘極電極與氧化物層接觸。在前述和以下實施例中的一或多個中，第一半導體層由SiGe製成以及第二半導體層由Si製成。
根據本揭露內容實施例，一種半導體元件的製造方法，形成鰭結構，具有下鰭結構及設置在下鰭結構上的上鰭結構，上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層。部分地蝕刻第一半導體層以減小第一半導體層的寬度。形成氧化物層在上鰭結構上。形成犧牲閘極結構在具有氧化物層的上鰭結構上。在鰭結構的源極/汲極區域上形成源極/汲極磊晶層。去除犧牲閘極結構以形成閘極空間。去除閘極空間中的氧化物層以暴露閘極空間中的第二半導體層。在暴露的每個第二半導體層上形成第三半導體層。藉由混合第三半導體層和第二半導體層以形成多個通道線。以及形成閘極結構在閘極空間中的通道線的周圍。在前述和以下實施例中的一或多個中，第一半導體層由SiGe製成，第二半導體層由Si製成，以及第三半導體層由SiGe或Ge製成。在前述和以下實施例中的一或多個中，藉由熱氧化形成氧化物層。在前述和以下實施例中的一或多個中，藉由熱氧化使經蝕刻的第一半導體層完全地氧化。在前述和以下實施例中的一或多個中，保留氧化物層的一部分在源極/汲極磊晶層與閘極結構之間。
根據本揭露內容實施例，一種半導體元件的製造方法，形成鰭結構，具有下鰭結構及設置在下鰭結構上的 上鰭結構，上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層。部分地蝕刻第一半導體層以減小第一半導體層的寬度。形成氧化物層在上鰭結構上。形成犧牲閘極結構在具有氧化物層的上鰭結構上。在上鰭結構的源極/汲極區域，移除其未被犧牲閘極結構覆蓋之處。形成源極/汲極磊晶層以接觸第二半導體層。移除犧牲閘極結構以形成閘極空間。去除氧化物層以暴露閘極空間中的第二半導體層。形成閘極結構在閘極空間中的第二半導體層的周圍。在前述和以下實施例中的一或多個中，保留氧化物層的一部分在源極/汲極磊晶層與閘極結構之間。
根據本揭露內容實施例，一種半導體元件包含下鰭結構設置在基板上，多個半導體線設置在下鰭結構上，閘極結構設置在半導體線的通道區域上，多個閘極側壁間隔物設置在閘極結構之相對的側面上，以及源極/汲極磊晶層。與閘極側壁間隔物不同的材料製成的介電層，包裹在閘極側壁間隔物之下的半導體線。在前述和以下實施例中的一或多個中，閘極側壁間隔物由由氮化矽基材料製成，以及該介電層由Si和Ge中的至少一者的氧化物製成。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，至少一個半導體線具有兩個垂直側面，V形底面和倒V形頂面的橫截面。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，至少一個半導體線具有橫截面，該橫截面具有兩個垂直側面，向上突出的頂側和向下突出的底側。在前述和以下實施例中的一或多個中，半導體線中最上面的一個，具 有與剩餘的半導體線不同的橫截面。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，最上面的一個半導體線具有橫截面，該橫截面具有兩個垂直側面，平坦的頂側和向下突出的底側，其餘的是半導體線的橫截面具有兩個垂直側面，一個向上突出的頂側和一個向下突出的底側。在前述和以下實施例中的一或多個中，介電層設置在源極/汲極磊晶層和閘極結構的閘極介電層之間。在前述和以下實施例中的一或多個中，源極/汲極磊晶層包裹半導體線的源極/汲極區域。在前述和以下實施例中的一或多個中，源極/汲極磊晶層與半導體線的橫向端面接觸。在前述和以下實施例中的一或多個中，半導體線的通道區域由第一半導體材料製成，並且半導體線的源極/漏極區域由不同於第一半導體材料的第二半導體材料製成。在前述和以下實施例中的一或多個中，第一半導體材料是SiGe，第二半導體材料是Si。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，介電層包裹由第二材料製成的半導體線的一部分。在前述和以下實施例中的一或多個中，介電層包括矽-鍺氧化物部分和氧化矽部分。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，矽-鍺氧化物部分設置在相鄰的半導體線之間。在前述和以下實施例中的一或多個中，在閘極側壁間隔物下方，氧化矽部分設置在半導體線的側面上。
在另一例示性態樣中，一種半導體元件包括下鰭結構，設置在基板上，多個半導體線設置在下鰭結構上，閘極結構設置在半導體線的通道區域之上方，多個閘極側壁 間隔物設置在閘極結構之相對的側面上，以及源極/汲極磊晶層。與閘極側壁間隔物不同的材料製成的介電層，設置在閘極側壁間隔物之下的半導體線的側面上。在前述和以下實施例中的一或多個中，氣隙設置在閘極側壁間隔物下方的相鄰半導體線之間。在前述和以下實施例中的一或多個中，一或多層介電材料設置在閘極側壁間隔物下方的相鄰半導體線之間。在前述和以下實施例中的一或多個中，一或多層介電材料中的至少一層是高k介電材料。
根據本揭露的另一例示性態樣，一種半導體元件包括設置在基板下的鰭結構，多個半導體線設置在下鰭結構上，閘極結構設置在半導體線的通道區域上，多個閘極側壁間隔物設置在閘極結構的多個相對的側面上，以及源極/汲極磊晶層。與閘極側壁間隔物不同的材料製成的介電層，設置在閘極側壁間隔物下方的半導體線的側面上，以及與半導體線不同的半導體材料，設置在閘極側壁間隔物下方的相鄰半導體線之間。
前述內容概述了許多實施例或示例的特徵，使本技術領域中具有通常知識者可以從各方面更佳了解本揭露。本技術領域中具有通常知識者應可理解，且輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同的優點。本技術領域中具有通常知識者也應理解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神及範圍的情況下，可對本揭露進行各種改變，替換及變更。
10:基板
40:隔離絕緣層
54:犧牲閘極電極層
55:閘極側壁間隔物
56:掩模層
60A、60B:源極/汲極磊晶層

Claims (10)

  1. 一種半導體元件的製造方法，包括：形成一鰭結構，具有一下鰭結構以及設置在該下鰭結構上的一上鰭結構，該上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層；部分地蝕刻該些第一半導體層以減小該些第一半導體層的多個寬度；在部分地蝕刻該些第一半導體層後，形成一氧化物層在該上鰭結構上，其中該氧化物層形成自經蝕刻的該些第一半導體層的完全氧化和該些第二半導體層的氧化；形成一犧牲閘極結構在具有該氧化物層的該上鰭結構上；形成一源極/汲極磊晶層在該鰭結構的一源極/汲極區域上；去除該犧牲閘極結構以形成一閘極空間；去除該氧化物層以暴露該閘極空間中的該些第二半導體層；以及形成一閘極結構在該閘極空間中的該些第二半導體層的周圍。
  2. 如申請專利範圍第1項所述的方法，其中，在形成該源極/汲極磊晶層之前，去除該源極/汲極區域中的該氧化物層。
  3. 如申請專利範圍第2項所述的方法，其中 該源極/汲極磊晶層環繞該源極/汲極區域中的該些第二半導體層。
  4. 一種半導體元件的製造方法，包括：形成一鰭結構，具有一下鰭結構以及設置在該下鰭結構上的一上鰭結構，該上鰭結構包括交替堆疊的多個第一半導體層和多個第二半導體層；部分地蝕刻該些第一半導體層以減小該些第一半導體層的多個寬度；形成一氧化物層在該上鰭結構上；形成一犧牲閘極結構在具有該氧化物層的該上鰭結構上；形成一源極/汲極磊晶層在該鰭結構的一源極/汲極區域上；去除該犧牲閘極結構以形成一閘極空間；去除該閘極空間中的該氧化物層以暴露該閘極空間中的該些第二半導體層；形成一第三半導體層在每個暴露的該些第二半導體層上；藉由混合該些第三半導體層和該些第二半導體層形成多個通道線；以及形成一閘極結構在該閘極空間中的該些通道線的周圍。
  5. 如申請專利範圍第4項所述的方法，其中： 該些第一半導體層由SiGe製成；該些第二半導體層由Si製成；以及該第三半導體層由SiGe或Ge製成。
  6. 如申請專利範圍第4項所述的方法，其中藉由一熱氧化形成該氧化物層。
  7. 如申請專利範圍第6項所述的方法，其中藉由該熱氧化使經該蝕刻的該些第一半導體層完全地氧化。
  8. 如申請專利範圍第4項所述的方法，其中保留該氧化物層的一部分在該源極/汲極磊晶層與該閘極結構之間。
  9. 一種半導體元件，包括：一下鰭結構設置在一基板上；多個半導體線設置在該下鰭結構上；一閘極結構設置在該些半導體線的多個通道區域上；多個閘極側壁間隔物設置在該閘極結構之多個相對的側面上；以及一源極/汲極磊晶層；其中，一介電層由與該些閘極側壁間隔物不同的一材料製成，包裹在該些閘極側壁間隔物之下的該些半導體線的周圍； 其中在該些閘極側壁間隔物下方，該些半導體線中最上方的一者具有橫截面包括平坦的頂側和向下突出的底側，其餘的該些半導體線具有橫截面包括向上突出的頂側和向下突出的底側。
  10. 如申請專利範圍第9項所述的元件，其中該些閘極側壁間隔物由一氮化矽基材料製成，以及該介電層由Si和Ge中的至少一者的一氧化物製成。
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