TW201730956A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW201730956A
TW201730956A TW105124290A TW105124290A TW201730956A TW 201730956 A TW201730956 A TW 201730956A TW 105124290 A TW105124290 A TW 105124290A TW 105124290 A TW105124290 A TW 105124290A TW 201730956 A TW201730956 A TW 201730956A
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epitaxial
layer
fin
forming
epitaxial layers
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TW105124290A
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TWI637437B (zh
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彭成毅
江宏禮
楊玉麟
葉致鍇
育佳 楊
劉繼文
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台灣積體電路製造股份有限公司
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Abstract

提供了電晶體結構與電晶體結構之形成方法。此電晶體結構包括一第一磊晶材料與一第二磊晶材料之交替膜層。於部分實施例中，於一N型或P型電晶體中可移除此第一磊晶材料與第二磊晶材料之一。可移除第一磊晶材料與第二磊晶材料之一最底層，及可凹刻或凹蝕第一磊晶材料與第二磊晶材料之一的側壁。

Description

半導體裝置及其形成方法
本揭露是關於半導體裝置及其形成方法。更特別地，本揭露係關於如鰭型場效電晶體之半導體裝置及其形成方法。
半導體積體電路(integrated circuit，IC)工業已經歷快速成長。積體電路材料與設計上的技術演進已開創積體電路之不同世代，其中每一世代相較於前一世代，具有更小且更複雜之電路。在積體電路之演變過程中，通常功能性密度(即，每晶片面積所具有之內連元件數)已隨著特徵尺寸(即，使用製程所能製作之最小元件尺寸)之縮減而增加。
這些演進已增加處理與製造積體電路之複雜度。對於這些演進，積體電路之處理與製造亦相應發展。舉例來說，已導入了鰭型場效電晶體(FinFET)以取代平面型電晶體(planar transistor)。業已研發出了鰭型場效電晶體(FinFET)之結構及其製造方法。
依據一實施例，本揭露提供了一種半導體裝置之形成方法，包括：形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，該交替磊晶結構包括複數個磊晶 層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括第一半導體材料，而該些第二磊晶層包括第二半導體材料，該交替磊晶結構之該些膜層係交替該些第一磊晶層之一與該些第二磊晶層之一而形成；形成一第一介電層於該第一鰭與該第二鰭上；露出該第二鰭之一通道區；移除該第二鰭之該通道區內之該些第一磊晶層之至少一部；形成一第一閘極堆疊物於該第一鰭上，該第一閘極堆疊物沿該些第一磊晶層之側壁與該第一鰭之該些第二磊晶層延伸；以及形成一第二閘極堆疊物於該第二鰭上，該第二閘極堆疊物沿該些第二磊晶層之側壁延伸。
依據另一實施例，本揭露提供了一種半導體裝置之形成方法，包括：形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，此交替磊晶結構包括複數個磊晶層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括第一半導體材料，而該些第二磊晶層包括第二半導體材料，該交替磊晶結構之該些膜層係交替該些第一磊晶層之一與該些第二磊晶層之一而形成；選擇地蝕刻於該第一鰭之一第一通道區內之至少該些第一磊晶層之一之側壁；選擇地蝕刻於該第二鰭之一第二通道區內之至少該些第二磊晶層之一之側壁；形成一第一閘極堆疊物於該第一鰭上；及形成一第二閘極堆疊物於該第二鰭上。
依據又一實施例，本揭露提供了一種半導體裝置，包括：一基板；複數個第一源極/汲極區以及插入於該些第一源極/汲極區之間之一第一通道區，該些第一源極/汲極區 與該第一通道區包括了複數個第一磊晶層與複數個第二磊晶層的交替膜層；複數個第二源極/汲極區以及插入於該些第二源極/汲極區之間之一第二通道區，該些第二源極/汲極區與該第二通道區包括了該些第一磊晶層與該些第二磊晶層的交替膜層，該第二通道區包括了該第二磊晶層，其中於該第一磊晶層與該些第二源極/汲極區之間存有一缺口；一第一閘極電極，延伸於該第一通道區上；及一第二閘極電極，延伸於該第二通道區上。
100‧‧‧基板
102‧‧‧交替磊晶層結構
102a‧‧‧第一磊晶層
102b‧‧‧第二磊晶層
206‧‧‧罩幕層
206a‧‧‧第一介電層
206b‧‧‧第二介電層
206c‧‧‧第三介電層
206d‧‧‧多晶矽層
206e‧‧‧先進圖案膜層
206f‧‧‧底抗反射塗層
310‧‧‧鰭
310a‧‧‧第一鰭
310b‧‧‧第二鰭
312‧‧‧溝槽
412‧‧‧淺溝槽隔離物
414‧‧‧襯層
414a‧‧‧第一襯層次層
414b‧‧‧第二襯層次層
618‧‧‧假閘極介電層
620‧‧‧假閘極電極層
622‧‧‧硬罩幕層
622a‧‧‧第一硬罩幕層
622b‧‧‧第二硬罩幕層
718‧‧‧假閘極介電層
720‧‧‧假閘極電極
726‧‧‧假閘極堆疊物
826‧‧‧間隔物層
828‧‧‧側壁間隔物
930‧‧‧第一源極/汲極區
932‧‧‧第二源極/汲極區
1136‧‧‧層間介電層
1138‧‧‧保護層
1138a‧‧‧第一保護子層
1138b‧‧‧第二保護子層
1140‧‧‧保護層
1360‧‧‧圖案罩幕
2062‧‧‧保護罩幕
2264‧‧‧奈米線
2466‧‧‧中間層
2468‧‧‧閘極介電層
2470‧‧‧閘極電極
2568‧‧‧蝕刻停止層
2570‧‧‧第二層間介電層
2572‧‧‧接觸物
2574‧‧‧襯層
2674‧‧‧導電材料
2710‧‧‧應變鬆弛緩衝物
3072‧‧‧圖案罩幕
3080‧‧‧額外罩幕
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
W4‧‧‧寬度
第1-7、8A-8B、9-23、24A-24B、25-26圖顯示了依據部分實施例之於形成鰭型場效電晶體(FinFET)的中間階段的多個剖面圖與多個立體圖；第27A-27D圖顯示了依據部分實施例之N型場效電晶體之各種形態之立體圖；第28A-28D圖顯示了依據部分實施例之P型場效電晶體之各種形態之立體圖；第29A-29B圖顯示了依據部分實施例之N型場效電晶體之各種形態之立體圖；第30A-30G圖顯示了依據部分實施例之於場效電晶體之形成中之中間階段之剖面圖；第31A-31G圖顯示了依據部分實施例之N型場效電晶體之各種形態之立體圖；以及第32A-32D圖顯示了依據部分實施例之P型場效電晶體之 各種形態之立體圖。
為以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“較下部”、“上方”、“較上部”及類似的用語等。除了圖式所繪示的方位之外，空間相關用語用以涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
依據各個解說實施例，提供了具有全包覆閘極(Gate-All-Around，GAA)之鰭型場效電晶體(Fin Field-Effect Transistor，FinFETs)及其製造方法。繪示了形成鰭型場效電晶體的數個中間階段。亦討論了此些實施例的變化情形。於各圖 式與繪示實施例中，相同標號係代表相同元件。值得注意的是，基於繪示的目的，第1-26圖繪示了一P型鰭型場效電晶體與一N型鰭型場效電晶體的形成，其中P型鰭型場效電晶體呈現出一鰭樣結構(fin-like structure)與一多重閘極電極(multi-gate gate electrode)，而N型鰭型場效電晶體呈現出具有全包覆閘極電極(GAA electrode)之一奈米線樣結構(nanowire-like structure)。此些範例僅做為解說目的之用，而當使用不同材料時，本技術領域中具有通常知識者可以理解到N型鰭型場效電晶體可使用鰭樣結構(fin-like structure)而P型鰭型場效電晶體可採用奈米線樣結構(nanowire-like structure)。亦值得注意的是，繪示於第27A-32D圖內之多個實施例繪示了解說用之單一結構，而可結合在此描述之N型與P型結構而形成適用於不同材料類型與操作特徵之裝置。
第1-26圖顯示了依據部分實施例之採用相似材料於一基板上形成一P型鰭型場效電晶體(P type FinFET)與一N型鰭型場效電晶體(N type FinFET)的各個剖面圖與立體圖。請參照第1圖，提供了可為晶圓之一部之一基板100與一交替磊晶層結構102之剖面圖。於部分實施例中，基板100包括結晶態矽基板(例如晶圓)。基板100可依照設計需求(例如P型基板或N型基板)而包括各種摻雜區。於部分實施例中，摻雜區可摻雜有P型或N型摻質。例如，摻雜區摻雜有如硼(boron)或二氟化硼(BF2)之P型摻質、如磷或砷之N型摻質、及/或其組合。於N型鰭型場效電晶體或P型鰭型場效電晶體中可設置此些摻雜區。
於其他之部分實施例中，基板100可由如鑽石或鍺 之其他適合之元素態半導體、如砷化鎵(gallium arsenic)、碳化矽(silicon carbide)、砷化銦(indium arsenide)或磷化銦(indium phosphide)之適合之化合物半導體、或如矽碳化鍺(silicon germanium carbide)、砷磷化鎵(gallium arsenic phosphide,GaAsP)或磷化鎵銦(gallium indium phosphide)之適合之合金半導體所製成。再者，基板100可包括一磊晶層，可經過應變及/或經施加應力以增進表現，及/或可包括絕緣層上有矽(SOI)結構。
交替磊晶層結構102係形成於基板100上。如下文中所詳述，將圖案化基板100與交替磊晶層結構102以形成延伸自基板100處之鰭(fin)。鰭將用於形成P型鰭型場效電晶體及/或N型鰭型場效電晶體之用。可自如N型鰭之具有一導電類型之鰭之通道區移除交替磊晶層之交替膜層之一，進而形成了延伸於源極/汲極區之間的奈米線結構。可利用此些交替膜層以於如P型鰭之另一導電類型之鰭內之通道區誘發應力。於此實施例中描述之實施例繪示了可用於形成具有全包覆閘極設計之奈米線結構之N型鰭型場效電晶體以及P型鰭型場效電晶體之受應力的交替膜層之製程與材料。然而，亦可選用其他材料，使得全包覆閘極奈米線結構可用於P型鰭型場效電晶體，而應變交替膜層可用於N型鰭型場效電晶體。
例如，於部分實施例中之交替磊晶層結構102可包括數個第一磊晶層102a與數個第二磊晶層102b的交替膜層(稱為交替膜層結構102)，其中交替磊晶層結構102可包括自單一膜層的第一磊晶層102a與第二磊晶層102b至數個(例如2、4、 6、或更多)膜層之單一膜層的第一磊晶層102a與第二磊晶層102b之任意數量之交替膜層。於一實施例中，奈米線可用於形成N型電晶體、第一磊晶層102a可為一矽鍺層，而第二磊晶層102b可為矽層，其中矽層可用於N型鰭型場效電晶體，而矽鍺層可做為通道區之用，而矽層可做為P型鰭型場效電晶體之應變物(stressor)。
於部分實施例中，矽鍺層係藉由採用了二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)、鍺甲烷(GeH4)、與氯化氫(HCl)、乙硼烷(B2H6)、或氫氣(H2)做為反應氣體於約400℃至約800℃之溫度下及約1托爾至約200托爾之壓力下施行之低溫化學氣相沉積(LPCVD)製程所形成。矽層係藉由採用二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)做為反應氣體於約400℃至約750℃之溫度下及約10托爾至約200托爾之壓力下施行之低溫化學氣相沉積製程所形成。於部分實施例中，第一磊晶層102a與第二磊晶層102b分別形成有約5奈米至約10奈米之厚度。如此之厚度允許了矽層釋放出壓縮應力(compressive stress)至矽鍺層，而不使得矽鍺層之表面變的鬆散，進而改善了P型鰭型場效電晶體的電性表現。如前所述，可重複此些製程任意次數以得到對應於奈米線與通道區的數量之期望膜層數量。
依據部分實施例，第2圖繪示了於交替磊晶層結構102上形成一罩幕層206之後之裝置。舉例來說，罩幕層206可包括一第一介電層206a、一第二介電層206b、一第三介電層206c、一多晶矽層206d、一先進圖案膜層(advanced patterning film，APF)206e與一底抗反射塗層(bottom anti-reflective coating，BARC)206f，但是亦可能使用不同材料、膜層、膜層數量或相似物。一般來說，第一介電層206a、第二介電層206b與第三介電層206c係做為硬罩幕(hardmask)，而多晶矽層206d、先進圖案膜層206e與一底反射塗層206f的結合可用於圖案化硬罩幕以及做為特徵尺寸控制之用，以得到與控制如第一介電層206a、第二介電層206b與第三介電層206c之硬罩幕圖案化的期望尺寸。可調整各膜層的厚度，使得於各別蝕刻製程(於下討論)時各膜層具有足夠厚度以保護下方的材料。以下所提供的材料係做為範例之用，而非用以限定本揭露。
可沉積第一介電層206a於交替磊晶層結構102上。第一介電層206a可由一或多個適合的介電材料所形成，例如氧化矽、氮化矽、如摻碳氧化物之低介電常數(low-k)介電材料、如多孔性摻碳二氧化矽之極低介電常數(extremely low-k)介電材料、如聚亞醯胺之聚合物、上述材料之組合、或相似物。可藉由如化學氣相沉積、或旋塗玻璃製程之一製程沉積第一介電層206a，但是亦可使用一適當製程以形成厚度約20埃至約80埃之第一介電層206a。於部分實施例中，可使用第一介電層206a作為後續製程之蝕刻停止層(ESL)。
可沉積第二介電層206b於第一介電層206a上。第二介電層206b可採用如第一介電層206a之相似材料與相似方法所形成，但是第一介電層206a與第二介電層206b需不能為相同材料。於部分實施例中，第二介電層206b可具有約300埃至約500埃之厚度。
可沉積第三介電層206c於第二介電層206b上。可 使用第三介電層206c作為後續製程之一蝕刻停止層，且可採用如第一介電層206a與第二介電層206b之相似材料與相似製程而形成，但是第一介電層206a、第二介電層206b與第三介電層206c需不能為相同材料。於一實施例中，可形成厚度約300埃至約700埃之厚度之第三介電層206c。於部分實施例中，第一介電層206a、第二介電層206b與第三介電層206c可為單一介電層而非三個各別膜層。
於部分實施例中，第一介電層206a、第二介電層206b與第三介電層206c包括了氧化物-氮化物-氧化物(ONO)層，其中第一介電層206a係為氧化物(例如氧化矽)、第二介電層206b為氮化物(例如氮化矽)、而第三介電層206c為氧化物(例如氧化矽)。
可藉由化學氣相沉積法以沉積介於約50埃至約500埃之範圍內之一厚度而形成多晶矽層206d。先進圖案膜層206e可包括由化學氣相沉積製程形成之非晶碳(amorphous carbon)，但亦可採用其他適當材料與方法而形成。於部分實施例中，先進圖案膜層206e形成具有介於約50埃至約250埃之厚度。亦可使用其他厚度與材料。
可形成底抗反射塗層206f於先進圖案膜層206e上幫助後續微影製程，以圖案化一上方膜層(未顯示)，例如圖案化阻劑層。底抗反射塗層206f可包括氮氧化矽(SiON)、聚合物、相似物、或其組合，且可藉由化學氣相沉積、旋塗製程、相似方法、或其組合所形成。底抗反射塗層206f具有足以提供基於材料與波長之足夠抗反射量之厚度。於一實施例中，底抗 反射塗層206f形成有約100埃至約2000埃之厚度。
依據部分實施例，第3圖繪示於施行一圖案化製程以形成數個溝槽後之裝置。於部分實施例中，可使用微影技術以圖案化罩幕層206。通常，沉積阻劑材料(未顯示)於罩幕層206上。照射如光之射線穿透圖案化光罩至阻劑材料，以誘發暴露於能量下之阻劑材料的數個部分的反應。顯影阻劑材料以移除阻劑材料的一部，其中剩餘的阻劑材料保護了下方膜層免於受到如蝕刻之後續步驟的影響。
如第3圖所示，圖案化製程形成了穿透交替磊晶層結構102並進入基板100內之數個溝槽312。交替磊晶層結構102與下方的基板100之剩餘區域形成了如第一鰭310a與第二鰭310b之數個鰭(通稱為鰭310)。於下文中般所詳述，第一鰭310a將作為一P型鰭型場效電晶體之鰭而第二鰭310將作為一N型鰭型場效電晶體之奈米線(nanowire)。
請參照第4圖，依據部分實施例，於介於相鄰鰭310之間的溝槽312內形成淺溝槽隔離物(STI)412。於形成淺溝槽隔離物412之前，於基板100及鰭310的側壁上形成一或多個襯層(統稱為襯層414)。於部分實施例中，襯層414具有厚度介於約10埃至約50埃之單膜層結構。於其他實施例中，襯層414具有包含如第4圖所示之一第一襯層次層414a與一第二襯層次層414b之一雙層結構。於部分實施例中，第一襯層次層414a包括氧化矽且具有介於約5埃至約20埃之厚度，而第二襯層次層414b包括氮化矽且具有介於約5埃至約30埃之厚度。襯層414可藉由如物理氣相沉積、化學氣相沉積或原子層沉積之一或多個 製程沉積所形成，但亦可使用其他適當製程。可採用其他材料及/或製程。
淺溝槽隔離物412可由如氧化矽、氮化矽、氮氧化矽、摻雜氟矽酸玻璃(FSG)之介電材料、如氧化矽、氮化矽、如摻碳氧化物之低介電常數介電材料、如多孔性摻碳二氧化矽之極低介電常數介電材料、如聚亞醯胺之聚合物、上述材料之組合、或相似物所製成。於部分實施例，淺溝槽隔離物412可藉由如化學氣相沉積、流動型化學氣相沉積(flowable CVD)或旋塗玻璃製程之一製程所沉積，但亦可採用其他適當製程。接著，採用如蝕刻製程、化學機械研磨(CMP)或相似製程之製程以移除延伸於鰭310之頂部之上以及位於鰭310的頂面上之襯層414之數個部分。
依據部分實施例，第5圖繪示了凹蝕(recessing)淺溝槽隔離物412與襯層414以露出鰭310的側壁。於部分實施例中，利用鰭310作為蝕刻罩幕並採用一或多道選擇蝕刻製程而凹蝕淺溝槽隔離物412與襯層414。舉例來說，淺溝槽隔離物412與襯層414係採用單一蝕刻製程而凹蝕。於其他實施例中，淺溝槽隔離物412與襯層414係採用多重蝕刻製程而凹蝕。例如，採用鰭310與襯層414作為蝕刻罩幕而採用第一蝕刻製程凹蝕淺溝槽隔離物412，並接著採用第二蝕刻製程凹蝕襯層414。
凹蝕的深度係由交替磊晶層結構102之高度而決定。如下文中詳述，可移除第一磊晶層102a。如此，凹蝕的深度係露出最下方第一磊晶層102a，進而使得可採用一蝕刻而移除最下方以及其他第一磊晶層102a。
請參照第6圖，依據部分實施例，形成假閘極介電層618與假閘極電極層620於露出之鰭310上。接著將圖案化假閘極介電層618與假閘極電極層620以形成假閘極堆疊物，其將用於定義與形成源極/汲極區之用。接著將移除假閘極堆疊物，以允許針對通道區內之鰭的處理的施行，以及將於通道區上形成一閘極堆疊物。
於部分實施例中，假閘極介電層618係形成於露出的鰭310上。假閘極介電層618可藉由熱氧化法、化學氣相沉積法、濺鍍、或其他已知並用於形成假閘極介電層之方法而形成。於部分實施例中，假閘極介電層618可採用相同於淺溝槽隔離物412之材料所形成。於其他實施例中，假閘極介電層618可由如氧化矽、氮化矽之介電材料、如氧化矽、氮化矽、如摻碳氧化物之低介電常數介電材料、如多孔性摻碳二氧化矽之極低介電常數介電材料、如聚亞醯胺之聚合物、上述材料之組合、或相似物之一或多個適合介電所製成。於其他實施例中，假閘極介電層618包括具有如高於3.9之高介電常數介電材料。此些材料可包括氮化矽、氮氧化矽、如二氧化鉿(HfO2)、HfZrOx、HfSiOx、HfTiOx、HfAlOx之金屬氧化物、相似物或其組合與其多重膜層。
接著，形成假閘極電極層620於假閘極介電層618上。於部分實施例中，假閘極電極層620為一導電材料且可擇自由包括多晶矽、多晶矽鍺、金屬氮化物、金屬矽化物、金屬氧化物與金屬所組成族群。於一實施例中，假閘極電極層620可藉由物理氣相沉積、化學氣相沉積、濺鍍沉積或其他已知並 用於沉積導電材料之方法而形成。可使用導電或非導電之其他材料。假閘極電極層620通常具有一非平坦頂面且可於沉積後被平坦化。
如第6圖所示，形成一硬罩幕層622於假閘極電極層620上。硬罩幕層622包括一或多個罩幕層且將用於圖案化假閘極電極層620以形成假閘極電極之用。硬罩幕層622可包括一或多個圖案化層。於部分實施例中，硬罩幕層622可包括一第一硬罩幕層622a與一第二硬罩幕層622b。第一硬罩幕層622a可為氧化物層(例如氧化矽)，而第二硬罩幕層622b可為氮化物(例如氮化矽)。可藉由如化學氣相沉積或旋塗製程而沉積第一硬罩幕層622a與第二硬罩幕層622b，但亦可採用其他適當製程。第一硬罩幕層622a可具有約10埃至約50埃之厚度而第二硬罩幕層622b可具有約150埃至約850埃之厚度。第7圖顯示了圖案化假閘極電極層620與假閘極介電層618以形成假閘極電極720與假閘極介電層718。假閘極電極720與假閘極介電層718形成了一假閘極堆疊物726。
請參照第8A與8B圖，沉積一間隔物層826於假閘極堆疊物726、鰭310與淺溝槽隔離物412上。第8B圖繪示了如第8A圖內8B-8B線段之垂直於介於相鄰假閘極堆疊物726之間之源極/汲極區之一剖面圖。於部分實施例中，間隔物層826係由氮化矽所形成，且具有單膜層結構。於其他實施例中，間隔物層可具有包括數個膜層之一複合層。舉例來說，間隔物層可包括氧化矽層與位於氧化矽層上之氮化矽層。
依據部分實施例，請參照第9圖，圖案化間隔物層 826(參照第8A與8B圖)以形成沿著假閘極堆疊物726側壁之側壁間隔物828。於部分實施例中，可利用非等向性蝕刻以移除位於裝置之水平部上及沿著假閘極堆疊物726側壁上的間隔物層。如第9圖所示，基於位於裝置的水平部與沿著鰭310的側壁上的間隔物層826的厚度差異，間隔物826可殘留於假閘極堆疊物726的側壁上而露出了源極/汲極區內之鰭310。
依據部分實施例，第10圖繪示了分別沿著假閘極堆疊物726的相對側形成磊晶之第一源極/汲極區930與第二源極/汲極區932於第一鰭310a與第二鰭310b之露出部上。除了由交替磊晶層結構102所造成的應力外，於源極/汲極區採用磊晶成長材料使得源極/汲極區可於通道區內釋放應力。對於P型或N型鰭型場效電晶體，可改變用於第一源極/汲極區930與第二源極/汲極區932之材料，使得對N型鰭型場效電晶體可使用於通道區內施加拉伸應力之另一類材料，以及對P型鰭型場效電晶體可使用於通道區內施加壓縮應力之一類材料。例如，可使用磷化矽(SiP)或碳化矽(SiC)以形成N型鰭型場效電晶體，及可使用矽鍺(SiGe)與鍺(Ge)以形成P型鰭型場效電晶體。亦可使用其他材料。
於N型裝置與P型裝置使用不同材料之實施例中，較期望的為遮蔽其中之一(例如N型鰭)而形成磊晶材料於另一(例如P型鰭)上，以及重複此製程以形成另一材料。第一源極/汲極區930與第二源極/汲極區932可透過一佈植製程以佈植適當摻質或藉由於材料成長時而臨場摻雜摻質。於部分實施例中，第一源極/汲極區930係由矽鍺或摻雜硼之鍺所形成以形成 P型鰭型場效電晶體，而第二源極/汲極區932係由碳化矽或摻雜磷之磷化矽所形成以形成N型鰭型場效電晶體。
雖然第10圖僅繪示了位於假閘極堆疊物726一側之第一源極/汲極區930與第二源極/汲極區932，位於假閘極堆疊物之相對側上之第一源極/汲極區930與第二源極/汲極區932具有相似結構型態。
接著，請參照第11圖，形成第一層間介電層1136於第10圖所示結構上。值得注意的是，第1-10圖剖面係穿過源極/汲極區(除了另外提到的)所得到，以繪示源極/汲極區的形成。第11-25圖係關於通道區所施行的製程步驟，因此第11-25圖顯示了沿第10圖內之A-A線段之所得到的閘極電極。
於部分實施例中，可順應地沉積一保護層1138於第一源極/汲極區930與第二源極/汲極區932上以於後續形成穿透第一層間介電層1136至第一源極/汲極區930與第二源極/汲極區932之接觸物的形成時保護第一源極/汲極區930與第二源極/汲極區932。於部分實施例中，如第11圖所示，保護層1138包括具有一第一保護子層1138a與一第二保護子層1138b之一雙層結構。於部分實施例中，第一保護子層1138a包括氧化矽並具有介於約10埃至約30埃之厚度，而第二保護子層1138b包括氮化矽並具有介於約20埃至約60埃之厚度。保護層1138可藉由如物理氣相沉積、化學氣相沉積、或原子層沉積之一或多個製程而沉積，但亦可使用其他適當製程。可使用其他材料及/或製程。
於部分實施例中，第一層間介電層1136可包括氧 化矽、氮化矽、相似物、或其組合。第一層間介電層1136可由化學氣相沉積、高密度電漿、相似物或其組合所形成。接著，可平坦化第一層間介電層1136以大體與假閘極電極720之頂面共平面。於一實施例中，第一層間介電層1136係藉由如化學機械研磨以移除部分之第一層間介電層1136而平坦化。於其他實施例中，亦可使用例如蝕刻之其他平坦化技術。
於部分實施例中，於平坦化步驟後，凹蝕了第一層間介電層1136及沉積了保護層1140，而得到了如第11圖所示之結構。保護層1140可包括氮化矽，其於後續製程步驟中保護第一層間介電層1136與下方結構。
第12圖繪示了沿著假閘極電極720之第11圖內結構的剖面圖。為了方便解說，第12-23圖係採用剖面圖以較佳地與更清楚地繪示了通道區的製程。
依據部分實施例，第13圖繪示了於第二鰭310b上之一圖案罩幕1360的形成。如將於下文中所詳細討論，會分別地處理第一鰭310a與第二鰭310b的通道區。特別地，於部分實施例中，第一鰭310a將形成P型鰭型場效電晶體，而第一鰭310a係經過處理而薄化或凹蝕第二磊晶層102b，而第二鰭310b係經過處理以移除第一磊晶層102a。圖案罩幕1360可採用具有與下方膜層於蝕刻時表現出足夠蝕刻選擇率任何罩幕材料所形成。例如，於部分實施例中，圖案罩幕1360包括具有約10埃至約100埃之厚度之氮化矽膜層。於其他實施例中，圖案罩幕1360包括具有約5埃至約50埃之厚度之氧化矽，以及位於氧化矽上具有約5埃至約50埃厚度之氮化矽層。圖案罩幕1360可藉由如 物理氣相沉積、化學氣相沉積、或原子層沉積之一或多個製程所沉積，但可利用其他適當製程並藉由微影技術而圖案化。亦可採用其他材料及/或製程。
接著，於部分實施例中，如第14圖所示，施行一蝕刻製程以部分移除位於第一鰭310(例如用於P型裝置之鰭)上之假閘極電極720。於形成具有矽與矽鍺之交替層之P型裝置的實施例中，矽鍺層係做為於P型裝置中電流流通之通道區。如此，較佳地期望最上方膜層可為矽鍺(例如電流載子層)，進而允許了後續形成之上方閘極電極與最上方膜層的較佳交留，而於此些實施例中，較佳地移除第一鰭310a的頂層(例如為最上方第二磊晶層102b，於本範例中為矽)。例如，於交替磊晶層結構102包括用於第一磊晶層102a之矽鍺與用於第二磊晶層102b之矽的交替膜層之一實施例中，第一鰭310a之最上方層較佳地為一矽鍺層。
於一些實施例中，假閘極電極720係藉由對於假閘極電極720之材料有選擇性之一蝕刻製程所凹蝕。例如，當假閘極電極720包括多晶矽時，可使用採用三氟化氮(NF3)、六氟化硫(SF6)、氯氣(Cl2)、溴化氫(HBr)、相似物或其組合之一乾蝕刻、採用氫氧化銨(NH4OH)、四甲基氫氧化銨(TMAH)、相似物或其組合之一濕蝕刻以移除假閘極電極720。如第14圖所示，凹陷假閘極電極720至使得最上方第二磊晶層120b延伸高出凹口之底部之一深度。
依據部分實施例，第15圖繪示了位於最上方第二磊晶層102b上之假閘極介電層718的移除，而第16圖繪示了最 上方第二磊晶層102b的移除。於假閘極介電層718包括氧化矽的實施例中，可使用採用稀釋氫氟酸之濕蝕刻以移除假閘極介電層618的露出部分。於第二磊晶層102b包括矽之實施例中，可使用採用四甲基氫氧化銨(TMAH)溶液之濕蝕刻以移除第二磊晶層102b。亦可使用其他製程與材料。
依據部分實施例，第17圖繪示了於移除位於第一鰭310a上之剩餘假閘極電極720後之最終結構。可使用前述之蝕刻製程以移除位於第一鰭310a上之剩餘假閘極電極720。
依據部分實施例，請參照第18圖，沿著第一鰭310a的側壁移除假閘極介電層718(請參照第17圖)。如前所述，可薄化或凹蝕第二磊晶層102b。如此，移除假閘極介電層718以露出第二磊晶層102b。於假閘極介電層718包括氧化矽之實施例中，可使用採用稀釋氫氟酸之濕蝕刻以移除假閘極介電層718之露出部分。
依據部分實施例，第19圖繪示了凹蝕第一鰭310a內之第二磊晶層102b。於由矽鍺所形成之第一磊晶層102a及由矽形成之第二磊晶層102b的實施例中，可採用使用四甲基氫氧化銨(TMAH)溶液之濕蝕刻以移除第二磊晶層102b。亦可使用其他製程與材料。
可調整第一磊晶層102a之寬度W1及第二磊晶層102b之寬度W2，使得於第一磊晶層102a上可達成足夠的閘極控制以及自第二磊晶層102b施加於第一磊晶層102a之期望應力。於部分實施例中，第一磊晶層102a的寬度W1約5奈米至約10奈米，而第二磊晶層102b的寬度W2約1奈米至約7奈米。
依據部分實施例，請參照第20圖，第一鰭310a係為保護罩幕2062所保護。於第二鰭310b施行製程時，保護罩幕2062保護了第一鰭310a。於此範例中，第一鰭310a將形成具有磊晶材料之交替膜層的一P型鰭型場效電晶體，而將處理第二鰭310b以移除第一磊晶層102a以形成第二磊晶層102b之奈米線。於部分實施例中，保護罩幕2062為透過如化學氣相沉積、流動化學氣相沉積或旋塗玻璃製程所形成之氧化矽材料，但可採用任何適當製程。可選擇性地施行一化學機械研磨製程或其他平坦化製程以移除高於圖案罩幕1360之材料。亦可採用其他材料與製程。
接著，依據部分實施例，如第21圖所示，可移除圖案罩幕1360與假閘極電極720。於圖案罩幕1360包括氮化矽之部分實施例中，可採用磷酸移除圖案罩幕1360。可採用先前討論之相似製程移除假閘極電極720。
依據部分實施例，第22圖與第23圖繪示了之位於第二鰭310b上之假閘極介電層718的移除以及後續第一磊晶層102a的移除。假閘極介電層718的移除露出了第二鰭310b，進而允許了第一磊晶層102a的移除。可採用前述之移除位於第一鰭310a上之假閘極介電層718之相似製程與材料以移除位於第二鰭310b上之假閘極介電層718。
於第一磊晶層102a由矽鍺所形成及第二磊晶層102b由矽所形成之實施例中，可採用於蝕刻矽鍺較蝕刻矽為較高速率之蝕刻化學品之而移除第一磊晶層102a，例如過氧化氫混合物(APM)、硫酸過氧化物混合物(SPM)或相似物。此蝕刻 製程移除了第一磊晶層102a，進而形成了奈米線2264。
可選擇性地施行一圓滑化製程以得到如第23圖所示之圓滑化奈米線。此圓滑化製程可採用如熱氧化製程於約300℃至700℃溫度下之氧氣環境下及約0.5托爾至約20托爾之壓力下施行。可採用氫氟酸(HF)移除氧化物層以及於約250℃至約600℃及約1托爾至約100托爾之壓力的氫氣環境下回火以露出下方的半導體材料。於部分實施例中，早於移除第一磊晶層102a之前，第二磊晶層102b的寬度W3為約5奈米至約10奈米，而於圓滑化後之第二磊晶層102b的寬度W4為約1奈米至約7奈米。
依據部分實施例，第24A與24B圖繪示了沿第一鰭310a與奈米線2264的表面形成之一中間層2466。第24A為立體圖而第24B圖為沿第24A圖內24B-24B線段之剖面圖。中間層2466幫助了後續形成之高介電常數介電層與下方半導體材料之間的緩衝。於部分實施例中，中間層2466為可由化學反應所形成之二氧化矽化學品。例如，採用去離子水+臭氧、過氧化氫混合物(APM)或其他方法可形成氧化物化學品。其他實施例中間層2466可使用不同材料或製程。於一實施例中，中間層2466具有約3埃至約7埃之厚度。
於中間層2466上形成一閘極介電層2468。於一實施例中，閘極介電層2468包括一或多個高介電常數介電層(例如具有大於3.9之介電常數)。例如，此一或多個閘極介電層可包括一或多個金屬氧化物、鉿、鋁、鋯之矽酸鹽、其組合及其多重膜層。其他適當材料包括了鑭、鎂、鈀、鈦、鉛、鋯之金 屬氧化物、金屬合金氧化物或其組合。示例性範例包括了MgOx,BaTixOy,BaSrxTiyOz,PbTixOy,PbZrxTiyOz，及相似物。閘極介電層2468之形成方法包括了分子束沉積、原子層沉積、物理氣相沉積、或相似方法。於一實施例中，閘極介電層2468可具有約3埃至約30埃之厚度。
第24A圖和第24B圖繪示了形成於閘極介電層2468上之閘極電極2470。閘極電極2470可為擇自由鈦、銀、鋁、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)與鋯(Zr)所組成族群之金屬。於另一實施例中，閘極電極2470可包括擇自由氮化鈦、氮化鎢、氮化鉭、與釕所組成族群之一金屬。於本實施例中，閘極電極2470可採用如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍或其組合之一適當製程所形成。可施行如化學機械研磨製程之一平坦化製程以去除過量材料。
於第25、26圖中，形成如一蝕刻停止層2568與第二層間介電層2570之一或多個介電層於結構上，以及形成穿透多個介電層至多個元件之接觸物2572。第二層間介電層2570可包括藉由如化學氣相沉積、電漿加強型化學氣相沉積、旋塗、相似物或其組合之一適當方法所形成之氧化矽、四乙基矽甲烷(TEOS)、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟摻雜矽玻璃(FSG)、碳氧化矽、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其組成物、其結合或相似物。可施行如化學機械研磨之平坦化製程以平坦化第二層間介電層2570。
用於接觸物2572之開口可採用微影技術與一或多 個蝕刻步驟所形成。於開口內形成如擴散阻障層、黏著層、或相似物之一襯層2574，以及於開口內形成導電材料2674。襯層可包括由原子層沉積、化學氣相沉積或相似物所形成之鈦、氮化鈦、鉭、氮化鉭、或相似物。導電材料可包括由原子層沉積、化學氣相沉積、物理氣相沉積或相似物所形成之銅、銅合金、銀、金、鎢、鋁、鎳或相似物。可施行如化學機械研磨之平坦化製程以移除第二層間介電層2570之一表面上的過量材料。
於其他實施例中，N型鰭型場效電晶體及/或P型鰭型場效電晶體可利用不同之材料及/或形狀。舉例來說，第27A-27D圖顯示了不同於參照第1-26圖之前述討論之奈米線結構之用於N型場效電晶體之多個其他實施例，而第28A-28D圖顯示了不同於參照第1-26圖之前述討論之用於P型場效電晶體之多個其他實施例。值得注意的是，第27A-28D圖顯示了通道區與源極/汲極區之一立體圖。
繪示於第27A-28D圖內之實施例起始於相似於參照第1圖所示之前述製程，除了早於形成交替磊晶層結構102之前先形成一應變鬆弛緩衝物(strain relaxed buffer，SRB)2710，而交替磊晶層結構102係形成於應變鬆弛緩衝物2710上。於部分實施例中，應變鬆弛緩衝物2710包括矽0.75鍺0.25，且可為於約400℃至約800℃之溫度及約1托爾至約200托爾之一壓力下採用二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)、鍺甲烷(GeH4)及氯化氫、氫化硼(B2H6)或氫氣(H2)作為反應氣體而施行之低溫化學氣相沉積所成長。
接著，可形成交替磊晶層結構102於應變鬆弛緩衝 物2710上。於部分實施例中，第一磊晶層102a包括了於約400℃至約800℃之溫度及約1托爾至約200托爾之一壓力下採用二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)、鍺甲烷(GeH4)及氯化氫、氫化硼(B2H6)或氫氣(H2)作為反應氣體而施行之低溫化學氣相沉積所成長之矽0.5鍺0.5。第二磊晶層102b包括了矽，其可為於約400℃至約750℃之溫度及約10托爾至約200托爾之一壓力下採用二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)作為反應氣體而施行之低溫化學氣相沉積而成長。於此些實施例中，第二磊晶層102b具有較第一磊晶層102a為大的晶格常數，而第一磊晶層102a具有較應變鬆弛緩衝物2710為大的晶格常數。
對N型鰭型場效電晶體結構而言，矽層係作為介於源極與汲極之間電流流通之通道區之用，而矽0.5鍺0.5使得矽層處於拉伸應變(tensile strain)之下，從而增進了N型鰭型場效電晶體結構的效率。
對P型鰭型場效電晶體結構而言，矽0.5鍺0.5係作為介於源極與汲極之間電流流通之通道區之用，而矽層使得矽0.5鍺0.5處於壓縮應變(compressive strain)之下，從而增進了P型鰭型場效電晶體結構的效率。
可施行類似參照第2-9圖之前述討論製程，其中溝槽312(參見第3圖)可以至少部分地延伸到應變鬆弛緩衝物2710之內，且可以延伸到下方之基板100處。如前所述，可使用其他材料形成磊晶之第一源極/汲極區930與磊晶之第二源極/汲極區932。舉例來說，用於形成第27A-27D圖內N型鰭型場效電晶體結構之第二源極/汲極區932之材料可為矽鍺磷 (SiGeP)，其可藉由於約400℃至約800℃之溫度及約10托爾至約200托爾之一壓力下採用二氯矽甲烷(SiH2Cl2)或矽甲烷(SiH4)、鍺甲烷(GeH4)或Ge2H2Cl2與磷化氫(PH3)作為反應氣體之一低溫化學氣相沉積的施行所成長。用於形成第28A-28D圖內P型鰭型場效電晶體結構之第一源極/汲極區930之材料可為鍺錫(GeSn)，其可藉由於約400℃至約700℃之溫度及約10托爾至約200托爾之一壓力下採用鍺甲烷(GeH4)或氯化鋅(SnCl4)作為反應氣體之一低溫化學氣相沉積的施行所成長。接著，可施行相同於第11-26圖之前述製程，其中可使用下文中所描述蝕刻製程以得到期望的形狀。
繪示於第27A與28A圖內之實施例採用了具有相似形狀與尺寸的第一磊晶層102a與第二磊晶層102b。於其他實施例中，第一磊晶層102a與第二磊晶層102b可具有不同形狀。例如，第27B-27D圖繪示了採用了部分蝕刻之第一磊晶層102a之多個實施例，而第28B-28D圖繪示了採用了部分蝕刻之第二磊晶層102b之多個實施例。
請參照第27B圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可部分蝕刻第一磊晶層102a以於第一磊晶層102a的側壁內形成V型凹口。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(001)結晶方向以及沿側壁之(110)結晶方向。採用稀釋的過氧化氫混合物(APM)或硫酸過氧化物混合物(SPM)溶液於約5℃至約50℃蝕刻約5秒至約100秒而沿著(111)結晶方向選擇性蝕刻第一磊晶層102a，進而提供了具有(111)結晶方向之V型凹口。
請參照第27C圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可部分蝕刻第一磊晶層102a以於第一磊晶層102a的側壁內形成U型凹口。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(001)結晶方向以及沿側壁之(110)結晶方向。於約20℃至約50℃之溫度下及於約5托爾至約50托爾下施行採用氯化氫或氯氣之乾蝕刻約10秒至約100秒而選擇性蝕刻第一磊晶層102a，進而提供了具有(111)結晶方向之U型凹口。
請參照第27D圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可均勻地蝕刻第一磊晶層102a以於第一磊晶層102a的側壁內形成凹口或薄化第一磊晶層102a。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(100)結晶方向以及沿側壁之(111)結晶方向。採用過氧化氫混合物(APM)或硫酸過氧化物混合物(SPM)溶液於約5℃至約50℃蝕刻約5秒至約100秒而選擇性蝕刻第一磊晶層102a，進而提供了具有(111)結晶方向之凹陷表面。
請參照第28B圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可部分蝕刻第二磊晶層102b以於第二磊晶層102b的側壁內形成V型凹口。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(001)結晶方向以及沿側壁之(110)結晶方向。採用氫氧化銨(NH4OH)、四甲基氫氧化銨(TMAH)於約5℃至約50℃下蝕刻約5秒至約100秒而沿著(111)結晶方向選擇性蝕刻第二磊晶層102b，進而提供了具有(111)結晶方向之V型凹口。
請參照第28C圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可部分蝕刻第二磊晶層102b以於第二磊晶層102b的側壁內形成U型凹口。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(001)結晶方向而第一磊晶層102a表現出沿側壁之(110)結晶方向。於約20℃至約100℃之溫度下及於約5托爾至約50托爾下施行採用氯化氫或氯氣之乾蝕刻約10秒至約100秒而選擇性蝕刻第二磊晶層102b，進而提供了具有(111)結晶方向之U型凹口。
請參照第28D圖，於第一磊晶層102a為矽0.5鍺0.5與第二磊晶層102b為矽之實施例中，可均勻地蝕刻第一磊晶層102a以於第一磊晶層102a的側壁內形成凹口或薄化第一磊晶層102a。於本實施例中，第二磊晶層102b(例如矽層)表現出沿一頂面之(100)結晶方向而第一磊晶層102a表現出沿側壁之(111)結晶方向。採用氫氧化銨(NH4OH)、四甲基氫氧化銨(TMAH)於約5℃至約50℃蝕刻約5秒至約100秒而選擇性蝕刻第一磊晶層102a，進而提供了具有(111)結晶方向之凹陷表面。
依據部分實施例，第29A與29B圖繪示了於通道區內之交替磊晶層結構102的上方膜層與應變鬆弛緩衝物2710為分隔的。特別地，第29A圖繪示了完全地移除最下方第一磊晶層102a之一實施例，而第29B圖繪示了最下方第一磊晶層之中央部經過薄化直到交替磊晶層結構102之上方層與通道區內的應變鬆弛緩衝物2710完全分隔之一實施例。
舉例來說，於部分實施例中，當應變鬆弛緩衝物2710包括矽0.3鍺0.7時，第一磊晶層102a包括矽0.5鍺0.5，而第二 磊晶層102b包括鍺，較期望移除交替磊晶層結構102內之一或多個膜層，例如為第29A圖所示之最下方的第一磊晶層102a。當形成N型鰭型場效電晶體，此些實施例為特別有利。
於此實施例中，鍺材料較第一磊晶層102a與應變鬆弛緩衝物2710具有更大的晶格常數，而應變鬆弛緩衝物2710較第一磊晶層102a具有更大的晶格常數。於一N型裝置中，於通道區內矽0.5鍺0.5作為電子載子之用。移除最下方之第一磊晶層102a鬆散了相鄰之第二磊晶層102b(於繪示實施例中的鍺)，其結果為降低了壓縮應力或誘發於剩餘第二磊晶層102b內的拉伸應力。
依據部分實施例，第30A-30F圖繪示了移除最下方第一磊晶層102a之不同中間製程步驟。第30A-30F圖推論了相似於第1-26圖所討論之製程，其中相似符號代表了相同元件。請參照第30A，假設已施行了參照第1-4圖所討論的前述製程。第5圖繪示了淺溝槽隔離物412係經過凹蝕而使得最下方第一磊晶層102a為露出的之一實施例，而於第30A圖內所繪示之實施例中凹蝕了淺溝槽隔離物412而並未露出最下方之第一磊晶層102。
於部分實施例中，早於如參照第6圖之前述形成假閘極介電層618之前，可形成額外之一罩幕層3080於鰭上。此額外之罩幕層3080於移除最下方第一磊晶層102a之後續製程中提供了對於鰭310的額外保護。於此些實施例中，額外之罩幕層3080可為形成於鰭310上之結晶矽上蓋層或氮化矽層。
接著，可施行參照第6-21圖之前述製程。舉例來 說，第30C圖繪示了參照第6-21圖之形成假閘極電極720於鰭310上以及前述其他結構的形成。
依據部分實施例，第30D圖繪示採用一圖案罩幕3072以遮蔽P型之第一鰭310a。值得注意的是，第30A-30E圖繪示了P型第一鰭310a遮罩基於解說目的，但可以理解的是依照包括了參照第1-26圖所討論的製程之前述討論的其他製程中可凹蝕P型之第一鰭310a。於部分實施例中，可形成氮化矽之圖案罩幕，但亦可使用其他材料。
請參照第30E圖，移除假閘極電極720之露出部分以露出第二鰭310b與淺溝槽隔離物412的表面，而第30F圖繪示了凹蝕淺溝槽隔離物410以露出第二鰭310b之最下方第一磊晶層102a。如第30F圖所繪示，額外之罩幕層3080保護了交替磊晶層結構102內的上方膜層，而最下方第一磊晶層102a則未為罩幕層3080保護。如此，可蝕刻最下方的第一磊晶層102a以分隔交替磊晶層結構102的上方膜層與應變鬆弛緩衝物2710，進而鬆散或降低了交替磊晶層結構102之剩餘膜層的壓縮應力。依據部分實施例，第30G圖繪示了最下方之第一磊晶層102a的移除。
可採用任何適當製程移除最下方之第一磊晶層102a。舉例來說，可施行如參照第22圖之前述製程以如第29A圖所示完全移除了最下方磊晶層102a。於另一範例中，可施行如參照第27B圖之前述製程一較長時間以凹蝕最下方第一磊晶層102a的相對側壁直到如第29B圖所示般分隔交替磊晶層結構102與應變鬆弛緩衝物2710。
如第29A、29B圖所繪示之實施例可與如第27B-27D圖與第28B-28D圖所繪示實施例結合。舉例來說，第31A圖繪示了一實施例，其中如參照前述第29A圖般移除最下方第一磊晶層102a以及如參照前述第27B圖所示蝕刻剩餘第一磊晶層102a成V形側壁。同樣地，第31B圖繪示了一實施例，其中如參照前述第29A圖般移除最下方第一磊晶層102a以及如參照前述第27C圖所示般蝕刻剩餘第一磊晶層102a成U形側壁，而第31C圖繪示了一實施例，其中如參照前述第29A圖般移除最下方第一磊晶層102a以及如參照前述第27D圖所示般蝕刻剩餘第一磊晶層102a成凹口側壁。
於其他實施例中，第31D圖繪示了一實施例，其中參照前述第29B圖般切割最下方第一磊晶層102a以及如參照前述第27B圖般蝕刻剩餘第一磊晶層102a成V形側壁。相似地，第31E圖繪示了一實施例，其中如參照前述第29B圖般切割最下方的第一磊晶層102a，以及如參照前述第27C圖般蝕刻剩餘第一磊晶層102a成U形側壁，而第31F圖繪示了一實施例，其中如參照前述第29B圖般切割最下方的第一磊晶層102a，以及如參照前述第27D圖般蝕刻剩餘第一磊晶層102a成凹口側壁。
第31G繪示了結合了第1-26圖之元件之一實施例，其中移除所有的第一磊晶層102a，而第27A圖內交替磊晶層結構102內之元件係形成於應變鬆弛緩衝物2710上。可使用如前述描述與所顯示的相對製程。
依據部分實施例，第32A-32B繪示了可採用參照前述第29A與29B圖所示材料形成P型裝置之多個實施例。如前所 述，於部分實施例中，應變鬆弛緩衝物2710包括了矽0.3鍺0.7，第一磊晶層102a包括了矽0.5鍺0.5，以及第二磊晶層102b包括了鍺。於此些實施例中，P型鰭型場效電晶體之第一源極/汲極區可包括GeSn。請參照第32A圖，顯示了一實施例，其中保留所有第一磊晶層102a與第二磊晶層102b，而第一磊晶層102a與第二磊晶層102b的側壁都沒有經過薄化(例如V型、U型或切割)。於如此之實施例中，第二磊晶層102b之鍺材料可做為P型鰭型場效電晶體內之電洞載子且由於第一磊晶層102a之矽0.5鍺0.5與應變鬆弛緩衝物2710之矽0.3鍺0.7的較小晶格常數而將處於一壓縮應變下。
第32B-32D圖繪示了相似於第28B-28D圖之實施例，除了於第32B-32D圖內之第一磊晶層102a的側壁係經過薄化，而非如第28B-28D圖內之第二磊晶層102b的側壁。例如，第28B-28D圖繪示了第一磊晶層102a包括了矽0.5鍺0.5而第二磊晶層102b包括矽的實施例。於一P型裝置中，矽0.5鍺0.5扮演了電洞載子且由於第二磊晶層102b之矽材料較小的晶格常數而將處於壓縮應力下。於第30B-30D圖中，第二磊晶層102b的鍺材料作為電洞載子且由於第一磊晶層102a的矽0.5鍺0.5與應變鬆弛緩衝物2710的矽0.3鍺0.7的較小晶格常數而將處於壓縮應力下。因此，薄化第一磊晶層102a，進而改善第二磊晶層102b的閘極控制。可使用參照第28B圖內之第一磊晶層102a的矽0.5鍺0.5的相似製程以於第32B圖內之第一磊晶層102a的矽0.5鍺0.5內形成V型側壁。可使用參照第28C圖內之第一磊晶層102a的矽0.5鍺0.5的相似製程以於第32C圖內之第一磊晶層102a的矽0.5鍺 0.5內形成U型側壁。可使用參照第28D圖內之第一磊晶層102a的矽0.5鍺0.5的相似製程以於第32D圖內之第一磊晶層102a的矽0.5鍺0.5內形成凹陷或經切割之側壁。
可以理解的是，前述實施例在此藉由提供如奈米線結構以及與電流承載膜層的更大閘極交互作用而提供了較佳閘極及控制能力。例如，於通道區內的奈米線的形成實現了閘極完全包覆結構以及較佳的閘極控制。相似的，採用磊晶材料的交替膜層也實現了較佳的閘極控制。如此，相似材料可利用於通道區內的不同製程而應用於N型與P型裝置，進而降低關於不同磊晶層的成長之製造成本與製造時間。
再者，採用交替磊晶層結構102提供了元件裝置的改善。交替磊晶層結構102藉由插入交替應力層而避免或降低了應力鬆弛。藉由選擇材料使得應力(壓縮或拉伸)可作用至作為承載(例如電洞或電子)膜層上，於電流承載層的應力可控制於一較佳程度。
於一實施例中，提供了一種半導體裝置之形成方法。此方法包括形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，此交替磊晶結構含有複數個磊晶層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括一第一半導體材料，而該第二磊晶層包括一第二半導體材料，該交替磊晶結構之膜層係交替該些第一磊晶層之一與該些第二磊晶層之一。第一介電層係形成於該第一鰭與該第二鰭上，並露出該第二鰭之一通道區。此方法更包括移除該第二鰭之該通道區內之該些第一磊晶層之至少一部、形 成一第一閘極堆疊物於該第一鰭上，該第一閘極堆疊物沿該第一鰭之該些第一磊晶層與該些第第二磊晶層之數個側壁延伸、及形成一第二閘極堆疊物於該第二鰭上，該第二閘極堆疊物沿該些第二磊晶層之數個側壁延伸。
於另一實施例中，提供了一種半導體裝置之形成方法。此方法包括形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，此交替磊晶結構含有複數個磊晶層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括一第一半導體材料，而該第二磊晶層包括一第二半導體材料，該交替磊晶結構之膜層係交替該些第一磊晶層之一與該些第二磊晶層之一。選擇地蝕刻該第一鰭之該第一通道區內之至少該些第一磊晶層之一之數個側壁，及選擇地蝕刻於該第二鰭之該第二通道區內之至少該些第二磊晶層之一之數個側壁。形成一第一閘極堆疊物於該第一鰭上，及形成一第二閘極堆疊物於該第二鰭上。
於又一實施例中，提供了一種半導體裝置。此裝置包括一基板、複數個第一源極/汲極區以及設置於該些第一源極/汲極區之間之一第一通道區，該些第一源極/汲極區與該第一通道區包括了複數個第一磊晶層與複數個第二磊晶層的交替膜層，複數個第二源極/汲極區及設置於該些第二源極/汲極區之間之一第二通道區，該些第二源極/汲極區與該第二通道區包括了該些第一磊晶層與該些第二磊晶層的交替膜層，該第二通道區包括了該第二磊晶層，其中於該第一磊晶層與該些第二源極/汲極區之間存有一缺口。一第一閘極電極，延伸於 該第一通道區上，及一第二閘極電極，延伸於該第二通道區上。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基板
412‧‧‧淺溝槽隔離物
414‧‧‧襯層
414a‧‧‧第一襯層次層
414b‧‧‧第二襯層次層
828‧‧‧側壁間隔物
1136‧‧‧層間介電層
1138a‧‧‧第一保護子層
1138b‧‧‧第二保護子層
2466‧‧‧中間層
2468‧‧‧閘極介電層
2470‧‧‧閘極電極

Claims (10)

  1. 一種半導體裝置之形成方法，包括：形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，該交替磊晶結構包括複數個磊晶層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括第一半導體材料，而該些第二磊晶層包括第二半導體材料，該交替磊晶結構之該些膜層係交替該些第一磊晶層之一與該些第二磊晶層之一而形成；形成一第一介電層於該第一鰭與該第二鰭上；露出該第二鰭之一通道區；移除該第二鰭之該通道區內之該些第一磊晶層之至少一部；形成一第一閘極堆疊物於該第一鰭上，該第一閘極堆疊物沿該些第一磊晶層之側壁與該第一鰭之該些第二磊晶層延伸；以及形成一第二閘極堆疊物於該第二鰭上，該第二閘極堆疊物沿該些第二磊晶層之側壁延伸。
  2. 如申請專利範圍第1項所述之半導體裝置之形成方法，其中移除該些第一磊晶層之至少一部完全移除了介於該通道區之相鄰之該些第二磊晶層之間之該些第一磊晶層。
  3. 如申請專利範圍第1項所述之半導體裝置之形成方法，更包括：形成一應變鬆弛緩衝物於一基板上；形成該交替磊晶結構於該應變鬆弛緩衝物上；以及 形成數個溝槽於該交替磊晶結構內，該些溝槽至少部分地延伸進入該應變鬆弛緩衝物之內，其中該第一鰭與該第二鰭係插入於相鄰之該些溝槽內。
  4. 如申請專利範圍第1項所述之半導體裝置之形成方法，更包括：於形成該第一介電層之後，露出該第一鰭之該些第二磊晶層之一最上方第二磊晶層；以及移除該第一鰭之該些第二磊晶層之該最上方第二磊晶層，其中該第二閘極堆疊物延伸於該第一鰭之一最上方第一磊晶層之上。
  5. 一種半導體裝置之形成方法，包括：形成一第一鰭與一第二鰭，該第一鰭與該第二鰭各包括一交替磊晶結構，此交替磊晶結構包括複數個磊晶層，該些磊晶層包括複數個第一磊晶層與複數個第二磊晶層，該些第一磊晶層包括第一半導體材料，而該些第二磊晶層包括第二半導體材料，該交替磊晶結構之該些膜層係交替該些第一磊晶層之一與該些第二磊晶層之一而形成；選擇地蝕刻於該第一鰭之一第一通道區內之至少該些第一磊晶層之一之側壁；選擇地蝕刻於該第二鰭之一第二通道區內之至少該些第二磊晶層之一之側壁；形成一第一閘極堆疊物於該第一鰭上；以及形成一第二閘極堆疊物於該第二鰭上。
  6. 如申請專利範圍第5項所述之半導體裝置之形成方法，其中 選擇地蝕刻該第一通道區內之至少該些第一磊晶層之一之側壁完全移除了所有的該些第一磊晶層。
  7. 如申請專利範圍第5項所述之半導體裝置之形成方法，其中選擇地蝕刻該第一通道區內之至少該些第一磊晶層之一包括：移除於該第一通道區內之該些第一磊晶層內之一最下方第一磊晶層；以及選擇地蝕刻於該第一通道區內之剩餘的該些第一磊晶層之側壁。
  8. 如申請專利範圍第5項所述之半導體裝置之形成方法，更包括：形成一應變鬆弛緩衝物於一基板上；形成該交替磊晶結構於該應變鬆弛緩衝物上；以及形成數個溝槽於該交替磊晶結構內，該些溝槽至少部分地延伸進入該應變鬆弛緩衝物內，其中該第一鰭與該第二鰭係插入於相鄰之該些溝槽內。
  9. 如申請專利範圍第8項所述之半導體裝置之形成方法，其中選擇地蝕刻該第一通道區內之至少該些第一磊晶層之一之側壁包括形成穿透該第一鰭之一開口。
  10. 一種半導體裝置，包括：一基板；複數個第一源極/汲極區以及插入於該些第一源極/汲極區之間之一第一通道區，該些第一源極/汲極區與該第一通道區包括了複數個第一磊晶層與複數個第二磊晶層的交替膜 層；複數個第二源極/汲極區以及插入於該些第二源極/汲極區之間之一第二通道區，該些第二源極/汲極區與該第二通道區包括了該些第一磊晶層與該些第二磊晶層的交替膜層，該第二通道區包括了該第二磊晶層，其中於該第一磊晶層與該些第二源極/汲極區之間存有一缺口；一第一閘極電極，延伸於該第一通道區上；以及一第二閘極電極，延伸於該第二通道區上。
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US20170104061A1 (en) 2017-04-13
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US11309385B2 (en) 2022-04-19
US20180090570A1 (en) 2018-03-29
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