CN106571340B - 应变纳米线cmos器件和形成方法 - Google Patents
应变纳米线cmos器件和形成方法 Download PDFInfo
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- CN106571340B CN106571340B CN201610621501.0A CN201610621501A CN106571340B CN 106571340 B CN106571340 B CN 106571340B CN 201610621501 A CN201610621501 A CN 201610621501A CN 106571340 B CN106571340 B CN 106571340B
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Abstract
本发明提供了晶体管结构和晶体管结构的形成方法。晶体管结构包括第一外延材料和第二外延材料的交替层。在一些实施例中,对于一个n‑型或p‑型晶体管,可以去除第一外延材料或第二外延材料。可以去除第一外延材料和第二外延材料的最下的层,并且可以使第一外延材料或第二外延材料的侧壁缩进或凹进。本发明的实施例还涉及应变纳米线CMOS器件和形成方法。
Description
优先权声明和交叉引用
本申请要求2015年10月7日提交的标题为“应变纳米线CMOS设计和流量”的更早提交的临时申请美国专利申请第62/238,490号的权益,该申请结合于此作为参考。
技术领域
本发明的实施例涉及集成电路器件,更具体地,涉及应变纳米线CMOS器件和形成方法。
背景技术
集成电路(IC)材料和设计中的技术进步已经产生了多代IC,其中,每一代都比上一代具有更小和更复杂的电路。在IC演化过程中,功能密度(例如,每芯片面积的互连器件的数量)已经普遍增大,而几何尺寸已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。
这种按比例缩小也已经增加了处理和制造IC的复杂性,并且为了实现这些进步,需要IC处理和制造中的类似发展。例如,已经引进代替平面晶体管的鳍式场效应晶体管(FinFET)。正在发展FinFET的结构和制造FinFET的方法。
发明内容
本发明的实施例提供了一种形成半导体器件的方法,所述方法包括:形成第一鳍和第二鳍,每个所述第一鳍和每个所述第二鳍均包括交替外延结构,所述交替外延结构具有多个外延层,所述多个外延层包括第一外延层和第二外延层,所述第一外延层包括第一半导体材料,所述第二外延层包括第二半导体材料,所述交替外延结构的层在一个所述第一外延层和一个所述第二外延层之间交替;在所述第一鳍和所述第二鳍上方形成第一介电层;暴露所述第二鳍的沟道区域;去除所述第二鳍的所述沟道区域中的至少部分所述第一外延层;在所述第一鳍上方形成第一栅极堆叠件,所述第一栅极堆叠件沿着所述第一鳍的所述第一外延层的侧壁和所述第二外延层的侧壁延伸;以及在所述第二鳍上方形成第二栅极堆叠件,所述第二栅极堆叠件沿着所述第二外延层的侧壁延伸。
本发明的另一实施例提供了一种形成半导体器件的方法,所述方法包括:形成第一鳍和第二鳍,每个所述第一鳍和每个所述第二鳍均包括交替外延结构,所述交替外延结构具有多个外延层,所述多个外延层包括第一外延层和第二外延层,所述第一外延层包括第一半导体材料,所述第二外延层包括第二半导体材料,所述交替外延结构的层在一个所述第一外延层和一个所述第二外延层之间交替;选择性地蚀刻所述第一鳍的第一沟道区域中的至少一个所述第一外延层的侧壁;选择性地蚀刻所述第二鳍的第二沟道区域中的至少一个所述第二外延层的侧壁;在所述第一鳍上方形成第一栅极堆叠件;以及在所述第二鳍上方形成第二栅极堆叠件。
本发明的又一实施例提供了一种半导体器件,包括:衬底;第一源极/漏极区域和在所述第一源极/漏极区域之间插入的第一沟道区域,所述第一源极/漏极区域和所述第一沟道区域包括第一外延层和第二外延层的交替层;第二源极/漏极区域和在所述第二源极/漏极区域之间插入的第二沟道区域,所述第二源极/漏极区域包括所述第一外延层和所述第二外延层的所述交替层,所述第二沟道区域包括所述第二外延层,其中,在所述第二源极/漏极区域之间的所述第一外延层中存在间隙;第一栅电极,在所述第一沟道区域上方延伸;以及第二栅电极,在所述第二沟道区域上方延伸。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图26示出了根据一些实施例的FinFET的形成中的中间阶段的各个截面图和立体图;
图27A至图27D示出了根据一些实施例的用于n-型FinFET的各个配置的立体图;
图28A至图28D示出了根据一些实施例的用于p-型FinFET的各个配置的立体图;
图29A至图29B示出了根据一些实施例的用于n-型FinFET的各个配置的立体图;
图30A至图30G示出了根据一些实施例的FinFET的形成中的中间阶段的截面图;
图31A至图31G示出了根据一些实施例的用于n-型FinFET的各个配置的立体图;以及
图32A至图32D示出了根据一些实施例的用于p-型FinFET的各个配置的立体图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例,提供了具有全环栅(GAA)结构的鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。讨论了变化的实施例。贯穿各个视图和示例性实施例,相同的参考标号用于指定相同的元件。应该理解,虽然为了说明的目的,图1至图26示出了p-型FinFET和n-型FinFET的形成,其中,p-型FinFET显示了鳍式结构和多栅极栅电极并且n-型FinFET显示了具有GAA电极的纳米线式结构。这些提供的实例仅仅用于说明的目的并且本领域的普通技术人员应该意识到,当使用不同的材料时,n-型FinFET可以使用鳍式结构并且p-型FinFET可以使用纳米线式结构。同样,应该理解,为了说明的目的,图27A至图32D中示出的各个实施例示出了单个的结构,并且此处公开的各个n-型和p-型结构可以组合以形成设计为具有各种类型的材料和操作特性的器件。
图1至图26示出了根据一些实施例的使用类似的材料在衬底上形成p-型FinFET和n-型FinFET的截面图和立体图。首先参照图1,提供了衬底100和交替外延层结构102的截面图,衬底100可以是部分晶圆。在一些实施例中,衬底100包括晶体硅衬底(例如,晶圆)。依赖于设计需求(例如,p-型衬底或n-型衬底),衬底100可以包括各个掺杂的区域。在一些实施例中,掺杂的区域可以掺杂有p-型或n-型掺杂剂。例如,掺杂的区域可以掺杂有诸如硼或BF2的p-型掺杂剂;诸如磷或砷的n-型掺杂剂;和/或它们的组合。掺杂的区域可以配置为用于n-型FinFET或可选地配置为用于p-型FinFET。
在一些可选实施例中,衬底100可以由诸如金刚石或锗的一些其它的合适的元素半导体;诸如砷化镓、碳化硅、砷化铟或磷化铟的合适的化合物半导体;或诸如碳化硅锗、磷砷化镓或磷化镓铟的合适的合金半导体制成。此外,衬底100可以包括用于性能增强的应变的外延层(epi层)和/或可以包括绝缘体上硅(SOI)结构。
在衬底100上方形成交替外延层结构102。如下面更详细地解释,将图案化衬底100和交替外延层结构102以形成从衬底100延伸的鳍。进而使用该鳍形成p-型FinFET和/或n-型FinFET。可以从诸如n-型鳍的一种导电型的鳍的沟道区域去除交替的交替外延层,从而形成在源极和漏极区域之间延伸的纳米线结构。可以使用交替层对诸如p-型鳍的另一导电型的鳍的沟道区域施加应力。在这个实施例中描述的实施例示出了可以用于形成n-型FinFET的具有GAA设计的纳米线结构以及p-型FinFET的应力交替层的工艺和材料。然而,可以选择其它类型的材料,从而使得具有GAA的纳米线可以用于形成p-型FinFET并且应力交替层可以用于n-型FinFET。
例如,在一些实施例中,交替外延层结构102可以包括第一外延层102a和第二外延层102b的交替层(统称为交替外延层结构102),其中,交替外延层结构102可以包括从每个第一外延层102a和第二外延层102b的一层至每个第一外延层102a和第二外延层102b的许多层(例如,2、4、6或更多)的任何数量的交替层。在实施例中,其中,将形成用于n-型晶体管的纳米线,第一外延层102a可以是硅锗层并且第二外延层102b可以是硅层,其中,硅层将形成用于n-型FinFET的纳米线,并且硅锗层将用作沟道区域而硅层用作p-型FinFET的应力源。
在一些实施例中,使用SiH2Cl2或SiH4、GeH4和HCl、B2H6或H2作为反应气体,在约400℃至约800℃的温度下以及在约1托至约200托的压力下实施低压化学汽相沉积(LPCVD)工艺生长硅锗层。使用SiH2Cl2或SiH4作为反应气体,在约400℃至约750℃的温度下以及在约10托至约200托的压力下实施LPCVD工艺生长硅层。在一些实施例中,每个形成的第一外延层102a和第二外延层102b的厚度为从约5nm至约10nm。这样的厚度允许硅层向硅锗层施加压缩应力而不允许硅锗层的表面变得松弛,从而改进了p-型FinFET的电性能。如上所述,可以任意次数地重复这些工艺以获得对应于纳米线和沟道区域的数量的期望数量的层。
图2示出了根据一些实施例的在交替外延层结构102上方形成掩模层206之后的器件。例如,掩模层206可以包括第一介电层206a、第二介电层206b、第三介电层206c、多晶硅层206d、先进图案化膜(APF)206e和底部抗反射涂层(BARC)206f,但是可以使用不同的材料、层、层的数量等。一般地,第一介电层206a、第二介电层206b和第三介电层206c用作硬掩模,而多晶硅层206d、APF 206e和BARC 206f的组合将用于图案化硬掩模并且用于控制临界尺寸,以获得并且控制图案化的硬掩模(例如,第一介电层206a、第二介电层206b和第三介电层206c)的期望的尺寸。每层的厚度可以调整,从而使得每层在相应的蚀刻工艺(下述讨论的)期间具有足够的厚度保护下面的材料。例如,提供了以下材料作为实例并且并不意味着限制本发明。
可以在交替外延层结构102上方沉积第一介电层206a。第一介电层206a可以由诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物、这些的组合等的一种或多种合适的介电材料制成。可以通过诸如化学汽相沉积(CVD)或旋涂玻璃工艺的工艺沉积第一介电层206a,但是可以使用任何可接受的工艺形成厚度介于约至约之间的第一介电层206a。在一些实施例中,第一介电层206a可以用作随后工艺的蚀刻停止层(ESL)。
可以在第一介电层206a上方沉积第二介电层206b。第二介电层206b可以由与第一介电层206a类似的材料和类似的工艺形成,但是第一介电层206a和第二介电层206b不需要是相同的材料。在一些实施例中,形成的第二介电层206b的厚度介于约至约之间。
可以在第二介电层206b上方沉积第三介电层206c。第三介电层206c可以用作随后工艺的ESL并且可以由与第一介电层206a和第二介电层206b类似的材料和类似的工艺形成,但是第一介电层206a、第二介电层206b和第三介电层206c不需要是相同的材料。在实施例中,形成的第三介电层206c的厚度介于约至约之间。在一些实施例中,第一介电层206a、第二介电层206b和第三介电层206c可以是单介电层而不是三个分离的层。
在一些实施例中,第一介电层206a、第二介电层206b和第三介电层206c包括氧化物-氮化物-氧化物(ONO)层,其中,第一介电层206a是氧化物(例如,氧化硅)、第二介电层206b是氮化物(例如,氮化硅)并且第三介电层206c是氧化物(例如,氧化硅)。
可以通过LPCVD沉积多晶硅形成厚度在约至约的范围内的多晶硅层206d。APF 206e可以包括通过CVD工艺形成的无定形碳,但是可以可选地使用其它合适的材料和形成方法。在一些实施例中,形成的APF 206e的厚度介于约至约之间。可以使用其它的厚度和材料。
可以在APF 206e上方形成BARC 206f,有助于随后的光刻工艺图案化上面的层(诸如图案化的光刻胶层)(未示出)。BARC 206f可以包括SiON、聚合物等或它们的组合并且可以通过CVD、旋涂工艺等或它们的组合形成。BARC 206f具有足够的厚度以根据材料和波长提供足够的抗反射性质。在实施例中,形成的BARC层206f的厚度介于约至约之间。
图3示出了根据一些实施例的在实施图案化工艺形成沟槽312之后的器件。在一些实施例中,光刻技术用于图案化掩模层206。一般地,在掩模层206上方沉积光刻胶材料(未示出)。将光刻胶材料通过图案化的中间掩模辐照(暴露)于能量(例如,光),以引起暴露于能量的光刻胶材料的那些部分中的反应。显影光刻胶材料以去除部分光刻胶材料,其中,剩余的光刻胶材料保护下面的材料免受诸如蚀刻的随后的工艺步骤的损害。
如图3所示,图案化工艺形成了穿过交替外延层结构102并且至衬底100的沟槽312。交替外延层结构102和下面的衬底100的剩余的区域形成了鳍(诸如第一鳍310a和第二鳍310b(统称为鳍310))。如以下更详细地讨论的,第一鳍310a将用作p-型FinFET的鳍并且第二鳍310b将用于形成n-型FinFET的纳米线。
现在参照图4,根据一些实施例,在邻近的鳍310之间的沟槽312中形成浅沟槽隔离(STI)412。在形成STI 412之前,在衬底100和鳍310的侧壁上方形成一个或多个衬垫(统称为衬垫414)。在一些实施例中,衬垫414具有厚度介于约至约之间的单层结构。在其它实施例中,如图4示出的,衬垫414具有双层结构,该双层结构包括第一衬垫子层414a和第二衬垫子层414b。在一些实施例中,第一衬垫子层414a包括厚度介于约至约之间的氧化硅,并且第二衬垫子层414b包括厚度介于至约之间的氮化硅。可以通过诸如物理汽相沉积(PVD)、CVD或原子层沉积(ALD)的一个或多个工艺沉积衬垫414,但是可以使用任何可接受的工艺。可以使用其它的材料和/或工艺。
STI 412可以由诸如氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物、这些的组合等的合适的介电材料制成。在一些实施例中,可以通过诸如CVD、可流动CVD(FCVD)或旋涂玻璃工艺的工艺形成STI 412,但是可以使用任何可接受的工艺。随后,例如,使用蚀刻工艺、化学机械抛光(CMP)等去除鳍310的顶面上方延伸的部分STI 412和位于鳍310的顶面上方的部分衬垫414。
图5示出了根据一些实施例的使STI 412和衬垫414凹进以暴露鳍310的侧壁。在一些实施例中,使用鳍310作为蚀刻掩模,使用一个或多个选择性蚀刻工艺使STI 412和衬垫414凹进。例如,使用单个蚀刻工艺使STI412和衬垫414凹进。在可选实施例中,使用多个蚀刻工艺使STI 412和衬垫414凹进。例如,使用鳍310和衬垫414作为蚀刻掩模使用第一蚀刻工艺使STI 412凹进,并且随后,使用第二蚀刻工艺使衬垫414凹进。
凹槽的深度由交替外延层结构102的高度决定。如以下更详细的说明,将去除第一外延层102a。相应地,凹槽的深度是这样的:使得暴露最下的第一外延层102a,从而允许使用蚀刻工艺去除最下的以及其它的第一外延层102a。
参照图6,根据一些实施例,在暴露的鳍310上方形成伪栅极介电层618和伪栅电极层620。随后将图案化伪栅极介电层618和伪栅电极层620以形成将用于限定和形成源极/漏极区域的伪栅极堆叠件。之后,将去除伪栅极堆叠件以允许对沟道区域中的鳍实施处理,并且在沟道区域上方将形成栅极堆叠件。
在一些实施例中,在暴露的鳍310上方形成伪栅极介电层618。可以通过热氧化、CVD、溅射或任何用于形成伪栅极介电层的本领域中已知的其它的方法形成伪栅极介电层618。在一些实施例中,伪栅极介电层618可以由与STI 412相同的材料形成。在其它实施例中,伪栅极介电层618可以由诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物等或它们的组合的一种或多种合适的介电材料制成。在其它实施例中,例如,伪栅极介电层618包括具有大于3.9的高介电常数(k值)的介电材料。该材料可以包括氮化硅、氮氧化物、诸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx的金属氧化物等或它们的组合和它们的多层。
随后,在伪栅极介电层618上方形成伪栅电极层620。在一些实施例中,伪栅电极层620是导电材料并且可以从包括多晶硅(多晶Si)、多晶硅锗(多晶SiGe)、金属氮化物、金属硅化物、金属氧化物和金属的组中选择。在实施例中,可以通过PVD、CVD、溅射沉积或用于沉积导电材料的本领域中已知的其它技术沉积伪栅电极层620。可以使用导电和非导电的其它材料。伪栅电极层620的顶面通常具有非平坦的顶面并且可以在沉积之后平坦化。
图6也示出了在伪栅电极层620上方形成的硬掩模层622。硬掩模层622包括一个或多个掩模层并且将用于图案化伪栅电极层620以形成伪栅电极。硬掩模层622可以包括一个或多个图案化层。在一些实施例中,硬掩模层622包括第一硬掩模层622a和第二硬掩模层622b。第一硬掩模层622a可以是氧化物层(例如,氧化硅)并且第二硬掩模层622b可以是氮化物(例如,氮化硅)。可以通过诸如CVD或旋涂玻璃工艺的工艺沉积第一硬掩模层622a和第二硬掩模层622b,但是可以使用任何可接受的工艺。第一硬掩模层622a的厚度为从约至约并且第二硬掩模层622b的厚度为从约至约图7示出了图案化伪栅电极层620和伪栅极介电层618以形成伪栅电极720和伪栅极电介质718。伪栅电极720和伪栅极电介质718共同形成了伪栅极堆叠件726。
现在参照图8A和图8B,在伪栅极堆叠件726、鳍310和STI 412上方沉积间隔件层826。图8B示出了如由图8A中的8B-8B线示出的垂直于邻近的伪栅极堆叠件726之间的源极/漏极区域的截面图。在一些实施例中,间隔件层826由氮化硅形成并且可以具有单层结构。在可选实施例中,间隔件层可以具有包括多个层的组合结构。例如,间隔件层可以包括氧化硅层和氧化硅层上方的氮化硅层。
现在参照图9,根据一些实施例,图案化间隔件层826(见图8A和图8B)以沿着伪栅极堆叠件726的侧壁形成侧壁间隔件828。在一些实施例中,使用各向异性蚀刻工艺去除器件的水平部分上方和沿着伪栅极堆叠件726的侧壁的间隔件层。如图9示出的,由于器件的水平部分上方和沿着鳍310的侧壁上方的间隔件层826的厚度的不同,因此沿着伪栅极堆叠件726的侧壁的间隔件层826保留而鳍310暴露在源极/漏极区域中。
图10示出了根据一些实施例的分别沿着伪栅极堆叠件726的相对侧的,在第一鳍310a和第二鳍310b的暴露的部分上形成的外延的第一源极/漏极区域930和第二源极/漏极区域932。,除了由交替外延层结构102引起的应力之外,在源极/漏极区域中使用外延生长材料允许源极/漏极区域对沟道区域施加应力。对于n-型和p-型FinFET,可以改变用于第一源极/漏极区域930和第二源极/漏极区域932的材料,从而使得用于n-型FinFET的一种类型的材料对沟道区域施加拉伸应力,并且用于p-型FinFET的另一类型的材料施加压缩应力。例如,SiP或SiC可以用于形成n-型FinFET,以及SiGe或Ge可以用于形成p-型FinFET。可以使用其它的材料。
在实施例中,其中,不同的材料用于n-型器件和p-型器件,掩蔽一个(例如,n-型鳍)而在另一个(例如,p-型鳍)上形成外延材料是期望的,并且对另一个重复该工艺。第一源极/漏极区域930和第二源极/漏极区域932可以通过注入工艺注入适当的掺杂剂或通过在生长材料时原位掺杂来掺杂。在一些实施例中,第一源极/漏极区域930由掺杂有硼(B)的SiGe或Ge形成以形成p-型FinFET器件,并且第二源极/漏极区域932由掺杂有磷(P)的SiC或SiP形成以形成n-型FinFET器件。
虽然图10仅示出了位于伪栅极堆叠件726的一侧上的第一源极/漏极区域930和第二源极/漏极区域932,位于伪栅极堆叠件的相对侧上的第一源极/漏极区域930和第二源极/漏极区域932具有类似的结构配置。
下一步,如图11所示,在图10示出的结构上方形成第一层间电介质(ILD)1136。应该注意,图1至图10的截面图穿过源极/漏极区域截取(除了其它注意的地方之外)以示出源极/漏极区域的形成。图11至图25直接朝向对沟道区域实施的工艺步骤,并且由此,图11至图25是沿着图10中的A-A线示出的栅电极截取的。
在一些实施例中,可以在第一源极/漏极区域930和第二源极/漏极区域932上方共形地沉积保护层1138以在随后的穿过第一ILD 1136至第一源极/漏极区域930和第二源极/漏极区域932的接触件的形成期间保护第一源极/漏极区域930和第二源极/漏极区域932。在一些实施例中,如图11示出的,保护层1138具有包括第一保护子层1138a和第二保护子层1138b的双层结构。在一些实施例中,第一保护子层1138a包括氧化硅并且具有介于约至约之间的厚度,并且第二保护子层1138b包括氮化硅并且具有介于至约之间的厚度。可以通过诸如PVD、CVD或ALD的一个或多个工艺沉积保护层1138,但是可以使用任何可接受的工艺。可以使用其它的材料和/或工艺。
在一些实施例中,第一ILD 1136可以包括氧化硅、氮化硅等或它们的组合。可以通过CVD、高密度等离子体(HDP)等或它们的组合形成第一ILD 1136。随后可以平坦化第一ILD1136至与伪栅电极720的顶面基本共面。在实施例中,例如,通过使用CMP平坦化第一ILD1136以去除部分第一ILD 1136。在其它实施例中,可以使用诸如蚀刻的其它平坦化技术。
在一些实施例中,使第一ILD 1136凹进,并且沉积保护层1140和随后进行平坦化步骤,产生图11示出的结构。保护层1140可以包括氮化硅(Si3N4),该氮化硅在随后的工艺步骤中保护第一ILD 1136和下面的结构。
图12示出了沿着伪栅电极720的图11中的结构的截面图。为了易于说明,图12至图23示出了截面图以更好和更清楚地说明沟道区域的处理。
图13示出了根据一些实施例的在第二鳍310b上方的图案化的掩模1360的形成。如以下将更详细地讨论的,将单独地处理第一鳍310a和第二鳍310b的沟道区域。具体地,在一些实施例中,第一鳍310a将形成p-型FinFET器件,并且处理第一鳍310a以削薄第二外延层120b或使第二外延层120b凹进,并且处理第二鳍310b以去除第一外延层120a。可以由显示足够的蚀刻选择性的任何合适的掩模材料形成图案化的掩模1360以在蚀刻工艺期间保护下面的层。例如,在一些实施例中,图案化的掩模1360包括厚度介于约至约之间的氮化硅层。在其它实施例中,图案化的掩模1360具有厚度介于约至约之间的氧化硅以及位于氧化硅层上方的厚度介于约至约之间的氮化硅层。可以通过诸如PVD、CVD或ALD的一个或多个工艺沉积图案化的掩模1360,但是可以使用任何可接受的工艺,并且使用光刻技术图案化。可以使用其它材料和/或工艺。
之后,根据一些实施例,如图14示出的,实施蚀刻工艺以部分地去除第一鳍310a(例如,用于p-型器件的鳍)上方的伪栅电极720。在实施例中,其中,形成了硅和硅锗的交替层的p-型器件,在p-型器件中,硅锗层用作电流流动的沟道区域。因此,将硅锗层(例如,载流层)用于最上层是期望的,从而允许随后形成的上面的栅电极与最上层更好地相互作用,并且在这些实施例中,去除第一鳍310a的顶层(例如,最上的第二外延层102b,在这个实例中是硅)是期望的。例如,在实施例中,其中,交替外延层结构102包括用于第一外延层102a的硅锗以及用于第二外延层102b的硅的交替层,第一鳍310a的最上层是硅锗层是期望的。
在一些实施例中,通过对伪栅电极720的材料具有选择性的蚀刻工艺使伪栅电极720凹进。例如,如果伪栅电极720包括多晶硅,则可以使用NF3、SF6、Cl2、HBr等或它们的组合的干蚀刻或使用NH4OH、四甲基氢氧化铵(TMAH)等或它们的组合的湿蚀刻以去除伪栅电极720。如图14示出的,使伪栅电极720凹进至一定的深度,从而使得最上的第二外延层102b在凹槽的底部之上延伸。
根据一些实施例,图15示出了最上的第二外延层102b上方的伪栅极电介质718的去除并且图16示出了最上的第二外延层102b的去除。在实施例中,其中,伪栅极电介质718包括氧化硅,可以使用稀释的HF酸的湿蚀刻去除伪栅极电介质718的暴露的部分。在实施例中,其中,第二外延层102b包括硅,可以使用四甲基氢氧化铵(TMAH)溶液的湿蚀刻去除第二外延层102b。可以使用其它的工艺和材料。
图17示出了根据一些实施例的在去除第一鳍310a上方的伪栅电极720的剩余物之后产生的结构。上述描述的蚀刻工艺可以用于去除第一鳍310a上方的伪栅电极720的剩余物。
现在参照图18,根据一些实施例,沿着第一鳍310a的侧壁去除伪栅极电介质718(见图17)。如上述讨论的,削薄第二外延层102b或使第二外延层102b凹进。相应地,去除伪栅极电介质718以暴露第二外延层102b。在实施例中,其中,伪栅极电介质718包括氧化硅,可以使用稀释的HF酸的湿蚀刻去除伪栅极电介质718的暴露的部分。
图19示出了根据一些实施例的第一鳍310a中的第二外延层102b的凹进。在实施例中,其中,第一外延层102a由硅锗形成并且第二外延层102b由硅形成,可以使用四甲基氢氧化铵(TMAH)溶液的湿蚀刻使第二外延层102b凹进。可以使用其它的工艺和材料。
可以调整第一外延层102a的宽度W1和第二外延层102b的宽度W2,从而使得在第一外延层102a上实现足够的栅极控制以及第二外延层102b对第一外延层102a施加期望的应力。在一些实施例中,第一外延层102a的宽度W1为从约5nm至约10nm,并且第二外延层102b的宽度W2为从约1nm至约7nm。
现在参照图20,根据一些实施例,由保护掩模2062保护第一鳍310a。在对第二鳍310b实施处理时,保护掩模2062保护第一鳍310a。在这个实例中,第一鳍310a将形成具有外延材料的交替层的p-型FinFET,而将处理第二鳍310b以去除第一外延层102a,从而形成第二外延层102b的纳米线。在一些实施例中,保护掩模2602是通过诸如CVD、可流动CVD(FCVD)或旋涂玻璃工艺的工艺形成的氧化硅材料,但是可以使用任何合适的工艺。可选择地,可以实施CMP工艺或其它的平坦化工艺以去除图案化的掩模1360上方的材料。可以使用其它的材料和工艺。
之后,如图21示出的,根据一些实施例,可以去除第二鳍310b上方的图案化的掩模1360和伪栅电极720。在一些实施例中,其中,图案化的掩模1360包括氮化硅,可以使用H3PO4去除图案化的掩模1360。可以使用与上述讨论的类似的工艺去除伪栅电极720。
图22和图23示出了根据一些实施例的第二鳍310b上方的伪栅极电介质718的去除和随后的第一外延层102a的去除。伪栅极电介质718的去除暴露了第二鳍310b,从而允许第一外延层102a的去除。可以使用与上述讨论的去除第一鳍310a上方的伪栅极电介质718类似的工艺和材料去除第二鳍310b上方的伪栅极电介质718。
在实施例中,其中,第一外延层102a由硅锗形成并且第二外延层102b由硅形成,可以使用诸如NH4OH:H2O2:H2O(氨水过氧化氢混合物,APM)、H2SO4+H2O2(硫酸过氧化氢混合物,SPM)等的以比蚀刻硅更高的速率蚀刻硅锗的蚀刻剂去除第一外延层102a。该蚀刻工艺去除第一外延层102a,从而形成纳米线2264。
可选择地,如图23示出的,可以实施圆化工艺以获得圆化的、纳米线。例如,可以在O2的环境中在约300℃至约700℃的温度下和约0.5托至约20托的压力下使用热氧化工艺实施圆化工艺。可以在H2的周围下在从约250℃至约600℃的温度下和在从约1托至约100托的压力下使用HF或退火去除氧化层,以暴露下面的半导体材料。在一些实施例中,在去除第一外延层102a之前,第二外延层102b的宽度W3为从约5nm至约10nm,并且在圆化之后,第二外延层的宽度W4为从约1nm至约7nm。
图24A和图24B示出了根据一些实施例的沿着第一鳍310a和纳米线2264的表面形成的界面层2466的形成。图24A是立体图,并且图24B是沿着图24A的24B-24B线截取的截面图。界面层2466有助于缓冲随后形成的高k介电层和下面的半导体材料。在一些实施例中,界面层2466可以是由化学反应形成的化学氧化硅。例如,可以使用去离子水+臭氧(DIO3)、NH4OH+H2O2+H2O(APM)或其它方法形成化学氧化物。对于其它的实施例,界面层2466可以使用不同的材料或工艺。在实施例中,界面层2466具有约至约的厚度。
在界面层2466上形成栅极介电层2468。在实施例中,栅极介电层2468包括一个或多个高k介电层(例如,具有大于3.9的介电常数)。例如,一个或多个栅极介电层可以包括金属氧化物或Hf、Al、Zr的硅酸盐的一层或多层、它们的组合和它们的多层。其它合适的材料包括La、Mg、Ba、Ti、Pb、Zr、金属氧化物的形式、金属合金氧化物和它们的组合。示例性材料包括MgOx、BaTixOy、BaSrxTiyOz、PbTixOy、PbZrxTiyOz等。栅极介电层2468的形成方法包括分子束沉积(MBD)、ALD、PVD等。在实施例中,栅极介电层2468可以具有约至约的厚度。
图24A和图24B还示出了在栅极介电层2468上方形成的栅电极2470。栅电极2470可以是从W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn和Zr的组中选择的金属。在可选实施例中,栅电极2470包括从TiN、WN、TaN和Ru的组中选择的金属。在本实施例中,栅电极2470的厚度在从约5nm至约100nm的范围内。可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的工艺形成栅电极2470。可以实施诸如CMP的平坦化工艺以去除过量的材料。
在图25至图26中,在结构上方形成诸如蚀刻停止层2568和第二ILD2570的一个或多个介电层,并且穿过各个介电层至各个组件形成接触件2572。第二ILD 2570可以包括通过诸如CVD、PECVD、旋涂等或它们的组合的任何合适的方法形成的氧化硅、TEOS、PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合材料、它们的组合等。可以实施诸如CMP的平坦化工艺以平坦化第二ILD 2570。
可以使用光刻技术和一个或多个蚀刻步骤形成用于接触件2572的开口。在开口中形成诸如扩散阻挡层、粘合层等的衬垫2574和导电材料2674。衬垫可以包括通过ALD、CVD等形成的钛、氮化钛、钽、氮化钽等。导电材料可以是通过ALD、CVD、PVD等形成的铜、铜合金、银、金、钨、铝、镍等。可以实施诸如CMP的平坦化工艺以从第二ILD 2570的表面去除过量的材料。
对于n-型FinFET和/或p-型FinFET的其它实施例,可以使用不同的材料和/或形状。例如,图27A至图27D示出了可以用于n-型FinFET的各个其它的实施例,不同于参照图1至图26的上述讨论的纳米线结构,并且图28A至图28D示出了可以用于参照图1至图26的上述讨论的p-型FinFET的各个其它的实施例。应该注意,图27A至如28D示出了沟道区域和源极/漏极区域的立体图。
诸如在图27A至图28D中示出的那些的实施例开始于与参照图1的上述讨论的那些类似的工艺,除了在形成交替外延层结构102之前,形成了应变弛豫缓冲(SRB)2710,并且在SRB 2710上方形成了交替外延结构102。在一些实施例中,SRB 2710包括Si0.75Ge0.25并且可以通过使用SiH2Cl2或SiH4、GeH4和HCl、B2H6或H2作为反应气体,在约400℃至约800℃的温度下以及在约1托至约200托的压力下实施的LPCVD工艺生长。
之后,可以在SBR 2710上方形成交替外延层结构102。在一些实施例中,第一外延层102a包括Si0.5Ge0.5,Si0.5Ge0.5通过使用SiH2Cl2或SiH4、GeH4和HCl、B2H6或H2作为反应气体,在约400℃至约800℃的温度下以及在约1托至约200托的压力下实施LPCVD工艺生长。第二外延层102b包括硅,该硅可以通过使用SiH2Cl2或SiH4作为反应气体,在约400℃至约750℃的温度下以及在约10托至约200托的压力下实施LPCVD工艺生长。在这些实施例中,第二外延层102b具有比第一外延层102a更大的晶格常数,第一外延层102a具有比SRB 2710更大的晶格常数。
对于n-型FinFET结构,硅层用作源极和漏极区域之间电流流动的沟道区域,并且Si0.5Ge0.5使Si层受到拉伸应变,从而增加了n-型FinFET结构的效率。
对于p-型FinFET结构,Si0.5Ge0.5层用作源极和漏极区域之间电流流动的沟道区域,并且Si层使Si0.5Ge0.5层受到压缩应变,从而增加了p-型FinFET结构的效率。
可以实施与参照图2至图9的上述讨论的那些类似的工艺,其中,沟槽312(见图3)可以至少部分地延伸至SRB 2710,并且可以延伸至下面的衬底100。如上所述,其它材料可以用于形成外延的第一源极/漏极区域930和外延的第二源极/漏极区域932。例如,用于形成图27A至图27D中的n-型FinFET器件的第二源极/漏极区域932的材料可以包括SiGeP,该材料可以通过使用SiH4或Si2H2Cl2、GeH4或Ge2H2Cl2和PH3(磷化氢)作为反应气体,在约400℃至约800℃的温度下以及在约10托至约200托的压力下实施LPCVD工艺生长。用于形成图28A至图28D中的p-型FinFET器件的第一源极/漏极区域930的材料可以包括GeSn,该材料可以通过使用GeH4、SnCl4作为反应气体,在约400℃至约700℃的温度下以及在约10托至约200托的压力下实施LPCVD工艺生长。之后,可以实施与参照图11至图26的上述讨论的类似的工艺,其中,使用以下描述的蚀刻工艺以获得期望的形状。
在图27A和图28A中示出的实施例使用了具有类似的形状和尺寸的第一外延层102a和第二外延层102b。在其它实施例中,第一外延层102a和第二外延层102b可以具有不同的形状。例如,图27B至图27D示出了使用部分地蚀刻的第一外延层102a的各个实施例,并且图28B至图28D示出了使用部分地蚀刻的第二外延层102b的各个实施例。
现在参照图27B,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以部分地蚀刻第一外延层102a以在第一外延层102a的侧壁中形成“V”形的凹槽。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(001)晶向以及沿着侧壁的(110)晶向。在约5℃至约50℃的温度下使用稀释的APM或SPM溶液约5秒至约100秒的蚀刻沿着(111)晶向选择性地蚀刻第一外延层102a,从而提供了具有(111)晶向的“V”形的凹槽。
现在参照图27C,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以部分地蚀刻第一外延层102a以在第一外延层102a的侧壁中形成“U”形的凹槽。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(001)晶向以及沿着侧壁的(110)晶向。在约5托至约50托的压力下以及在约20℃至约100℃的温度下使用HCl或Cl2气体实施约10秒至约100秒的干蚀刻工艺选择性地蚀刻第一外延层102a,从而提供了具有(111)晶向的“U”形的凹槽。
现在参照图27D,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以均匀地蚀刻第一外延层102a以在第一外延层102a的侧壁中形成凹槽。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(110)晶向以及沿着侧壁的(111)晶向。在约5℃至约50℃的温度下使用APM或SPM溶液约5秒至约100秒的蚀刻选择性地蚀刻第一外延层102a,从而提供了具有(111)晶向的凹进的表面。
现在参照图28B,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以部分地蚀刻第二外延层102b以在第二外延层102b的侧壁中形成“V”形的凹槽。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(001)晶向并且第二外延层102b显示了沿着侧壁的(110)晶向。在约5℃至约50℃的温度下使用TMAH或NH4OH约5秒至约100秒的蚀刻沿着(111)晶向选择性地蚀刻第二外延层102b,从而提供了具有(111)晶向的“V”形的凹槽。
现在参照图28C,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以部分地蚀刻第二外延层102b以在第二外延层102b的侧壁中形成“U”形的凹槽。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(001)晶向并且第一外延层102a显示了沿着侧壁的(110)晶向。在约20℃至约100℃的温度下以及在约5托至约50托的压力下使用HCl或Cl2气体实施约5秒至100秒的干蚀刻工艺选择性地蚀刻第二外延层102b,从而提供了“U”形的凹槽。
现在参照图28D,在实施例中,其中,第一外延层102a是Si0.5Ge0.5并且第二外延层102b是Si,可以均匀地蚀刻第一外延层102a以在第一外延层102a的侧壁中形成凹槽或削薄第一外延层102a。在这个实施例中,第二外延层102b(例如,硅层)显示了沿着顶面的(110)晶向并且第一外延层102a显示了沿着侧壁的(111)晶向。在约5℃至约50℃的温度下使用TMAH或NH4OH约5秒至约100秒的蚀刻选择性地蚀刻第一外延层102a,从而提供具有(111)晶向的凹进的表面。
图29A和图29B示出了根据一些实施例的交替外延层结构102的上层与沟道区域中的SRB 2710分开的实施例。具体地,图29A示出了完全地去除了最下的第一外延层102a的实施例,并且图29B示出了削薄最下的第一外延层的中间部分直至交替外延层结构102的上层与沟道区域中的SRB2710完全地分开的实施例。
例如,在一些实施例中,当诸如SRB 2710包括Si0.3Ge0.7,第一外延层102a包括Si0.5Ge0.5并且第二外延层102b包括Ge时,去除图29A示出的诸如最下的第一外延层102a的交替外延层结构102的一层或多层是期望的。当形成n-型FinFET时,诸如这些的实施例可能会特别有益。
在这个实施例中,与第一外延层102a和SRB 2710相比,Ge材料具有更大的晶格常数,并且与第一外延层102a相比,SRB 2710具有更大的晶格常数。在n-型器件中,Si0.5Ge0.5用作沟道区域中的电子的载体。去除最下的第一外延层102a使邻近的第二外延层102b(在这个示出的实施例中是Ge)弛豫,并且因此,减小了剩余的第二外延层102b中的压缩应力或引起了第二外延层102b中的拉伸应力。
图30A至图30F示出了根据一些实施例的用于去除最下的第一外延层102a的各个中间工艺步骤。图30A至图30F采取类似于参照图1至图26的上述讨论的那些的工艺,其中,相同的参考标号指定相同的元件。现在参照图30A,已经实施了采取的参照图1至图4的上述讨论的工艺。然而,图5示出了使STI 412凹进的实施例,从而使得暴露了最下的第一外延层102a,图30A中示出的实施例使STI 412凹进,使得未暴露最下的第一外延层102a。
在一些实施例中,如参照图6的上述讨论的,在形成伪栅极介电层618之前,可以在鳍上方形成附加掩模层3080。在随后的处理期间,附加掩模层3080对鳍310提供了额外的保护以去除最下的第一外延层102a。在这些实施例中,附加掩模层3080可以是在鳍结构310上方形成的晶体硅覆盖层或氮化硅层。
之后,可以实施诸如参照图6至图21的上述讨论的工艺。例如,图30C示出了参照图6至图21的上述讨论的在鳍310上方形成的伪栅电极720和形成的其它结构。
图30D示出了根据一些实施例的使用图案化的掩模3072的p-型第一鳍310a的掩蔽。应该注意,为了说明的目的,图30A至图30E示出,p-型第一鳍310a被掩蔽,但是应该理解,可以根据此处讨论的其它的工艺(包括参照图1至图26的上述讨论的那些)处理p-型第一鳍310a。在一些实施例中,图案化的掩模可以由氮化硅形成,但是可以使用其它的材料。
现在,转向图30E,去除伪栅电极720的暴露的部分以暴露第二鳍310b和STI 412的表面,并且图30F示出了使STI 410凹进以暴露第二鳍310b的最下的第一外延层102a。如图30F示出的,附加掩模层3080保护了交替外延层结构102的上层而最下的第一外延层102a未由附加掩模层3080保护。因此,可以蚀刻最下的第一外延层102a以使交替外延层结构102的上层与SRB 2710分开,从而弛豫或减小交替外延层结构102的剩余的层的压缩应力。图30G示出了根据一些实施例的最下的第一外延层102a的去除。
可以使用任何合适的工艺去除最下的第一外延层102a。例如,如图29A示出的,可以实施诸如参照图22的上述讨论的那些的工艺以完全地去除最下的外延层102a。如另一个实例,如图29B示出的,可以在较长时间内实施诸如参照图27B的上述讨论的那些的工艺以使最下的第一外延层102a的相对侧壁凹进,直至交替外延层结构102的上层与SRB 2710分开。
图29A和图29B示出的实施例可以与诸如图27B至图27D和图28B至图28D示出的那些的实施例相结合。例如,图31A示出的实施例中,如参照图29A的上述讨论地去除最下的第一外延层102a并且蚀刻剩余的第一外延层102a以实现参照图27B的上述讨论的“V”形的侧壁。类似地,图31B示出的实施例中,如参照图29A的上述讨论地去除最下的第一外延层102a并且蚀刻剩余的第一外延层102a以实现参照图27C的上述讨论的“U”形的侧壁,并且图31C示出的实施例中,如参照图29A的上述讨论地去除最下的第一外延层102a并且蚀刻剩余的第一外延层102a以形成参照图27D的上述讨论的凹进的侧壁。
如进一步的实例,图31D示出的实施例中,参照图29B的上述讨论的在最下的第一外延层102a上刻凹痕并且蚀刻剩余的第一外延层102a以实现参照图27B的上述讨论的“V”形的侧壁。类似地,图31E示出的实施例中,参照图29B的上述讨论的在最下的第一外延层102a上刻凹痕并且蚀刻剩余的第一外延层102a以实现参照图27C的上述讨论的“U”形的侧壁,并且图31F示出的实施例中,参照图29B的上述讨论的在最下的第一外延层102a上刻凹痕并且蚀刻剩余的第一外延层102a以形成参照图27D的上述讨论的凹进的侧壁。
图31G示出了去除全部的第一外延层102a的图1至图26的部件以及在SRB 2710上方形成交替外延层结构102的图27A的部件结合的实施例。可以使用参照上述图的上述讨论的那些的相关的工艺。
根据一些实施例,图32A至图32B示出了使用参照图29A和图29B的上述讨论的可以用于形成p-型器件的材料的各个实施例。如上所述,在一些实施例中,SRB 2710包括Si0.3Ge0.7,第一外延层102a包括Si0.5Ge0.5,并且第二外延层102b包括Ge。在这些实施例中,用于p-型FinFET的第一源极/漏极区域可以包括GeSn。首先参照图32A,这里示出的实施例剩余了全部的第一外延层102a和第二外延层102b并且既没有削薄第一外延层102a的侧壁也没有削薄第二外延层102b的侧壁(例如,“V”形,“U”形或有凹口的)。在这样的实施例中,由于第一外延层102a的Si0.5Ge0.5和SRB 2710的Si0.3Ge0.7的更小的晶格常数,因此第二外延层102b的Ge材料用作p-型FinFET的空穴载体并且将经受压缩应力。
图32B至图32D示出的实施例类似于图28B至图28D,除了图32B至图32D中削薄的是第一外延层102a的侧壁,而不是图28B至图28D的第二外延层102b的侧壁。例如,图28B至图28D示出的实施例中,第一外延层102a包括Si0.5Ge0.5并且第二外延层102b包括Si。在p-型器件中,由于第二外延层102b的Si材料的更小的晶格常数,因此Si0.5Ge0.5用作空穴载体并且经受压缩应力。在图30B至图30D中,由于第一外延层102a的Si0.5Ge0.5和SRB 2710的Si0.3Ge0.7的更小的晶格常数,因此第二外延层102b的Ge材料用作空穴载体并且经受压缩应力。相应地,削薄第一外延层102a,从而改进第二外延层102b的栅极控制。可以使用参照图28B中的第一外延层102a的Si0.5Ge0.5的上述讨论的类似的工艺形成图32B中的第一外延层102a的Si0.5Ge0.5中的“V”形的侧壁。可以使用参照图28C中的第一外延层102a的Si0.5Ge0.5的上述讨论的类似的工艺形成图32C中的第一外延层102a的Si0.5Ge0.5中的“U”形的侧壁。可以使用参照图28D中的第一外延层102a的Si0.5Ge0.5的上述讨论的类似的工艺形成图32D中的第一外延层102a的Si0.5Ge0.5中的缩进的或有凹口的侧壁。
可以明白,例如,诸如此处讨论的那些的实施例通过提供纳米线结构和与载流层的更大的栅极相互作用而提供了更大的栅极控制。例如,沟道区域中的纳米线结构的创建允许GAA结构和更大的栅极控制。类似地,使用外延材料的交替层允许更大的应力(压缩或拉伸)并且削薄选择层也允许更大的栅极控制。因此,在沟道区域中使用不同处理的n-型和p-型器件可以使用类似的材料,从而减小了涉及不同的外延层生长的制造成本和处理时间。
此外,交替外延层结构102的使用提供了改进的器件性能。交替外延层结构102通过插入交替应力层而防止或减小了应变弛豫。通过选择材料,使得在用作载体(例如,用于空穴或电子)的层上施加应力(压缩或拉伸),可以控制载流层中的应力至更大程度。
在实施例中,提供了形成半导体器件的方法,该方法包括形成第一鳍和第二鳍,每个第一鳍和第二鳍均包括交替外延结构,交替外延结构具有多个外延层,多个外延层包括第一外延层和第二外延层,第一外延层包括第一半导体材料,第二外延层包括第二半导体材料,交替外延结构的层在一个第一外延层和一个第二外延层之间交替。在第一鳍和第二鳍上方形成第一介电层,并且暴露了第二鳍的沟道区域。该方法还包括去除第二鳍的沟道区域中的至少部分第一外延层,在第一鳍上方形成第一栅极堆叠件,第一栅极堆叠件沿着第一鳍的第一外延层和第二外延层的侧壁延伸,并且在第二鳍上方形成第二栅极堆叠件,第二栅极堆叠件沿着第二外延层的侧壁延伸。
在上述方法中,其中,去除至少部分所述第一外延层完全地去除了所述沟道区域中的邻近的所述第二外延层之间的所述第一外延层。
在上述方法中,其中,所述第一栅极堆叠件和所述第二栅极堆叠件是相同的栅极堆叠件。
在上述方法中,其中,所述第一鳍包括p-型晶体管的沟道区域并且所述第二鳍包括n-型晶体管的沟道区域。
在上述方法中,还包括:在衬底上方形成应变弛豫缓冲(SRB);在所述应变弛豫缓冲上方形成所述交替外延结构;以及在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间。
在上述方法中,还包括:在衬底上方形成应变弛豫缓冲(SRB);在所述应变弛豫缓冲上方形成所述交替外延结构;以及在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间,其中,所述沟槽完全地穿过所述应变弛豫缓冲延伸。
在上述方法中,还包括:在衬底上方形成应变弛豫缓冲(SRB);在所述应变弛豫缓冲上方形成所述交替外延结构;以及在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间,其中,去除至少部分所述第一外延层包括将所述第二外延层的最下的第二外延层与所述沟道区域中的所述应变弛豫缓冲分开。
在上述方法中,还包括:在形成所述第一介电层之后,暴露所述第一鳍的所述第二外延层的最上的第二外延层;以及去除所述第一鳍的所述第二外延层的所述最上的第二外延层,其中,所述第二栅极堆叠件在所述第一鳍的最上的第一外延层的上表面上方延伸。
在上述方法中,其中,去除至少部分所述第一外延层包括沿着所述第一外延层的所述侧壁形成V形的缩进。
在上述方法中,其中,去除至少部分所述第一外延层包括沿着所述第一外延层的所述侧壁形成U形的缩进。
在上述方法中,其中,去除至少部分所述第一外延层包括使所述第一外延层的所述侧壁凹进。
在另一个实施例中,提供了形成半导体器件的方法。该方法包括形成第一鳍和第二鳍,每个第一鳍和第二鳍均包括交替外延结构,交替外延结构具有多个外延层,多个外延层包括第一外延层和第二外延层,第一外延层包括第一半导体材料,第二外延层包括第二半导体材料,交替外延结构的层在一个第一外延层和一个第二外延层之间交替。选择性地蚀刻第一鳍的第一沟道区域中的至少一个第一外延层的侧壁,并且选择性地蚀刻第二鳍的第二沟道区域中的至少一个第二外延层的侧壁。在第一鳍上方形成第一栅极堆叠件,并且在第二鳍上方形成第二栅极堆叠件。
在上述方法中,其中,选择性地蚀刻至少一个所述第一外延层的所述侧壁完全地去除全部的所述第一外延层。
在上述方法中,其中,选择性地蚀刻至少一个所述第一外延层包括:去除所述第一沟道区域中的所述第一外延层的最下的第一外延层;以及选择性地蚀刻所述第一沟道区域中的剩余的所述第一外延层的侧壁。
在上述方法中,其中,选择性地蚀刻至少一个所述第一外延层包括:去除所述第一沟道区域中的所述第一外延层的最下的第一外延层;以及选择性地蚀刻所述第一沟道区域中的剩余的所述第一外延层的侧壁,其中,选择性地蚀刻剩余的所述第一外延层的所述侧壁包括沿着所述第一外延层的所述侧壁形成V形的缩进。
在上述方法中,其中,选择性地蚀刻至少一个所述第一外延层包括:去除所述第一沟道区域中的所述第一外延层的最下的第一外延层;以及选择性地蚀刻所述第一沟道区域中的剩余的所述第一外延层的侧壁,其中,选择性地蚀刻剩余的所述第一外延层的所述侧壁包括沿着所述第一外延层的所述侧壁形成U形的缩进。
在上述方法中,其中,选择性地蚀刻至少一个所述第一外延层包括:去除所述第一沟道区域中的所述第一外延层的最下的第一外延层;以及选择性地蚀刻所述第一沟道区域中的剩余的所述第一外延层的侧壁,其中,选择性地蚀刻剩余的所述第一外延层的所述侧壁包括使所述第一外延层的所述侧壁凹进。
在上述方法中,还包括:在衬底上方形成应变弛豫缓冲(SRB);在所述应变弛豫缓冲上方形成所述交替外延结构;以及在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间。
在上述方法中,还包括:在衬底上方形成应变弛豫缓冲(SRB);在所述应变弛豫缓冲上方形成所述交替外延结构;以及在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间,其中,选择性地蚀刻所述第一鳍的所述第一沟道区域中的至少一个所述第一外延层的所述侧壁包括形成穿过所述第一鳍的开口。
在又另一个实施例中,形成了半导体器件。该器件包括衬底、第一源极/漏极区域和在第一源极/漏极区域之间插入的第一沟道区域(第一源极/漏极区域和第一沟道区域包括第一外延层和第二外延层的交替层)以及第二源极/漏极区域和在第二源极/漏极区域之间插入的第二沟道区域,第二源极/漏极区域包括第一外延层和第二外延层的交替层,第二沟道区域包括第二外延层,其中,在第二源极/漏极区域之间存在第一外延层中的间隙。第一栅电极在第一沟道区域上方延伸,并且第二栅电极在第二沟道区域上方延伸。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (18)
1.一种形成半导体器件的方法,所述方法包括:
形成第一鳍和第二鳍,每个所述第一鳍和每个所述第二鳍均包括交替外延结构,所述交替外延结构具有多个外延层,所述多个外延层包括第一外延层和第二外延层,所述第一外延层包括第一半导体材料,所述第二外延层包括第二半导体材料,所述交替外延结构的层在一个所述第一外延层和一个所述第二外延层之间交替;
在所述第一鳍和所述第二鳍上方形成第一介电层;
暴露所述第二鳍的沟道区域;
去除所述第二鳍的所述沟道区域中的至少部分所述第一外延层以沿着所述第一外延层的侧壁形成凹进;
在所述第一鳍上方形成第一栅极堆叠件,所述第一栅极堆叠件沿着所述第一鳍的所述第一外延层的侧壁和所述第二外延层的侧壁延伸;以及
在所述第二鳍上方形成第二栅极堆叠件,所述第二栅极堆叠件沿着所述第二外延层的侧壁延伸。
2.根据权利要求1所述的形成半导体器件的方法,其中,去除至少部分所述第一外延层完全地去除了所述沟道区域中的邻近的所述第二外延层之间的所述第一外延层。
3.根据权利要求1所述的形成半导体器件的方法,其中,所述第一栅极堆叠件和所述第二栅极堆叠件是相同的栅极堆叠件。
4.根据权利要求1所述的形成半导体器件的方法,其中,所述第一鳍包括p-型晶体管的沟道区域并且所述第二鳍包括n-型晶体管的沟道区域。
5.根据权利要求1所述的形成半导体器件的方法,还包括:
在衬底上方形成应变弛豫缓冲(SRB);
在所述应变弛豫缓冲上方形成所述交替外延结构;以及
在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间。
6.根据权利要求5所述的形成半导体器件的方法,其中,所述沟槽完全地穿过所述应变弛豫缓冲延伸。
7.根据权利要求5所述的形成半导体器件的方法,其中,去除至少部分所述第一外延层包括将所述第二外延层的最下的第二外延层与所述沟道区域中的所述应变弛豫缓冲分开。
8.根据权利要求1所述的形成半导体器件的方法,还包括:
在形成所述第一介电层之后,暴露所述第一鳍的所述第二外延层的最上的第二外延层;以及
去除所述第一鳍的所述第二外延层的所述最上的第二外延层,其中,所述第二栅极堆叠件在所述第一鳍的最上的第一外延层的上表面上方延伸。
9.根据权利要求1所述的形成半导体器件的方法,其中,去除至少部分所述第一外延层包括沿着所述第一外延层的所述侧壁形成V形的缩进。
10.根据权利要求1所述的形成半导体器件的方法,其中,去除至少部分所述第一外延层包括沿着所述第一外延层的所述侧壁形成U形的缩进。
11.一种形成半导体器件的方法,所述方法包括:
形成第一鳍和第二鳍,每个所述第一鳍和每个所述第二鳍均包括交替外延结构,所述交替外延结构具有多个外延层,所述多个外延层包括第一外延层和第二外延层,所述第一外延层包括第一半导体材料,所述第二外延层包括第二半导体材料,所述交替外延结构的层在一个所述第一外延层和一个所述第二外延层之间交替;
选择性地蚀刻所述第一鳍的第一沟道区域中的至少一个所述第一外延层的侧壁以沿着所述第一外延层的所述侧壁形成凹进;
选择性地蚀刻所述第二鳍的第二沟道区域中的至少一个所述第二外延层的侧壁;
在所述第一鳍上方形成第一栅极堆叠件;以及
在所述第二鳍上方形成第二栅极堆叠件。
12.根据权利要求11所述的形成半导体器件的方法,其中,选择性地蚀刻至少一个所述第一外延层的所述侧壁完全地去除全部的所述第一外延层。
13.根据权利要求11所述的形成半导体器件的方法,其中,选择性地蚀刻至少一个所述第一外延层包括:
去除所述第一沟道区域中的所述第一外延层的最下的第一外延层;以及
选择性地蚀刻所述第一沟道区域中的剩余的所述第一外延层的侧壁。
14.根据权利要求13所述的形成半导体器件的方法,其中,选择性地蚀刻剩余的所述第一外延层的所述侧壁包括沿着所述第一外延层的所述侧壁形成V形的缩进。
15.根据权利要求13所述的形成半导体器件的方法,其中,选择性地蚀刻剩余的所述第一外延层的所述侧壁包括沿着所述第一外延层的所述侧壁形成U形的缩进。
16.根据权利要求11所述的形成半导体器件的方法,还包括:
在衬底上方形成应变弛豫缓冲(SRB);
在所述应变弛豫缓冲上方形成所述交替外延结构;以及
在所述交替外延结构中形成沟槽,所述沟槽至少部分地延伸至所述应变弛豫缓冲,其中,所述第一鳍和所述第二鳍插入在邻近的所述沟槽之间。
17.根据权利要求16所述的形成半导体器件的方法,其中,选择性地蚀刻所述第一鳍的所述第一沟道区域中的至少一个所述第一外延层的所述侧壁包括形成穿过所述第一鳍的开口。
18.一种半导体器件,包括:
衬底;
第一源极区域、第一漏极区域和在所述第一源极区域与所述第一漏极区域之间插入的第一沟道区域,所述第一源极区域、所述第一漏极区域和所述第一沟道区域包括第一外延层和第二外延层的交替层;
第二源极区域、第二漏极区域和在所述第二源极区域与所述第二漏极区域之间插入的第二沟道区域,所述第二源极区域、所述第二漏极区域包括所述第一外延层和所述第二外延层的所述交替层,所述第二沟道区域包括所述第二外延层,其中,在所述第二源极区域和所述第二漏极区域之间的所述第一外延层中存在沿着所述第一外延层的侧壁的间隙;
第一栅电极,在所述第一沟道区域上方延伸;以及
第二栅电极,在所述第二沟道区域上方延伸。
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DE102016100022B4 (de) | 2021-03-18 |
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