CN112349591A - 改善寄生沟道效应的ns-fet及其制备方法 - Google Patents
改善寄生沟道效应的ns-fet及其制备方法 Download PDFInfo
- Publication number
- CN112349591A CN112349591A CN202011167515.2A CN202011167515A CN112349591A CN 112349591 A CN112349591 A CN 112349591A CN 202011167515 A CN202011167515 A CN 202011167515A CN 112349591 A CN112349591 A CN 112349591A
- Authority
- CN
- China
- Prior art keywords
- fin
- fet
- isolation material
- isolation
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 33
- 230000000694 effects Effects 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000005465 channeling Effects 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 239000002135 nanosheet Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nanotechnology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本公开提供一种改善寄生沟道效应的NS‑FET制备方法，包括：操作S1：在衬底上生长外延层并在外延层上制备掩膜；操作S2：对应所述掩膜刻蚀部分衬底形成鳍条部，刻蚀整个外延层形成沟道部；操作S3：在所述鳍条部的两侧台面区填充隔离材料形成隔离区；操作S4：制备侧墙包裹所述沟道部；操作S5：去除部分所述隔离材料并刻蚀窄化裸露出的鳍条部生成鳍条，去除所述侧墙及所述掩膜后制作栅极和源漏，完成改善寄生沟道效应的NS‑FET的器件制备。本公开还提供一种改善寄生沟道效应的NS‑FET。
Description
技术领域
本公开涉及半导体技术领域，尤其涉及一种改善寄生沟道效应的NS-FET及其制备方法。
背景技术
随着科技的发展，未来CMOS集成电路微缩将持续进行，半导体器件结构将从3DfinFET(fin Field-Effect Transistor，鳍式场效应晶体管)发展到3D堆叠GAA(Gate-All-Around，环绕栅极)NS-FET(NanoSheets FET，纳米片场效应晶体管)。
但是由于NS-FET制备工艺的特点，底部Sub-Fin引起的寄生沟道效应不可忽视，因此如何改善寄生沟道效应是一个亟需解决的技术问题。
公开内容
(一)要解决的技术问题
基于上述问题，本公开提供了一种改善寄生沟道效应的NS-FET及其制备方法，以缓解现有技术中半导体器件制备时容易引起寄生沟道效应，进而导致器件性能退化等技术问题。
(二)技术方案
本公开的一个方面，提供一种改善寄生沟道效应的NS-FET制备方法，包括：
操作S1：在衬底上生长外延层并在外延层上制备掩膜；
操作S2：对应掩膜刻蚀部分衬底形成鳍条部，刻蚀整个外延层形成沟道部；
操作S3：在鳍条部的两侧台面区填充隔离材料形成隔离区；
操作S4：制备侧墙包裹沟道部；
操作S5：去除部分隔离材料并刻蚀窄化裸露出的鳍条部生成鳍条，去除侧墙及掩膜后制作栅极和源漏，完成改善寄生沟道效应的NS-FET的器件制备。
根据本公开实施例，步骤S5还包括，完全去除隔离材料，整体刻蚀窄化鳍条部形成鳍条，重新填充隔离材料使其包裹鳍条的下部形成隔离区，制作栅极和源漏后完成改善寄生沟道效应的NS-FET的器件制备。
根据本公开实施例，外延层为交替外延生长的锗硅和硅层。
根据本公开实施例，操作S3中，在鳍条部的两侧台面区填充的隔离材料填充至鳍条部和沟道部的交界处附近。
根据本公开实施例，隔离材料为Oxide。
本公开的另一方面，提供一种改善寄生沟道效应的NS-FET，采用以上任一项的制备方法制备而成，改善寄生沟道效应的NS-FET，包括：
衬底，其上部制备有凸出的鳍条；
沟道部，覆于鳍条上，其宽度大于鳍条的上部的宽度；以及
隔离区，位于鳍条的下部的两侧。
根据本公开实施例，凸出的鳍条两侧分别形成有台面区，台面区用于填充隔离材料形成隔离区。
(三)有益效果
从上述技术方案可以看出，本公开改善寄生沟道效应的NS-FET及其制备方法至少具有以下有益效果其中之一或其中一部分：
(1)完全兼容常规的NS-FET制备工艺；
(2)降低了寄生沟道的漏电；
(3)提高了Sub-Fin(亚鳍式结构)的栅控能力，在不增加漏电的情况下提高了驱动电流，以及开关比，获得了更小的DIBL(Drain Induced Barrier Lowering，漏致势垒降低效应)以及SS(Subthreshold Swing，亚阈值摆幅)；
(4)提高了Sub-Fin露出以及sub-SD(亚源漏)刻蚀的工艺窗口，获得了更稳定的器件特性。
附图说明
图1为本公开实施例改善寄生沟道效应的NS-FET制备方法的流程示意图。
图2为图1中操作S1后的器件结构示意图。
图3为图1中操作S2后的器件结构示意图。
图4为图1中操作S3后的器件结构示意图。
图5为图1中操作S4后的器件结构示意图。
图6-图7为图1中操作S5后的器件结构示意图。
图8-图9为图1中另一种操作S5后的器件结构示意图。
图10a为采用图8-图9所示器件结构形成的改善寄生沟道效应的NS-FET的立体结构示意图。
图10b为图10a沿垂直沟道部延伸方向剖开后的结构示意图。
图10c为图10a沿沟道部延伸方向剖开后的结构示意图。
具体实施方式
本公开提供了一种改善寄生沟道效应的NS-FET及其制备方法，通过窄化Sub-Fin结构，实现具有优秀栅控的sub-channel(亚沟道)导电沟道的纳米片场效应晶体管。
在实现本公开的过程中发明人发现，由于NS-FET制备的特点，底部Sub-Fin引起的寄生沟道效应不可忽视，尤其在3nm技术节点以下，栅长越来越短的情况下，底部寄生沟道的漏电会变得越来越严重，仅仅依靠表面掺杂并不足以改善漏电引起的器件性能的退化。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
在本公开实施例中，提供一种改善寄生沟道效应的NS-FET制备方法，结合图1至图10c所示，所述制备方法，包括：
操作S1：在衬底上生长外延层并在外延层上制备掩膜；
在本公开实施例中，如图2所示，衬底的制备材料为硅；然后在硅衬底上交替外延生长锗硅和硅层。
在本公开实施例中，掩膜成条状，制备材料为氮化硅。
操作S2：对应所述掩膜刻蚀部分衬底形成鳍条部(即Sub-Fin)，刻蚀整个外延层形成沟道部；如图3所示。
操作S3：在所述鳍条部的两侧台面区填充隔离材料形成隔离区；
在本公开实施例中，如图4所示，在对应鳍条部两侧台面区填充隔离材料，即填充至鳍条部和沟道部的交界处，沟道部两侧未填充隔离材料。所述隔离材料为Oxide。
操作S4：制备侧墙包裹所述沟道部；如图5所示。
操作S5：去除部分所述隔离材料并刻蚀窄化裸露出的鳍条部(即窄化Sub-Fin)，去除所述侧墙及所述掩膜后制作栅极和源漏，完成改善寄生沟道效应的NS-FET的器件制备。如图6至图7所示。
在本公开实施例中，所述步骤S5还包括，完全去除所述隔离材料，整体刻蚀窄化鳍条部形成鳍条，重新填充隔离材料使其包裹所述鳍条的下部形成隔离区，进行后续工艺(制作栅极和源漏)完成改善寄生沟道效应的NS-FET的制备。如图8至图10c所示。
从而，本公开利用传统纳米片场效应晶体管制备工艺，实现了具有窄Sub-Fin的改善寄生沟道效应的纳米片场效应晶体管结构。
本公开另一方面还提供一种改善寄生沟道效应的NS-FET，采用上述的制备方法制备而成，所述改善寄生沟道效应的NS-FET，包括：
衬底，其上部制备有凸出的鳍条；
沟道部，覆于所述鳍条上，其宽度大于所述鳍条的上部的宽度；
隔离区，位于所述鳍条的下部的两侧；
其中，所述鳍条的下部的宽度大于所述鳍条的上部的宽度；或者所述鳍条的下部的宽度等于所述鳍条的上部的宽度。
所述凸出的鳍条两侧分别形成有台面区，用于填充隔离材料形成隔离区。
在本公开实施例中，图10a至图10c所示，所述沟道部延伸方向的起始端和截止端还制备有Spacer。
至此，已经结合附图对本公开实施例进行了详细描述。需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
依据以上描述，本领域技术人员应当对本公开改善寄生沟道效应的NS-FET及其制备方法有了清楚的认识。
综上所述，本公开提供了一种改善寄生沟道效应的NS-FET及其制备方法，该NS-FET具有相对于纳米片沟道较窄的Sub-Fin的晶体管结构及工艺方法，部分窄的Sub-Fin露出STI表面，实现具有优秀栅控的sub-channel导电沟道。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
此外，除非特别描述或必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。并且上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
Claims (7)
1.一种改善寄生沟道效应的NS-FET制备方法，包括：
操作S1：在衬底上生长外延层并在外延层上制备掩膜；
操作S2：对应所述掩膜刻蚀部分衬底形成鳍条部，刻蚀整个外延层形成沟道部；
操作S3：在所述鳍条部的两侧台面区填充隔离材料形成隔离区；
操作S4：制备侧墙包裹所述沟道部；
操作S5：去除部分所述隔离材料并刻蚀窄化裸露出的鳍条部生成鳍条，去除所述侧墙及所述掩膜后，制作栅极和源漏，完成改善寄生沟道效应的NS-FET的器件制备。
2.根据权利要求1所述的制备方法，所述步骤S5还包括，完全去除所述隔离材料，整体刻蚀窄化鳍条部形成鳍条，重新填充隔离材料使其包裹所述鳍条的下部形成隔离区，制作栅极和源漏后完成改善寄生沟道效应的NS-FET的器件制备。
3.根据权利要求1所述的制备方法，所述外延层为交替外延生长的锗硅层和硅层。
4.根据权利要求1所述的制备方法，操作S3中，在鳍条部的两侧台面区填充的隔离材料填充至鳍条部和沟道部的交界处附近。
5.根据权利要求1所述的制备方法，所述隔离材料为Oxide。
6.一种改善寄生沟道效应的NS-FET，采用以上权利要求1至5任一项所述的制备方法制备而成，所述改善寄生沟道效应的NS-FET，包括：
衬底，其上部制备有凸出的鳍条；
沟道部，覆于所述鳍条上，其宽度大于所述鳍条的上部的宽度；以及
隔离区，位于所述鳍条的下部的两侧。
7.根据权利要求6所述的改善寄生沟道效应的NS-FET，所述凸出的鳍条两侧分别形成有台面区，所述台面区用于填充隔离材料形成隔离区。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011167515.2A CN112349591A (zh) | 2020-10-27 | 2020-10-27 | 改善寄生沟道效应的ns-fet及其制备方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011167515.2A CN112349591A (zh) | 2020-10-27 | 2020-10-27 | 改善寄生沟道效应的ns-fet及其制备方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112349591A true CN112349591A (zh) | 2021-02-09 |
Family
ID=74358812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011167515.2A Pending CN112349591A (zh) | 2020-10-27 | 2020-10-27 | 改善寄生沟道效应的ns-fet及其制备方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112349591A (zh) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170236917A1 (en) * | 2016-02-16 | 2017-08-17 | Globalfoundries Inc. | Finfet having notched fins and method of forming same |
| CN109285778A (zh) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN110189997A (zh) * | 2019-04-28 | 2019-08-30 | 中国科学院微电子研究所 | 堆叠纳米片环栅晶体管及其制备方法 |
| CN110690290A (zh) * | 2019-09-18 | 2020-01-14 | 华东师范大学 | 一种非对称栅氧结构的纳米片环栅场效应晶体管 |
| CN111128736A (zh) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 半导体元件的制造方法及其元件 |
| US20200273753A1 (en) * | 2019-02-25 | 2020-08-27 | International Business Machines Corporation | Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer |
-
2020
- 2020-10-27 CN CN202011167515.2A patent/CN112349591A/zh active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170236917A1 (en) * | 2016-02-16 | 2017-08-17 | Globalfoundries Inc. | Finfet having notched fins and method of forming same |
| CN109285778A (zh) * | 2017-07-20 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN111128736A (zh) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 半导体元件的制造方法及其元件 |
| US20200273753A1 (en) * | 2019-02-25 | 2020-08-27 | International Business Machines Corporation | Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer |
| CN110189997A (zh) * | 2019-04-28 | 2019-08-30 | 中国科学院微电子研究所 | 堆叠纳米片环栅晶体管及其制备方法 |
| CN110690290A (zh) * | 2019-09-18 | 2020-01-14 | 华东师范大学 | 一种非对称栅氧结构的纳米片环栅场效应晶体管 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10998425B2 (en) | FinFET structure and method for fabricating the same | |
| US10535757B2 (en) | Structure of a fin field effect transistor (FinFET) | |
| US8633076B2 (en) | Method for adjusting fin width in integrated circuitry | |
| CN103296023B (zh) | 半导体器件及其制造和设计方法 | |
| CN111584486B (zh) | 具有交错结构的半导体装置及其制造方法及电子设备 | |
| KR101504311B1 (ko) | 맨드렐 산화 공정을 사용하여 finfet 반도체 디바이스용 핀들을 형성하는 방법 | |
| US9455346B2 (en) | Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage | |
| TWI576902B (zh) | 半導體裝置與其製作方法 | |
| US8410547B2 (en) | Semiconductor device and method for fabricating the same | |
| US20070132053A1 (en) | Integrated Circuit On Corrugated Substrate | |
| KR20060062048A (ko) | 핀 전계 효과 트랜지스터 및 그 제조방법 | |
| KR102088706B1 (ko) | 금속 소스/드레인 기반 전계효과 트랜지스터 및 이의 제조방법 | |
| US20160329400A1 (en) | Nanowire and method of fabricating the same | |
| CN111106176B (zh) | 半导体器件及其制造方法及包括该半导体器件的电子设备 | |
| CN112349592B (zh) | 避免寄生沟道效应的ns-fet及其制备方法 | |
| CN109326650B (zh) | 半导体器件及其制造方法及包括该器件的电子设备 | |
| CN112349590B (zh) | 改善寄生沟道效应的ns-fet及其制备方法 | |
| KR100467527B1 (ko) | 이중 게이트 ｍｏｓｆｅｔ 및 그 제조방법 | |
| CN112349591A (zh) | 改善寄生沟道效应的ns-fet及其制备方法 | |
| US9472550B2 (en) | Adjusted fin width in integrated circuitry | |
| CN115241272A (zh) | 半导体元件 | |
| CN108376709B (zh) | 一种插入倒t形介质层的鳍式场效应晶体管及其制备方法 | |
| CN113380797A (zh) | 半导体装置及其制造方法及包括其的电子设备 | |
| KR20060027440A (ko) | 용량성 결합된 접합 핀 전계 효과 트랜지스터, 그 제조방법 및 이를 채용하는 상보형 트랜지스터 | |
| CN115939216B (zh) | 一种场效应晶体管及制备方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210209 |