CN111128736A - 半导体元件的制造方法及其元件 - Google Patents

半导体元件的制造方法及其元件 Download PDF

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CN111128736A
CN111128736A CN201911031414.XA CN201911031414A CN111128736A CN 111128736 A CN111128736 A CN 111128736A CN 201911031414 A CN201911031414 A CN 201911031414A CN 111128736 A CN111128736 A CN 111128736A
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layer
fin structure
semiconductor
gate
source
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CN111128736B (zh
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郑兆钦
陈奕升
江宏礼
陈自强
张开泰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件的制造方法及其元件。半导体元件的制造方法包括：形成鳍结构，具有下鳍结构和设置在下鳍结构上的上鳍结构。上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层。第一半导体层被部分地蚀刻以减少第一半导体层的宽度。形成氧化物层在上鳍结构上。形成牺牲栅极结构在具有氧化物层的上鳍结构上。形成源极/漏极磊晶层在鳍结构的源极/漏极区域上。去除牺牲栅极结构以形成栅极空间。去除氧化物层以暴露栅极空间中的第二半导体层。形成栅极结构在栅极空间中的第二半导体层的周围。

Description

半导体元件的制造方法及其元件
技术领域
本揭露是关于一种半导体元件的制造方法及其元件。
背景技术
随着半导体工业逐步发展为纳米技术节点以追求更高的元件密度，更高的性能和更低的成本，来自制造和设计问题的挑战导致三维设计的发展，例如多栅极场效晶体管(Field effect transistor，FET)，包括鳍式场效晶体管(FinFET)以及环绕式栅极(Gate-all-around，GAA)场效晶体管。在鳍式场效晶体管中，在邻近栅极电极的通道区域与栅极介电层之间插入三个侧表面。因为栅极结构在三个表面上围绕(包裹)鳍，所以晶体管实质上具有三个栅极，控制经由鳍或通道区域的电流。遗憾地，第四侧，其远离栅电极位于通道的底部，因此不受栅极控制。相反地，在一个环绕式栅极场效晶体管(GAA FET)中，通道区域的所有侧表面被栅极电极围绕，由于更陡峭的次临限摆动(Sub-threshold current swing,SS)和较小的漏极能障降低(DIBL)，允许在通道区域实现更充分的耗尽(Depletion)以及减少短通道效应(Short-channel effects)。随着晶体管尺寸不断缩小到次10-15纳米技术节点，需要进一步改进GAA FET。
发明内容
一种半导体元件的制造方法，包括：形成鳍结构，具有下鳍结构以及设置在下鳍结构上的上鳍结构，上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层；部分地蚀刻第一半导体层以减小第一半导体层的多个宽度；形成氧化物层在上鳍结构上；形成牺牲栅极结构在具有氧化物层的上鳍结构上；形成源极/漏极磊晶层在鳍结构的源极/漏极区域上；去除牺牲栅极结构以形成栅极空间；去除氧化物层以暴露栅极空间中的第二半导体层；以及形成栅极结构在栅极空间中的第二半导体层的周围。
一种半导体元件的制造方法，包括：形成鳍结构，具有下鳍结构以及设置在下鳍结构上的上鳍结构，上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层；部分地蚀刻第一半导体层以减小第一半导体层的多个宽度；形成氧化物层在上鳍结构上；形成牺牲栅极结构在具有氧化物层的上鳍结构上；形成源极/漏极磊晶层在鳍结构的源极/漏极区域上；去除牺牲栅极结构以形成栅极空间；去除栅极空间中的氧化物层以暴露栅极空间中的第二半导体层；形成第三半导体层在每个暴露的第二半导体层上；通过混合第三半导体层和第二半导体层形成多个通道线；以及形成栅极结构在栅极空间中的通道线的周围。
一种半导体元件，包括：下鳍结构、多个半导体线、栅极结构、多个栅极侧壁间隔物以及源极/漏极磊晶层。下鳍结构设置在基板上；多个半导体线设置在下鳍结构上；栅极结构设置在半导体线的多个通道区域上；多个栅极侧壁间隔物设置在栅极结构的多个相对的侧面上；并且介电层是由与栅极侧壁间隔物不同的材料制成，包裹在栅极侧壁间隔物之下的半导体线的周围。
附图说明
本揭露内容从后续实施例以及附图可以更佳理解。应注意的是，根据本产业的标准作业，许多构件未按照比例绘制。事实上，许多构件的尺寸可以任意地放大或缩小以清楚论述。
图1绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图2绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图3A和图3B绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图4A和图4B绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图5绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图6A，图6B，图6C和图6D绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图7A，图7B，图7C和图7D绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图8A，图8B，图8C和图8D绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图9A，图9B，图9C，图9D和图9E绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图10A，图10B，图10C，图10D，图10E和图10F绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图11A，图11B，图11C，图11D，图11E，图11F和图11G绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图12A，图12B，图12C，图12D和图12E绘示根据本揭露的一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图13A绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图13B绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图13C绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的视图；
图14A，图14B，图14C，图14D，图14E和图14F绘示根据本揭露的另一实施例的GAAFET元件的连续制程的各个阶段之一的各种视图；
图15A，图15B，图15C，图15D，图15E和图15F绘示根据本揭露的另一实施例的GAAFET元件的连续制程的各个阶段之一的各种视图；
图16A，图16B，图16C，图16D和图16E绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图17A，图17B，图17C和图17D绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图18A，图18B，图18C和图18D绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图19A，图19B，图19C，图19D和图19E绘示根据本揭露的另一实施例的GAA FET元件的连续制程的各个阶段之一的各种视图；
图20A，图20B，图20C和图20D绘示根据本揭露的一些实施例的GAA FET元件的各种视图。
【符号说明】
10 基板
12 杂质离子
11 下鳍结构
11A 下鳍结构
11B 下鳍结构
15 掩模层
15A 第一掩模层
15B 第二掩模层
20 第一半导体层
25 第二半导体层
26 第三半导体层
27 合金半导体层
29 气隙
30 鳍结构
30A 鳍结构
30B 鳍结构
35A 第一鳍衬垫层
35B 第二鳍衬垫层
40 隔离绝缘层
45 氧化物层
54 牺牲栅极电极
55 栅极侧壁间隔物
56 掩模层
60A 第一源极/漏极磊晶层
60B 第二源极/漏极磊晶层
62 源极/漏极磊晶层
63 第一绝缘衬垫层
65 层间介电质(ILD)层
102 界面层
104 栅极介电层
106 功函数调整层
108 栅电极层
110 第二绝缘衬垫层
115 第二ILD层
120 主体层
122 衬垫层
D1 蚀刻度
H1 高度
W1 宽度
具体实施方式
应理解，以下的揭露内容提供许多不同实施例或范例，以实施本揭露内容的不同结构。以下叙述构件及排列方式的特定实施例或范例，以求简化本揭露内容。当然，这些仅为范例说明并非用以限定本揭露内容。举例来说，构件尺寸并未限定于所揭露的范围或数值，而是根据制程条件及/或元件的期望特性。再者，若是以下的揭露内容叙述了将一第一特征部件形成于一第二特征部件上或上方，即表示其包含了上述第一特征部件与上述第二特征部件形成直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使得上述第一特征部件与上述第二特征部件可能未直接接触的实施例。为达简化及明确目的，不同特征部件可随意绘构成不同尺寸。为求简化，在所附附图中，可省略一些层别/特征部件。
再者，在空间上的相关用语，例如“之下”、“以下”、“下”、“以上”、“上”等等在此处是用以容易表达出本说明书中所绘示的附图中元件或特征部件与另外的元件或特征部件的关系。这些空间上的相关用语除了涵盖附图所绘示的方位外，还涵盖装置于使用或操作中的不同方位。此装置可具有不同方位(旋转90度或其他方位)且此处所使用的空间上的相关符号同样有相应的解释。此外，“由...所构成”一词可意味“包含”或“仅包含”。再者，在以下制程中，可于所述操作中或之间进行一或多个额外的操作，且可更改操作顺序。在此揭露中“A，B及C中的一个”一词意味A，B及/或C(A，B，C，A及B，A及C，B及C或A，B及C)，并不表示A中的一个元素，B中的一个元素以及C中的一个元素，除非另有说明。
在以下的实施例中，除非另有说明，否则可以在另一实施例中采用一个实施例的材料，配置，尺寸，操作及/或过程，并且可以省略其详细说明。
具有纳米尺寸的通道的环绕式栅极(GAA)场效晶体管，例如纳米线或纳米片，在半导体集成电路的进一步的技术节点中，被视为具有前景的元件，以实现较低的操作电源，较高的元件性能，较高的元件密度，以及较低的制程成本等。以上述准则来看，如何优化制程流程是关键挑战。在GAA FET制造流程中，用于通道磊晶(channel epitaxy)、内侧间隔(inner spacer)、形成纳米线(nanowire)，以及形成具有高k(介电常数)介电质的金属栅极的制程为常见的制程瓶颈。
在本揭露中，提出了解决上述问题的元件结构及其制造方法。
图1至图12E绘示根据本揭露的一实施例的制造GAA FET元件的连续制程。应当理解，可以在图1至图12E所示的操作之前，期间和之后提供额外操作，以及如下所述的一些操作可被替换或消除，对于该方法的额外实施例，其操作/过程的顺序是可互换的。
如图1所示，将杂质离子(掺杂剂)12植入硅基板10中以形成井区域。执行离子植入是为预防击穿效应(punch-through effect)。在一些实施例中，基板10至少在其表面部分上包括单晶半导体层。基板10可以包括单晶半导体材料，例如但不限于Si，Ge，SiGe，GaAs，InSb，GaP，GaSb，InAlAs，InGaAs，GaSbP，GaAsSb和InP。在一个实施例中，基板10由结晶硅制成。
基板10可包括在其表面区域中一或多个缓冲层(未绘示)。缓冲层可用于逐渐地将晶格常数从基板的晶格常数变化为源极/漏极区域的晶格常数。缓冲层可以由磊晶生长的单晶半导体材料形成，例如但不限于Si，Ge，GeSn，SiGe，GaAs，InSb，GaP，GaSb，InAlAs，InGaAs，GaSbP，GaAsSb，GaN，GaP和InP。在一个具体的实施例中，基板10包括在硅基板10上磊晶生长的硅锗(SiGe)缓冲层。SiGe缓冲层的Ge浓度可以从最底部缓冲层的30atomic％锗增加到最顶部缓冲层的70atomic％锗。基板10可以包括已经适当地掺杂杂质(例如，p型或n型导电性)的各种区域。举例来说，掺杂剂12是为用于n型FinFET的硼(BF2)和用于p型FinFET的磷。
如图2所示，在基板10上形成堆叠的半导体层。堆叠的半导体层包括第一半导体层20和第二半导体层25。再者，在堆叠层上形成掩模层15。第一半导体层20及第二半导体层25是由具有不同晶格常数的材料所制成，并且可包括一或多个层的Si，Ge，SiGe，GeSn，SiGeSn，GaAs，InSb，GaP,GaSb，InAlAs，InGaAs，GaSbP，GaAsSb或InP。
在一些实施例中，第一半导体层20和第二半导体层25是由Si，Si化合物，SiGe，Ge或Ge化合物制成。在特定实施例中，第一半导体层20为Si1-xGex，其中0.15≤x≤0.5，并且第二半导体层25为Si。在一些实施例中，0.15≤x≤0.25，在其它实施例中，第二半导体层25由Si1-yGey制成，其中y是等于或小于约0.2，以及x>y。
如图2所示，设置五层第一半导体层20以及五层第二半导体层25。然而，这些层的数目不限于五个，也可以小到为1(每一层)，在一些实施例中，形成2-20层的每个第一与第二半导体层。通过调整堆叠层的数量，可以调整GAA FET元件的驱动电流。
磊晶地形成第一半导体层20和第二半导体层25在基板10上。第一半导体层20的厚度可等于或小于第二半导体层25的厚度，在一些实施例中，第一半导体层20的厚度在约2nm至约10nm的范围内，在其他实施方案中，在约3nm至约5nm的范围内。在一些实施例中，第二半导体层25的厚度在至约5nm至约20nm的范围内，在其他实施方案中，在约7.5nm至约12.5nm的范围内。第一半导体层和第二半导体层中的每一个的厚度可以相同，或者可以变化。
在一些实施例中，底部第一半导体层(最接近基板10的层)的厚度大于其他的第一半导体层的厚度。在一些实施方案中，底部第一半导体层的厚度在约10nm至约50nm的范围内，或者在其他实施例中，其在20nm至40nm的范围内。
在一些实施例中，掩模层15包括第一掩模层15A和第二掩模层15B。第一掩模层15A是由氧化硅制成的衬垫氧化物层，其可以通过热氧化形成。第二掩模层15B是由氮化硅(SiN)制成，其通过化学气相沉积(CVD)形成，包括低压化学气相沉积(LPCVD)和电浆增强化学气相沉积(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)或其他合适的方法。使用图案操作包括微影和蚀刻，将掩模层15图案化为掩模图案。
接着，如图3A和图3B所示，通过图案化的掩模层图案化第一和第二半导体层20、25的堆叠层，从而使堆叠层形成为鳍结构30，鳍结构30在Y方向上延伸，并且沿着X方向布置。
可以通过任何合适的方法来图案化鳍结构30。例如，可以使用一或多个微影制程来图案化鳍结构，包括双重图案化或多重图案化制程。通常，双重图案化或多重图案化制程结合微影和自对准制程，从而允许产生具有较小间距的图案，例如，小于相对于使用单个、直接光微影制程所获得的间距。举例来说，在一个实施例中，在基板上形成并使用微影制程图案化牺牲层。使用自对准制程在图案化的牺牲层旁边形成间隔物。然后去除牺牲层，接着可以使用剩余的间隔物或心轴来图案化鳍结构。
如图3A及图3B所示，两个鳍结构30A和30B沿X方向布置。但鳍结构的数量不限于两个，并且可以小到一个以及三个或更多。在一些实施例中，形成一或多个虚设鳍结构在鳍结构30的两侧上，以改善图案化操作中的图案逼真度。如图3A和图3B所示，鳍结构30具有由堆叠的半导体层20、25构成的上部和井部分11，其对应于下鳍结构。在一些实施例中，鳍结构30A用于p通道GAA FET，鳍结构30B用于n通道GAA FET。如图4A所示，鳍结构30A和30B分别设置在下鳍结构11A和11B上。在其他实施例中，鳍结构用于相同类型的场效晶体管。
在一些实施例中，鳍结构30的上部的宽度W1沿X方向在约5nm至约30nm的范围内。在其他实施例中，在约7.5nm至约15nm的范围内。沿着Z方向上该鳍结构30的高度H1在约5nm至约200nm的范围内。
形成鳍结构之后，如图4A和图4B所示，横向地部分地蚀刻第一半导体层20。在一些实施例中，相对于第二半导体层25，使用电浆干蚀刻选择性地蚀刻第一半导体层20，然后使用缓冲HF(Buffered HF)进行湿式清洁制程。在一些实施例中，电浆源气体包括O2。在其它实施例中，湿蚀刻制程用于选择性地蚀刻第一半导体层20。蚀刻液(蚀刻剂)包括NH4OH的水溶液、H2O2和H2O及/或H2SO4、H2O2和H2O的水溶液。在其它实施例中，湿式蚀刻剂包括氢氧化四甲铵(TMAH)溶液。在一些实施例中，使用缓冲HF进行额外的湿式清洗制程。在特定实施例中，电浆干蚀刻和湿式蚀刻皆有使用。在一些实施例中，蚀刻量D1在约1nm至约10nm的范围内，在一些实施例中，在约2nm至约5nm的范围内。如图4B所示，经蚀刻的第一半导体层20的横截面的形状具有狗骨形状或线卷轴(或绕线管)形状。
部分蚀刻第一半导体层20之后，在基板上形成包括一或多层绝缘材料的绝缘材料层，使得鳍结构30A和30B完全嵌入绝缘层中。绝缘层的绝缘材料可包括氧化硅，氮化硅，氧氮化硅(SiON)，SiOCN，SiCN，氟硅玻璃(FSG)，或低介电常数介电材料，可由LPCVD(低压化学气相沉积)、电浆式化学气相沉积或可流动式化学气相沉积而形成。可以在形成绝缘层之后执行退火操作。接着，执行平坦化操作例如化学机械抛光(CMP)方法及/或回蚀方法，使得最上面的第二半导体层25的上表面从绝缘材料层暴露出来。
如图5所示，在一些实施例中，在形成绝缘材料层之前，形成一或多个鳍衬垫层35。鳍衬垫层35由SiN或氮化硅基材料(例如，SiON，SiCN或SiOCN)制成。在一些实施例中，鳍衬垫层35包括形成第一鳍衬垫层35A于基板10与下鳍结构11的侧面上，以及形成第二鳍衬垫层35B在第一鳍衬垫层35A上。在一些实施例中，每个衬垫层的厚度为约1nm和约20nm之间。在一些实施例中，第一鳍衬垫层35A包括氧化硅，并且具有在约0.5nm至约5nm之间的厚度，以及第二鳍衬垫层35B包括氮化硅，并且具有约0.5nm至约5nm之间的厚度。鳍衬垫层35可经由一或多个制程沉积而成，举例来说，物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)，也可使用任何可接受的制程。
接着，如图5所示。凹陷化绝缘材料层以形成隔离绝缘层40，使得鳍结构30的上部暴露出来。借此操作，鳍结构30通过隔离绝缘层40彼此电气隔离，这也称为浅沟槽隔离(STI)。在图5所示的实施例中，凹陷化绝缘材料层直到下鳍结构11的顶部暴露出来。第一半导体层20是牺牲层，随后被部分地去除，以及第二半导体层25随后形成GAA FET的通道层。在其他实施例中，在形成隔离绝缘层40之后，部分地蚀刻第一半导体层20。
如图6A至图6D所示，在形成隔离绝缘层40之后，在鳍结构30A和30B的上部上形成氧化物层45。图6A绘示的立体图，图6B绘示沿X方向的横剖面图。图6C绘示沿Y方向切割鳍结构30A的横剖面图。图6D绘示沿Y方向的切割鳍结构30B横剖面图。
在一些实施例中，通过热氧化制程氧化第一半导体层20和第二半导体层25以形成氧化物层45。在一些实施例中，热氧化制程包括在O2及/或O3的氧化环境中进行。在特定实施例中，在一温度下约800℃至约1000℃执行热制程。在其它实施例中，使用湿氧化制程。在特定实施例中，执行化学氧化制程。
在一些实施例中，通过热氧化，第一半导体层20完全地被氧化成氧化物层45。在其他实施例中，保留第一半导体层20的一部分在鳍结构中。在一些实施例中，剩余的第一半导体层20的宽度在约0.5nm至约2nm的范围内。在一些实施例中，氧化物层45的厚度在约1nm至约5nm的范围内。
当第一半导体层20由SiGe制成，并且第二半导体层25由Si制成时，氧化物层45包括在相应部分的硅-锗氧化物部分和氧化硅部分。在一些实施例中，硅-锗氧化物部分主要设置在相邻的第二半导体层25之间。在一些实施例中，氧化硅部分主要设置在第二半导体层25的侧面上。
在一些实施例中，在形成氧化物层45之后，执行退火操作。在一些实施例中，在一温度下约800℃至约1000℃执行退火制程。
如图7A至图7D所示，形成氧化物层45之后，形成牺牲栅极结构50在具有氧化物层45的鳍结构30A和30B上。图7A绘示一立体图，图7B绘示沿X方向切割牺牲栅极结构的横剖面图。图7C绘示沿Y方向切割鳍结构30A的横剖面图。图7D绘示沿Y方向切割鳍结构30B的横剖面图。
牺牲栅极结构50包括牺牲栅极电极54。在一些实施例中，未形成牺牲栅极介电层。形成牺牲栅极结构50在鳍结构的一部分的上方，其将成为通道区域。牺牲栅极结构50界定GAA FET的通道区域。
形成牺牲栅极结构50，首先通过在鳍结构30A和30B的上方以毯覆式沉积牺牲栅极电极层，使得鳍结构完全嵌入牺牲栅极电极层。牺牲栅极电极层包括硅，例如，多晶硅或非晶硅。在一些实施例中，牺牲栅极电极层的厚度在约100nm至约200nm的范围内。在一些实施例中，牺牲栅极电极层经受平坦化操作。通过化学气相沉积(CVD)，包括低压化学气相沉积(LPCVD)、电浆增强化学气相沉积(PECVD)、物理气相沉积(PVD)、原子层沉积(ALD)、或其它合适的制程来沉积牺牲栅极电极层。随后，在牺牲栅极电极层上形成掩模层56。掩模层56包括一或多个氮化硅(SiN)层和氧化硅层。
接着，对掩模层执行图案化操作以及将牺牲栅极电极层图案化为牺牲栅极结构50，如图7A至7D所示。牺牲栅极结构50包括牺牲栅极电极层54(例如，多晶硅)和掩模层56。
如图7A至图7D所示，通过图案化牺牲栅极结构，在牺牲栅极结构50的相对侧上，部分地暴露出具有第二半导体层25的鳍结构的上部分以及氧化物层45，从而界定源极/漏极(S/D)区域。在本揭露中，源极和漏极可互换使用，并且其结构基本上相同。在图7A至7D中，形成一个牺牲栅极结构50，但牺牲栅极结构的数量不限于一个。在特定实施例中，在Y方向上布置两个或更多的牺牲栅极结构。在特定实施例中，在牺牲栅极结构的两侧上形成一或多个虚设牺牲栅极结构，以改善图案逼真度。
如图8A至图8D所示，形成牺牲栅极结构50之后，形成栅极侧壁间隔物55。图8A绘示一立体图，图8B绘示沿X方向切割牺牲栅极结构50的横剖面图。图8C绘示沿Y方向切割鳍结构30A的横剖面图。图8D绘示沿Y方向C切割鳍结构30B的横剖面图。
为了形成栅极侧壁间隔物55，通过CVD或其他合适的方法保角地形成是为绝缘材料的毯覆层。以保角式方法沉积毯覆层，使得其在垂直表面上具有实质上相同的厚度，例如侧壁，水平表面，和牺牲栅极结构的顶部。在一些实施例中，沉积毯覆层至厚度为约2nm至约20nm。在一些实施例中，毯覆层的绝缘材料为氮化硅基材料，例如SiN，SiON，SiOCN或SiCN以及上述组合。在特定实施例中，绝缘材料是SiOC，SICON及SiCN中的一者。
更进一步，如图8A至8D所示。在牺牲栅极结构的相对侧壁上通过异向蚀刻形成栅极侧壁间隔物55。在形成毯覆层之后，对毯覆层执行异向蚀刻，例如，使用反应式离子蚀刻(RIE)。在异向蚀刻操作期间，从水平表面移除大部分的绝缘材料，留下介电隔离层在垂直表面上，例如，牺牲栅极结构的侧壁及被暴露的鳍结构的侧壁。掩模层56可从侧壁间隔物暴露出。在一些实施例中，随后可以执行等向蚀刻以去除暴露的鳍结构30的上部分的S/D区域的绝缘材料。
随后，通过适当的干式及/或湿式蚀刻操作去除形成在源极/漏极区域中的第二半导体层25周围的氧化物层45。
接着，如图9A至9E所示，形成源极/漏极磊晶层60A和60B。图9A绘示一立体图，图9B绘示沿X方向切割牺牲栅极结构50的横剖面图。图9C绘示沿Y方向切割鳍结构30A的横剖面图。图9D绘示沿Y方向切割鳍结构30B和图2的横剖面图。图9E绘示沿X方向切割源极/漏极区域的横剖面图。
形成包裹在鳍结构30A的S/D区域的第二半导体层25周围的第一S/D磊晶层60A。第一S/D磊晶层60A包括用于p通道FET的一或多层的Si，SiGe和SiGeP。通过CVD、ALD或分子束磊晶(MBE)的磊晶生长方法形成第一S/D磊晶层60A。在一些实施例中，第一S/D磊晶层60A包含硼(B)。形成包裹在鳍结构30B的S/D区域的第二半导体层第25周围的第二S/D磊晶层60B。第二S/D磊晶层60B包括用于n通道FET的一或多层的Si，SiP，SiC和SiCP。通过CVD、ALD或分子束磊晶(MBE)的磊晶生长方法形成第二S/D磊晶层60B。在一些实施例中，分别形成用于p通道FET的第一源极/漏极(S/D)磊晶层60A以及用于n通道FET的第二S/D磊晶层60B。
接着，如图10A至图10F所示，形成第一绝缘衬垫层63，然后形成层间介电质(ILD)层65，然后去除牺牲栅极结构50。图10A绘示一立体图。图10B绘示沿X方向切割通道区域的横剖面图。图10C绘示了沿Y方向切割鳍结构30A的横剖面图。图10D绘示沿Y方向切割鳍结构30B的横剖面图。图10E绘示沿X方向切割源极/漏极区域的横剖面图。图10F绘示沿X方向切割栅极侧壁间隔物55的横剖面图。
第一绝缘衬垫层63由氮化硅基材料制成，例如氮化硅，并且在随后的蚀刻操作中作为第一接触蚀刻停止层(CESL)。用于第一ILD层65的材料包括包含Si，O，C及/或H的化合物，如氧化硅，SICOH和SiOC。有机材料，例如聚合物，可用于第一ILD层65。形成第一ILD层65之后，执行平坦化操作，例如CMP，从而暴露牺牲栅极电极层54。
接着，如图10A至图10F所示，去除牺牲栅极电极层54，并且进一步去除氧化物层45，从而暴露第二半导体层25(半导体纳米线)的通道区域。在去除牺牲栅极结构期间，第一ILD层65保护第一和第二S/D磊晶层60A及60B。可以使用电浆干蚀刻及/或湿蚀刻去除牺牲栅极结构。当牺牲栅极电极层54为多晶硅且第一ILD层65为氧化硅，湿蚀刻剂例如TMAH溶液，可用于选择性地去除牺牲栅极电极层54。随后可以使用电浆干蚀刻及/或湿蚀刻去除氧化物层45。
如图10C，图10D和图10F所示，在一些实施例中，氧化物层45的一部分残留在栅极侧壁间隔物55之下，作为内侧间隔。在一些实施例中，剩余氧化物层45的厚度在约0.2nm至约2nm的范围内。
如图11A至图11G所示，在暴露第二半导体层25的线之后，在鳍结构30A与鳍结构30B中的第二半导体层25的线的周围形成栅极介电层104。图11A绘示一立体图。图11B绘示沿X方向切割通道区域的横剖面图。图11C绘示沿Y方向切割鳍结构30A的横剖面图。图11D绘示沿Y方向切割鳍结构30B中的横剖面图。图11E绘示沿X方向切割源极/漏极区域的横剖面图。图11F绘示沿X方向切割栅极侧壁间隔物55的横剖面图。图11G绘示通道区域的放大视图。
在一些实施例中，栅极介电层104包括一或多个层的介电材料，例如氧化硅，氮化硅，或高k介电材料，其他合适的介电材料，及/或上述组合。高k介电材料的实例包括HfO2，HfSiO，HfSiON，HfTaO，HfTiO，HfZrO，氧化锆，氧化铝，氧化钛，二氧化铪-氧化铝(HfO2-Al2O3)合金，其他合适的高k值介电材料及/或其组合。在一些实施例中，在通道层和栅极介电层104之间形成界面层102。可以通过CVD，ALD或任何合适的方法形成栅极介电层104。在一个实施例中，使用一个高度保角沉积制程形成栅极介电层104，例如ALD，以确保形成的栅极介电层具有围绕每个通道的均匀厚度。在一个实施例中，栅极介电层104的厚度在约1nm至约6nm范围内。
更进一步，在栅极介电质层104上形成一个栅电极层108如图11A至图11G所示。在一些实施例中，在栅极介电质层104上方形成一个栅电极层108以围绕每个通道层。栅电极108包括导电材料的一或多个层，例如多晶硅，铝，铜，钛，钽，钨，钴，钼，氮化钽，硅化镍，硅化钴，TiN，WN，TiAl，TiAlN，TaCN，TaC，TaSiN，金属合金，其他合适的材料及/或上述组合。可使用CVD、ALD、电镀、或其他合适的方法形成栅电极层108。栅电极层也沉积在第一ILD层65的上表面上。形成栅极介电层和栅电极层在第一ILD层65上，然后使用平坦化，例如，CMP，直到第一ILD层65露出。
在特定实施例中，一或多个功函数调整层106设置在栅极介电质层104和栅电极层108之间。功函数调整层106由导电材料制成，例如单层TiN，TaN，TaAlC，TiC，TaC，Co，Al，TiAl，HfTi，TiSi，TaSi或TiAlC，或者这些材料的两层或更多层的复层。对于n通道FET，使用TaN，TaAlC，TiN，TiC，Co，TiAl，HfTi，TiSi和TaSi中的一或多者作为功函数调整层。可以通过ALD，PVD，CVD，电子束蒸发或其他合适的制程形成功函数调整层106。再者，可使用不同的金属层分别形成用于n通道FET和p通道FET的功函数调整层106。
随后，在第一ILD层65上形成第二绝缘衬垫层110，并且在第二绝缘层110上形成第二ILD层115，如图12A至图12E所示。图12A绘示一立体图。图12B绘示沿X方向切割通道区域的横剖面图。图12C绘示沿Y方向切割鳍结构30A的横剖面图。图12D绘示沿Y方向切割鳍结构30B的横剖面图，以及图12E绘示沿X方向切割源极/漏极区域的横剖面图。
第二绝缘衬垫层110由含硅氮化物的材料制成，例如氮化硅，并且在随后的蚀刻操作用作第二CESL。用于第二ILD层115的材料包括Si，O，C及/或H的化合物，例如氧化硅，SiCOH和SiOC。有机材料例如聚合物，可以用于第二ILD层110。在形成第二ILD层110之后，执行平坦化操作，例如CMP。
接着，如图12A至图12E所示，形成接触开口以分别暴露源极/漏极磊晶层60A和60B。接触开口中填充有一或多个层的导电材料，从而形成S/D接触。在接触开口中和接触开口上形成一或多层的导电材料，然后执行平坦化操作，例如CMP操作，以形成S/D接触。在一些实施例中，S/D接触包括衬垫层122和主体层120。衬垫层122是阻挡层及/或胶(粘合)层。在一些实施例中，在源极/漏极磊晶层60A和60B上形成Ti层，并且在Ti层上形成TiN或TaN层，作为衬垫层122。主体层120包括一或多层Co，Ni，W，Ti，Ta，Cu和Al，或任何其他合适的材料。如图12A与12E所示，S/D导电接触分别环绕源极/漏极磊晶层60A和60B。
在一些实施例中，当第一半导体层由SiGe制成且第二半导体层由Si制成时，在栅极侧壁间隔物55下方，氧化物层45包括硅-锗氧化物部分和氧化硅部分。在一些实施例中，在栅极侧壁间隔物55下方，硅-锗氧化物部分主要设置在相邻的第二半导体层25之间，并且氧化硅部分主要设置在第二半导体层25的侧面上。
在一些实施例中，在栅极侧壁间隔物下方，第二半导体层25具有横截面，该横截面具有两个垂直侧面，V形底侧与反V形顶侧。在其他实施例中，在栅极侧壁间隔物下方，第二半导体层25具有横截面，该横截面具有两个垂直侧面，向上突出的顶侧和向下突出的底侧。在一些实施例中，在栅极侧壁间隔物下方，第二半导体层25中最上面的一个具有横截面，该横截面具有两个垂直侧面，平坦的顶侧和向下突出的底侧。
应当理解的是，GAA FETs经历进一步的互补式金氧半场效晶体管(CMOS)制程以形成各种特征，例如接触/通孔，互连金属层，介电层，钝化层等。
图13A至图16E绘示根据本揭露另一实施例的用于制造GAA FET元件的连续制程。应当理解，可以在图13A至图16E所示的过程之前，期间和之后提供附加操作。对于该方法的额外实施例，如下所述的部分的操作可以被替换或消除。操作/过程的顺序可以是可互换的。
形成如图9A至图9E所示的结构之后，n通道区域包括被掩模层所覆盖的鳍结构30A，掩模层可为，例如氮化硅层，以保护n通道区域。然后，类似于在图10A至图10E说明的操作，第二半导体层25在通道区域中暴露出来。图13A绘示用于p通道FET的通道区域中的第二半导体层25的放大视图。然后，如图13B所示，在第二半导体层25上方形成第三半导体层26。在一些实施例中，第三半导体层由Si1-zGez制成，其中0.2≤z≤1.0。在其它实施例中，0.3≤z≤0.5。在一些实施例中，第三半导体层26的厚度在约0.2nm至约2nm的范围内。
在形成第三半导体层26之后，执行热制程以形成第二半导体层25(例如，Si)和第三半导体层26(例如，硅锗)的合金27。合金27为Si1-wGew，其中0.3≤w≤0.7在一些实施例中，以及0.4≤z≤0.6在其它实施例中。在一些实施例中，在900℃至100C℃下执行热制程。在一些实施例中，使用快速热退火(RTA)。在特定实施例中，使用激光退火。
在一些实施例中，在热制程之前，形成氧化物覆盖层于第三半导体层26上，以及热制程之后，去除氧化物覆盖层。
随后，通过盖层保护具有合金半导体线27的p通道区域，然后加工n通道区域以暴露出通道区域中的第二半导体层25。接着，去除p通道区域的盖层，从而获得如图14A至图14F所示的结构。图14A绘示一立体图，图14B绘示沿X方向切割通道区域的横剖面图。图14C绘示沿Y方向的切割鳍结构30A的横剖面图。图14D绘示沿Y方向切割鳍结构30B的横剖面图，图14E绘示沿X方向切割源极/漏极区域的横剖面图。图14F绘示沿X方向切割栅极侧壁间隔物55的横剖面图。如图14B至图14F所示，在源极/漏极区域与栅极侧壁间隔物下面，保留第二半导体层25。
如图15A至图15F所示，类似于图11A至图11G，第二半导体层25的线在p通道区域和n通道区域中暴露之后，在第二半导体层25的线的周围形成栅极介电层104。图15A绘示一立体图。图15B绘示沿X方向切割通道区域的横剖面图。图15C绘示一个沿Y方向的切割鳍结构30A的横剖面图。图15D绘示沿Y方向切割鳍结构30B的横剖面图，图15E显示沿X方向切割源极/漏极区域的横剖面图，以及图15F绘示沿X方向切割栅极侧壁间隔物55的横剖面图。
随后，类似于图12A至图12E，如图16A至图16E所示，形成源极/漏极接触120。图16A绘示一立体图。图16B绘示沿X方向切割通道区域的横剖面图。图16C绘示沿Y方向切割鳍结构30A的横剖面图，图16D绘示沿Y方向切割鳍结构30B的横剖面图，以及图16E绘示沿X方向切割源极/漏极区域的横剖面图。
在一些实施例中，在栅极侧壁间隔物55下方，氧化物层45环绕半导体线25的Si部分。
应当理解的是，GAA FETs经历进一步的CMOS制程以形成各种特征，例如接触/通孔，互连金属层，介电层，钝化层等。
图17A至图19E绘示根据本揭露另一实施例的用于制造GAA FET元件的连续制程。应当理解，可以在图17A至图19E所示的制程之前，期间和之后提供额外操作。对于该方法的额外实施例，如下所述部分的操作可以被替换或消除。操作/过程的顺序可以是可互换的。
形成如图8A至8D所示的结构之后，如图17A至图17D所示，鳍结构的源极/漏极区域包括被移除的第二半导体层25和氧化物层45。图17A绘示一立体图。图17B绘示沿X方向切割通道区域的横剖面图。图17C绘示一个沿Y方向切割鳍结构30A的横剖面图。图17D绘示沿Y方向切割鳍结构30B的横剖面图。
接着，如图18A至图18D所示，形成源极/漏极磊晶层62A和62B。图18A绘示一立体图，图18B绘示沿X方向切割牺牲栅极结构50的横剖面图。图18C绘示沿着Y方向切割鳍结构30A的横剖面图。图18D绘示沿着Y方向切割鳍结构30B的横剖面图。
在鳍结构30A的S/D区域中的第二半导体层25的端面(End faces)上形成第一S/D磊晶层62A。第一S/D磊晶层62A包括用于p通道FET的一或多个层的Si，SiGe和SiGeP。通过CVD、ALD或分子束磊晶(MBE)的磊晶生长法形成第一S/D磊晶层62A。在一些实施例中，第一S/D磊晶层62A包含硼(B)。在鳍结构35B的S/D区域中的第二半导体层25的端面上形成第二S/D磊晶62B。第二S/D磊晶层62B包括用于n通道FET的一或多层的Si，SiP，SiC和SiCP。通过CVD、ALD或分子束磊晶(MBE)的磊晶生长方法形成第二S/D磊晶层62B。在一些实施例中，分别形成用于p通道FET的第一源极/漏极(S/D)磊晶层62A以及用于n通道FET的第二S/D磊晶层62B。
随后，通过如图10A至图12E所示的相同或类似的操作，形成源极/漏极接触120如图19A至图19E所示。图19A绘示一立体图。图19B绘示沿X方向切割通道区域的横剖面图。图19C绘示沿Y方向切割鳍结构30A的横剖面图。图19D绘示沿Y方向切割鳍结构30B的横剖面图，图19E绘示沿X方向切割源极/漏极区域的横剖面图。
应当理解的是，GAA FETs经历进一步的CMOS制程以形成各种特征，例如接触/通孔，互连金属层，介电层，钝化层等。
图20A至图20D绘示栅极侧壁间隔物55下方的鳍结构的各种结构。在一些实施例中，在第一半导体层20的氧化制程中，第一半导体层20未被完全氧化并且保留第一半导体层20的一部分。因此，在形成栅极结构之后，第一半导体层20的剩余部分存在栅极侧壁间隔物55之下，如图20A所示。氧化物层45连续地设置在第二半导体层25和剩余的第一半导体层20的侧面上。
在其他实施例中，当在栅极空间中去除氧化物层45时，实质上完全去除第二半导体层25之间的氧化物层。因此，如图20B所示，在形成栅极结构之后，在栅极侧壁间隔物55下方的第二半导体层之间形成气隙29。氧化物层45非连续地设置在第二半导体层25的侧面上。
再者，如图20C所示，在一些实施例中，在气隙填充一或多个介电材料。在特定实施例中，在第二半导体层25或合金半导体层27的上表面和下表面上形成界面层102，以及栅极介电层104填充在界面层102之间的空间如图20C所示。在其他实施例中，如图20D所示，界面层102连接相邻的第二半导体层25，以及在界面层102上形成栅极介电层104。氧化物层45非连续地设置在第二半导体层25的侧面上。
与现有制程相比，本文所描述各种实施例或示例提供了多种优点。例如，可以通过自对准的方式形成内侧间隔。此外，通过单通道磊晶制程形成Si纳米线(nano-wire)通道和SiGe纳米线通道。因此，可以改善GAA FETs的性能并降低制造成本。
应当理解的是，并不是所有的优点都已经在本揭示内容中被讨论，且对于所有的实施例也不需要特定的优点，并且其它实施例或示例可以提供不同的优点。
根据本揭露内容实施例，一种半导体元件的制造方法，形成鳍结构，具有下鳍结构及设置在下鳍结构上的上鳍结构。上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层。部分地蚀刻第一半导体层以减小第一半导体层的宽度。形成氧化物层在上鳍结构上。形成牺牲栅极结构在具有氧化物层的上鳍结构上。形成源极/漏极磊晶层在鳍结构的源极/漏极区域上。去除牺牲栅极结构以形成栅极空间。去除氧化物层以暴露栅极空间中的第二半导体层，以及形成栅极结构在栅极空间中的第二半导体层的周围。在前述和以下实施例中的一或多个中，通过热氧化形成氧化物层。在前述和以下实施例中的一或多个中，在热氧化之后，执行退火操作。在前述和以下实施例中的一或多个中，在800℃至1000℃下执行退火操作。在前述和以下实施例中的一或多个中，通过热氧化使经蚀刻的第一半导体层完全地氧化。在前述和以下实施例中的一或多个中，通过热氧化使经蚀刻的第一半导体层部分地氧化。在前述和以下实施例中的一或多个中，在栅极空间中去除氧化物层之后，在栅极空间中去除第一半导体层。在前述和以下实施例中的一或多个中，在形成源极/漏极磊晶层之前，去除源极/漏极区域中的氧化物层。在前述和以下实施例中的一或多个中，源极/漏极磊晶层环绕源极/漏极区域中的第二半导体层。在前述和以下实施例中的一或多个中，保留氧化物层的一部分在源极/漏极磊晶层与栅极结构之间。在前述和以下实施例中的一或多个中，在部分蚀刻第一半导体层之后，形成隔离绝缘层在下鳍结构的周围。在前述和以下实施例中的一或多个中，牺牲栅极结构包括牺牲栅极电极，以及牺牲栅极电极与氧化物层接触。在前述和以下实施例中的一或多个中，第一半导体层由SiGe制成以及第二半导体层由Si制成。
根据本揭露内容实施例，一种半导体元件的制造方法，形成鳍结构，具有下鳍结构及设置在下鳍结构上的上鳍结构，上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层。部分地蚀刻第一半导体层以减小第一半导体层的宽度。形成氧化物层在上鳍结构上。形成牺牲栅极结构在具有氧化物层的上鳍结构上。在鳍结构的源极/漏极区域上形成源极/漏极磊晶层。去除牺牲栅极结构以形成栅极空间。去除栅极空间中的氧化物层以暴露栅极空间中的第二半导体层。在暴露的每个第二半导体层上形成第三半导体层。通过混合第三半导体层和第二半导体层以形成多个通道线。以及形成栅极结构在栅极空间中的通道线的周围。在前述和以下实施例中的一或多个中，第一半导体层由SiGe制成，第二半导体层由Si制成，以及第三半导体层由SiGe或Ge制成。在前述和以下实施例中的一或多个中，通过热氧化形成氧化物层。在前述和以下实施例中的一或多个中，通过热氧化使经蚀刻的第一半导体层完全地氧化。在前述和以下实施例中的一或多个中，保留氧化物层的一部分在源极/漏极磊晶层与栅极结构之间。
根据本揭露内容实施例，一种半导体元件的制造方法，形成鳍结构，具有下鳍结构及设置在下鳍结构上的上鳍结构，上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层。部分地蚀刻第一半导体层以减小第一半导体层的宽度。形成氧化物层在上鳍结构上。形成牺牲栅极结构在具有氧化物层的上鳍结构上。在上鳍结构的源极/漏极区域，移除其未被牺牲栅极结构覆盖之处。形成源极/漏极磊晶层以接触第二半导体层。移除牺牲栅极结构以形成栅极空间。去除氧化物层以暴露栅极空间中的第二半导体层。形成栅极结构在栅极空间中的第二半导体层的周围。在前述和以下实施例中的一或多个中，保留氧化物层的一部分在源极/漏极磊晶层与栅极结构之间。
根据本揭露内容实施例，一种半导体元件包含下鳍结构设置在基板上，多个半导体线设置在下鳍结构上，栅极结构设置在半导体线的通道区域上，多个栅极侧壁间隔物设置在栅极结构的相对的侧面上，以及源极/漏极磊晶层。与栅极侧壁间隔物不同的材料制成的介电层，包裹在栅极侧壁间隔物之下的半导体线。在前述和以下实施例中的一或多个中，栅极侧壁间隔物由由氮化硅基材料制成，以及该介电层由Si和Ge中的至少一者的氧化物制成。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，至少一个半导体线具有两个垂直侧面，V形底面和倒V形顶面的横截面。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，至少一个半导体线具有横截面，该横截面具有两个垂直侧面，向上突出的顶侧和向下突出的底侧。在前述和以下实施例中的一或多个中，半导体线中最上面的一个，具有与剩余的半导体线不同的横截面。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，最上面的一个半导体线具有横截面，该横截面具有两个垂直侧面，平坦的顶侧和向下突出的底侧，其余的是半导体线的横截面具有两个垂直侧面，一个向上突出的顶侧和一个向下突出的底侧。在前述和以下实施例中的一或多个中，介电层设置在源极/漏极磊晶层和栅极结构的栅极介电层之间。在前述和以下实施例中的一或多个中，源极/漏极磊晶层包裹半导体线的源极/漏极区域。在前述和以下实施例中的一或多个中，源极/漏极磊晶层与半导体线的横向端面接触。在前述和以下实施例中的一或多个中，半导体线的通道区域由第一半导体材料制成，并且半导体线的源极/漏极区域由不同于第一半导体材料的第二半导体材料制成。在前述和以下实施例中的一或多个中，第一半导体材料是SiGe，第二半导体材料是Si。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，介电层包裹由第二材料制成的半导体线的一部分。在前述和以下实施例中的一或多个中，介电层包括硅-锗氧化物部分和氧化硅部分。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，硅-锗氧化物部分设置在相邻的半导体线之间。在前述和以下实施例中的一或多个中，在栅极侧壁间隔物下方，氧化硅部分设置在半导体线的侧面上。
在另一例示性态样中，一种半导体元件包括下鳍结构，设置在基板上，多个半导体线设置在下鳍结构上，栅极结构设置在半导体线的通道区域的上方，多个栅极侧壁间隔物设置在栅极结构的相对的侧面上，以及源极/漏极磊晶层。与栅极侧壁间隔物不同的材料制成的介电层，设置在栅极侧壁间隔物之下的半导体线的侧面上。在前述和以下实施例中的一或多个中，气隙设置在栅极侧壁间隔物下方的相邻半导体线之间。在前述和以下实施例中的一或多个中，一或多层介电材料设置在栅极侧壁间隔物下方的相邻半导体线之间。在前述和以下实施例中的一或多个中，一或多层介电材料中的至少一层是高k介电材料。
根据本揭露的另一例示性态样，一种半导体元件包括设置在基板下的鳍结构，多个半导体线设置在下鳍结构上，栅极结构设置在半导体线的通道区域上，多个栅极侧壁间隔物设置在栅极结构的多个相对的侧面上，以及源极/漏极磊晶层。与栅极侧壁间隔物不同的材料制成的介电层，设置在栅极侧壁间隔物下方的半导体线的侧面上，以及与半导体线不同的半导体材料，设置在栅极侧壁间隔物下方的相邻半导体线之间。
前述内容概述了许多实施例或示例的特征，使本技术领域中具有通常知识者可以从各方面更佳了解本揭露。本技术领域中具有通常知识者应可理解，且轻易地以本揭露为基础来设计或修饰其他制程及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应理解这些相等的结构并未背离本揭露的发明精神与范围。在不背离本揭露的发明精神及范围的情况下，可对本揭露进行各种改变，替换及变更。

Claims (10)

1.一种半导体元件的制造方法，其特征在于，包括：
形成一鳍结构，具有一下鳍结构以及设置在该下鳍结构上的一上鳍结构，该上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层；
部分地蚀刻该些第一半导体层以减小该些第一半导体层的多个宽度；
形成一氧化物层在该上鳍结构上；
形成一牺牲栅极结构在具有该氧化物层的该上鳍结构上；
形成一源极/漏极磊晶层在该鳍结构的一源极/漏极区域上；
去除该牺牲栅极结构以形成一栅极空间；
去除该氧化物层以暴露该栅极空间中的该些第二半导体层；以及
形成一栅极结构在该栅极空间中的该些第二半导体层的周围。
2.根据权利要求1所述的半导体元件的制造方法，其特征在于，在形成该源极/漏极磊晶层之前，去除该源极/漏极区域中的该氧化物层。
3.根据权利要求2所述的半导体元件的制造方法，其特征在于，该源极/漏极磊晶层环绕该源极/漏极区域中的该些第二半导体层。
4.一种半导体元件的制造方法，其特征在于，包括：
形成一鳍结构，具有一下鳍结构以及设置在该下鳍结构上的一上鳍结构，该上鳍结构包括交替堆叠的多个第一半导体层和多个第二半导体层；
部分地蚀刻该些第一半导体层以减小该些第一半导体层的多个宽度；
形成一氧化物层在该上鳍结构上；
形成一牺牲栅极结构在具有该氧化物层的该上鳍结构上；
形成一源极/漏极磊晶层在该鳍结构的一源极/漏极区域上；
去除该牺牲栅极结构以形成一栅极空间；
去除该栅极空间中的该氧化物层以暴露该栅极空间中的该些第二半导体层；
形成一第三半导体层在每个暴露的该些第二半导体层上；
通过混合该些第三半导体层和该些第二半导体层形成多个通道线；以及
形成一栅极结构在该栅极空间中的该些通道线的周围。
5.根据权利要求4所述的半导体元件的制造方法，其特征在于：
该些第一半导体层由SiGe制成；
该些第二半导体层由Si制成；以及
该第三半导体层由SiGe或Ge制成。
6.根据权利要求4所述的半导体元件的制造方法，其特征在于，通过一热氧化形成该氧化物层。
7.根据权利要求4所述的半导体元件的制造方法，其特征在于，通过该热氧化使经该蚀刻的该些第一半导体层完全地氧化。
8.根据权利要求4所述的半导体元件的制造方法，其特征在于，保留该氧化物层的一部分在该源极/漏极磊晶层与该栅极结构之间。
9.一种半导体元件，其特征在于，包括：
一下鳍结构设置在一基板上；
多个半导体线设置在该下鳍结构上；
一栅极结构设置在该些半导体线的多个通道区域上；
多个栅极侧壁间隔物设置在该栅极结构的多个相对的侧面上；以及
一源极/漏极磊晶层；
其中，一介电层是由与该些栅极侧壁间隔物不同的一材料制成，包裹在该些栅极侧壁间隔物之下的该些半导体线的周围。
10.根据权利要求9所述的半导体元件，其特征在于，该些栅极侧壁间隔物由一氮化硅基材料制成，以及该介电层由Si和Ge中的至少一者的一氧化物制成。
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