CN107017205A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN107017205A
CN107017205A CN201611042625.XA CN201611042625A CN107017205A CN 107017205 A CN107017205 A CN 107017205A CN 201611042625 A CN201611042625 A CN 201611042625A CN 107017205 A CN107017205 A CN 107017205A
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semiconductor layer
fin structure
layer
drain
source
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CN107017205B (zh
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陈奕升
吴政宪
叶致锴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了半导体器件及其制造方法。半导体器件包括设置在衬底上方的第一沟道层、设置在衬底上方的第一源极/漏极区域、设置在每个第一沟道层上并且包裹每个第一沟道层的栅极介电层以及设置在栅极介电层上并且包裹每个第一沟道层的栅电极层。第一沟道层的每个均包括由第一半导体材料制成的半导体线。半导体线延伸至第一源极/漏极区域。第一源极/漏极中的半导体线由第二半导体材料包裹围绕。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2015年11月30日提交的美国临时专利申请第62/261，267号的优先权，其全部内容结合于此作为参考。
技术领域
本发明的实施例涉及半导体集成电路，并且更具体地涉及具有全环栅结构的半导体器件及其制造方法。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如多栅极鳍式场效应晶体管(FET)(包括fin FET(Fin FET)和全环栅(GAA)FET)的三维设计的发展。在Fin FET中，栅电极邻近于沟道区域的三个侧面，同时栅极介电层介于栅电极和沟道层之间。因为栅极结构在三个侧面上围绕(包裹)鳍，因此该晶体管实质上具有控制流经鳍或沟道区域的电流的三个栅极。不幸地，第四侧，该沟道的底部远离栅电极因此不在栅极的紧密控制之下。相反地，在GAA FET中，沟道区域的所有侧面均由栅电极围绕，由于更陡的亚阈值摆幅(SS)和更小的漏极感应势垒降低(DIBL)，这使得沟道区域中的耗尽更为充分并且引起了更小的短沟道效应。
随着晶体管尺寸按比例不断缩小至亚10至15nm技术节点，需要GAA FET的进一步改进。
发明内容
根据本发明的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层 的堆叠结构；将所述堆叠结构图案化成鳍结构；在所述鳍结构上方形成牺牲栅极结构，从而使得所述牺牲栅极结构覆盖所述鳍结构的部分而所述鳍结构的剩余部分保持暴露，所述剩余部分为源极/漏极区域并且所述鳍结构中由所述牺牲栅极结构覆盖的所述部分为沟道区域；去除所述鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；使所述沟道区域中的所述第二半导体层在垂直于所述第一方向的第二方向上向内朝着所述牺牲栅极结构凹进；在所述源极/漏极区域中的暴露的所述第一半导体层上形成外延源极/漏极结构，从而使得所述外延源极/漏极结构包裹在所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；去除所述牺牲栅极结构以暴露所述鳍结构的所述沟道区域；在去除所述牺牲栅极结构之后，去除所述鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述沟道区域中的所述第一半导体层；以及在所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
根据本发明的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层的堆叠结构；将所述堆叠结构图案化成第一鳍结构和第二鳍结构；在所述第一鳍结构和所述第二鳍结构上方形成牺牲栅极结构，从而使得所述牺牲栅极结构覆盖所述第一鳍结构的部分和所述第二鳍结构的部分，而所述第一鳍结构和所述第二鳍结构的剩余部分保持暴露，所述剩余部分分别为所述第一鳍结构和所述第二鳍结构的源极/漏极区域，并且所述第一鳍结构的由所述牺牲栅极结构覆盖的所述部分为所述第一鳍结构的沟道区域以及所述第二鳍结构的由所述牺牲栅极结构覆盖的所述部分为所述第二鳍结构的沟道区域；用第一保护层覆盖所述第二鳍结构；去除所述第一鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述第一鳍结构的所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；使所述第一鳍结构的所述沟道区域中的所述第二半导体层在垂直于所述第一方向的第二方向上向内朝着所述牺牲栅极结构凹进；在所述第一鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层上形成第一外延源极/漏极结构，从而 使得所述第一外延源极/漏极结构包裹在所述第一鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；去除所述第一鳍结构上方的所述牺牲栅极结构以暴露所述第一鳍结构的所述沟道区域；在去除所述牺牲栅极结构之后，去除所述第一鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第一鳍结构的所述沟道区域中的所述第一半导体层；以及在所述第一鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
根据本发明的又一方面，提供了一种半导体器件，包括：第一沟道层，设置在衬底上方；第一源极/漏极区域，设置在所述衬底上方；栅极介电层，设置在所述第一沟道层的每个上并且包裹所述第一沟道层的每个；以及栅电极层，设置在所述栅极介电层上并且包裹所述第一沟道层的每个，其中：所述第一沟道层的每个均包括由第一半导体材料制成的半导体线；所述半导体布线延伸至所述第一源极/漏极区域，以及所述第一源极/漏极中的所述半导体线由第二半导体材料包裹围绕。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图31示出了根据本发明的一个实施例的用于制造GAA FET器件的示例性顺序工艺。
图32A至图35B示出了根据本发明的其它实施例的用于制造GAA FET器件的示例性工艺。
图36至图39B示出了根据本发明的其它实施例的用于制造GAA FET器件的示例性工艺。
图40是根据本发明的各个实施例的示出S/D结构和沟道蚀刻工艺的组合的表。
具体实施方式
应该理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件期望的性质。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。为了简单和清楚的目的，各个部件可以以任意比例绘制。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。此外，术语“由…制成”可以意味着“包括”或“由…组成”。
图1至图31是根据本发明的一个实施例的用于制造GAA FET器件的示例性顺序工艺。应该明白，可以在图1至图31所示的工艺之前、期间和/或之后提供额外的操作，并且对于方法的额外的实施例，可以替换或消除以下所描述的一些操作。操作/工艺的顺序可以互换。
如图1所示，在衬底10上方形成堆叠的半导体层。堆叠的半导体层包括第一半导体层20和第二半导体层25。
在一个实施例中，衬底10包括至少在它的表面部分上的单晶半导体层。衬底10可以包括单晶半导体层，诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在这个实施例中，衬底10由Si制成。
衬底10可以包括在它的表面区域中的一个或多个缓冲层(未示出)。该缓冲层可以用于将晶格常数从衬底的晶格常数逐渐改变至源极/漏极区域的晶格常数。在本发明中，源极和漏极互换使用并且基本没有结构的不 同。术语“源极/漏极”(S/D)指的是源极和漏极的一个。可以由外延生长单晶半导体材料(诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP)形成缓冲层。在特定实施例中，衬底10包括在硅衬底10上外延生长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从最底缓冲层的30原子百分比的锗增大至最顶缓冲层的70原子百分比的锗。
第一半导体层20和第二半导体层25由具有不同晶格常熟的材料制成并且可以包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP的一层或多层。
在一些实施例中，第一半导体层20和第二半导体层25由Si、Si化合物、SiGe、Ge或Ge化合物制成。在一个实施例中，第一半导体层20是Si1-xGex(其中，x大于约0.3)或Ge(x＝1.0)并且第二半导体层25是Si或Si1-yGey(其中，y小于约0.4)，并且x＞y。在本发明中，“M”化合物或“M基化合物”意味着化合物的主体是M。
在另一实施例中，第二半导体层25是Si1-yGey(其中，y大于约0.3)或Ge，并且第一半导体层20是Si或Si1-xGex(其中，x小于约0.4)，并且x＜y。在又一实施例中，第一半导体层20由Si1-xGex制成，其中，x在约0.3至约0.8的范围内，并且第二半导体层25由Si1-xGex制成，其中，x在约0.1至约0.4的范围内。在本发明的一个实施例中，第一半导体层20由Si1-xGex制成，其中，0.1＜x＜0.9(此后称为SiGe)，并且第二半导体层25由Si制成。
在图1中，设置了第一半导体层20的六个层和第二半导体层25的六个层。然而，层数不限于六个，并且可以小到1(每层)。在一些实施例中，形成第一半导体层和第二半导体层的每个的2至10层。通过调整堆叠层的数量，可以调整GAA FET器件的驱动电流。
在衬底10上方外延形成第一半导体层20和第二半导体层25。第一半导体层20的厚度可以等于或大于第二半导体层25的厚度，并且在一些实施例中，在约5nm至约50nm的范围内，并且在其它实施例中，在约10nm至约30nm的范围内。在一些实施例中，第二半导体层25的厚度在约5nm 至约30nm的范围内，并且在其它实施例中，在约10nm至约20nm的范围内。每个第一半导体层20的厚度可以相同或可以改变。
在一些实施例中，底部第一半导体层(距离衬底10最近的层)比其余的第一半导体层都厚。在一些实施例中，底部第一半导体层的厚度在约10nm至约50nm的范围内，并且在其它实施例中，在约20nm至约40nm的范围内。
下一步，如图2所示，在堆叠层上方形成掩模层30。在一些实施例中，掩模层30包括第一掩模层32、第二掩模层34和第三掩模层36。第一掩模层32是由氧化硅制成的垫氧化物层(可以通过热氧化形成)。第二掩模层34由氮化硅(SiN)制成并且第三掩模层36由氧化硅制成，通过包括低压CVD(LPCVD)和等离子体增强CVD(PECVD)的化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或其它合适的工艺形成第二掩模层34和第三掩模层36。通过使用包括光刻和蚀刻的图案化操作将掩模层30图案化成掩模图案。
下一步，如图3所示，通过使用图案化掩模层来图案化第一半导体层20和第二半导体层25的堆叠层，从而该堆叠层形成为在Y方向上延伸的鳍结构Fn和Fp。在随后的制造操作中，鳍结构Fn用于形成n-型FET并且鳍结构Fp用于形成p-型FET。每个鳍结构均包括底层15，该底层15是蚀刻的衬底的部分。
在一些实施例中，鳍结构沿着X方向的宽度W1在约5nm至约40nm的范围内，并且在其它实施例中，在约6nm至约15nm的范围内。鳍结构沿着Z方向的高度H1在约30nm至约200nm的范围。
在形成鳍结构之后，在衬底上方形成包括一层或多层绝缘材料的隔离绝缘层50，从而使得鳍结构完全地嵌入在隔离绝缘层50内。用于隔离绝缘层50的绝缘材料可以包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)或低K介电材料。在隔离绝缘层50的形成之后，可以实施退火操作。之后，如图4所示，实施诸如化学机械抛光(CMP)方法和/或回蚀方法的平坦化操作，从而使得垫氧化物层32的上表面从绝 缘材料层处暴露。在一些实施例中，暴露了鳍结构的上表面。
在一些实施例中，如图4所示，在图3的结构上方形成第一衬垫层42并且在第一衬垫层42上方进一步形成第二衬垫层44。第一衬垫层42由氧化硅或氧化硅基材料制成并且第二衬垫层44由SiN或氮化硅基材料制成。在一些实施例中，第二衬垫层44由氧化硅或氧化硅基材料制成并且第一衬垫层42由SiN或氮化硅基材料制成。
之后，如图5所示，使隔离绝缘层50凹进以部分地暴露鳍结构的部分。如图5所示，暴露的鳍结构Fp和Fn都包括第一半导体层20P和20N以及第二半导体层25P和25N的堆叠结构。
如图5所示，最底第一半导体层完全地从隔离绝缘层50处暴露。在其它实施中，最底第一半导体层部分地嵌入在隔离绝缘层50内。
在暴露鳍结构Fp和Fn的上部(堆叠层部分)之后，在暴露的鳍结构上方形成牺牲栅极结构。
通过在鳍结构上方第一毯式沉积牺牲栅极介电层75(例如，见图12B)来形成牺牲栅极结构。牺牲栅极介电层包括氧化硅、氮化硅或氮氧化硅的一层或多层。在一些实施例中，牺牲栅极介电层的厚度在约1nm至约5nm的范围内。之后，在牺牲栅极介电层和鳍结构上方毯式沉积牺牲栅电极层70，从而使得鳍结构完全地嵌入在牺牲栅电极层70内。牺牲栅电极层包括硅，诸如多晶硅或非晶硅。在一些实施例中，牺牲栅电极层的厚度在约100nm至约200nm的范围内。在一些实施例中，牺牲栅电极层经受平坦化操作。使用CVD(包括LPCVD和PECVD)、PVD、ALD或其它合适的工艺来沉积牺牲栅极介电层和牺牲栅电极层。
随后，如图6所示，在牺牲栅电极层70上方形成掩模层71。掩模层71包括垫SiN层72和氧化硅掩模层74。
下一步，如图7所示，对掩模层71实施图案化操作并且将牺牲栅电极层图案化为牺牲栅极结构G1至G5。图7示出了在暴露的鳍结构上方形成牺牲栅极结构之后的结构。在鳍结构中将变成沟道区域的部分上方形成牺牲栅极结构。牺牲栅极结构限定了GAA FET的沟道区域。此外，通过图案化牺牲栅极结构，部分地暴露了第一半导体层和第二半导体层在牺牲栅极 结构的相对两侧的堆叠层以作为源极/漏极(S/D)区域。在本发明中，源极和漏极互换使用并且它们的结构基本相同。
在图7所示的一个实施例中，在鳍结构Fp和Fn上方形成牺牲栅极结构G1，而仅在鳍结构Fp上方形成牺牲栅极结构G2和G3并且仅在鳍结构Fn上方形成牺牲栅极结构G4和G5。牺牲栅极结构的配置不限于图7。在一些实施例中，牺牲栅电极层70的宽度在约5nm至约25nm的范围内。
在形成牺牲栅极结构之后，如图8所示，通过使用CVD或其它合适的方法共形地形成用于侧壁间隔件的绝缘材料的毯式层77。图8是对应于图7的线X1-X1(G1和G3、G5之间)的切割图。毯式层77以共形的方式沉积，从而使得毯式层77在牺牲栅极结构的垂直面(诸如侧壁)、水平面和顶面上形成为具有基本相等的厚度。在一些实施例中，毯式层77沉积有约2nm至约10nm的范围内的厚度。在一个实施例中，毯式层77的绝缘材料是氮化硅基材料，诸如SiN、SiON、SiOCN或SiCN和它们的组合。
此外，如图9所示，在牺牲栅极结构的相对侧壁上形成侧壁间隔件76。在形成毯式层77之后，例如，使用反应离子蚀刻(RIE)对毯式层77实施各向异性蚀刻。在各向异性蚀刻工艺期间，从水平面去除大多数绝缘材料，留下垂直面(诸如牺牲栅极结构的侧壁和暴露的鳍结构的侧壁)上的介电间隔件层。掩模层74可以从侧壁间隔件暴露。在一些实施例中，如图9所示，随后实施各向同性蚀刻以从暴露的鳍结构Fn和Fp的侧壁处去除绝缘材料。在其它实施例中，部分地去除位于鳍结构的侧壁上的绝缘材料。在一些实施例中，各向同性蚀刻是湿蚀刻工艺。在一些实施例中，在形成侧壁间隔件76之后，G1与G2、G2或G1与G4和G5之间的间隔在约5nm至约25nm的范围内。
随后，如图10所示，由保护层55覆盖包括鳍结构Fn的n-型FET区域。在一些实施例中，保护层55由SiN制成。可以通过CVD和图案化操作形成保护层55。
如图11所示，在由保护层55覆盖n-型FET区域之后，去除鳍结构Fp的S/D区域中的第一半导体层20P。
可以使用相对于第二半导体层25P能选择性地蚀刻第一半导体层20P 的蚀刻剂来去除或蚀刻第一半导体层20P。
当第一半导体层20P是Ge或SiGe并且第二半导体层25P是Si时，可以使用湿蚀刻剂(诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)、氢氧化钾(KOH)溶液、盐酸(HCl)溶液或热氨溶液)来选择性地去除第一半导体层20P。也可以使用等离子体干蚀刻或化学汽相蚀刻。
当第一半导体层20P是Si并且第二半导体层25P是Ge或SiGe时，可以使用湿蚀刻剂(诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)、氢氧化钾(KOH)溶液、盐酸(HCl)溶液或热氨溶液)来选择性地去除第一半导体层20P。也可以使用等离子体干蚀刻或化学汽相蚀刻。
图12A至图15B示出了本发明的一个实施例中的蚀刻第一半导体层20P的工艺。图12A、图13A、图14A和图15A示出了沿着X方向的S/D区域的截面图，并且图12B、图13B、图14B和图15B示出了沿着Y方向的鳍结构的截面图。
图12A、图13A、图14A和图15A也示出了隔离绝缘层50以及第一衬垫层42和第二衬垫层44。图12B、图13B、图14B和图15B也示出了牺牲栅极介电层75、牺牲栅电极层70和侧壁间隔件76。
图12A和图12B示出了暴露鳍结构Fp的S/D区域之后的结构。图13A和图13B示出了去除鳍结构Fp的S/D区域处的第一半导体层20P之后的结构。在图13A和图13B的阶段中，第一半导体层20P的端部位于包括侧壁间隔件76的侧面的平面处。
在一些实施例中，如图14A和图14B所示，进一步水平蚀刻位于牺牲栅极结构下方的第一半导体层20P。在图14A和图14B的阶段中，第一半导体鳍20P的端部位于侧壁间隔件76之下。蚀刻的量W2多于约0nm并且少于侧壁间隔件76的厚度。在一些实施例中，W2在约1nm至约5nm的范围内，并且在其它实施例中，在约2nm至约4nm的范围内。
此外，如图15A和图15B所示，在一些实施例中，当去除第一半导体层20P时，也蚀刻了第二半导体层25P。在一些实施例中，剩余的第二半 导体层25P的量W2’在约1nm至约10nm的范围内。
图16A至图16D示出了形成p-型FET的S/D外延层80P之后的结构。图16B示出了沿着鳍结构Fp的截面图。图16C示出了S/D区域的沿着X方向的截面图并且图16D示出了鳍结构的沿着Y方向的截面图。S/D外延层80P包括SiGe和Ge的一个或多个。如图16C所示，S/D外延层80P包裹在第二半导体层25P周围。
在形成S/D外延层80P之后，形成S/D外延层80N的同时保护层56覆盖p-型区域。如图17所示，去除n-型区域中的保护层55而p-型区域由保护层56覆盖。
下一步，如图18所示，与图11的操作类似，去除S/D区域的第一半导体层20N。
图19A至图22B示出了本发明的一个实施例中蚀刻第一半导体层20N的工艺。图19A、图20A、图21A和图22A示出了S/D区域的沿着X方向的截面图，并且19B、图20B、图21B和图22B示出了鳍结构的沿着Y方向的截面图。
图19A、图20A、图21A和图22A也示出了隔离绝缘层50以及第一衬垫层42和第二衬垫层44。图19B、图20B、图21B和图22B也示出了牺牲栅极介电层75、牺牲栅电极层70和侧壁间隔件76。
图19A和图19B示出了暴露鳍结构Fn的S/D区域之后的结构。图20A和图20B示出了去除鳍结构Fn的S/D区域处的第一半导体层20N之后的结构。在图20A和图20B的阶段中，第一半导体层20N的端部位于包括侧壁间隔件76的侧面的平面处。
在一些实施例中，如图21A和图21B所示，进一步水平蚀刻位于牺牲栅极结构下方的第一半导体层20N。在图21A和图21B的阶段中，第一半导体鳍20N的端部位于侧壁间隔件之下。蚀刻的量W3多于约0nm并且少于侧壁间隔件76的厚度。在一些实施例中，W3在约1nm至约5nm的范围内，并且在其它实施例中，在约2nm至约4nm的范围内。
此外，如图22A和图22B所示，在一些实施例中，当去除第一半导体层20N时，也蚀刻了第二半导体层25N。在一些实施例中，剩余的第二半 导体层25N的量W3’在约1nm至约10nm的范围内。
图23A至图23C示出了形成n-型FET的S/D外延层80N之后的结构。图23B示出了S/D区域的沿着X方向的截面图，并且图23C示出了鳍结构的沿着Y方向的截面图。S/D外延层80N包括SiC、SiP和SiCP的一个或多个。如图23B所示，S/D外延层80N包裹在第二半导体层25N周围。
通过使用CVD、ALD或分子束外延(MBE)的外延生长方法来形成S/D外延层80P和80N。形成S/D外延层80P和80N的顺序可以互换。
在形成S/D外延层80N之后，去除保护层56。图24示出了在形成S/D外延层80P和80N以及去除保护层之后沿着鳍结构Fn的截面图。
如图25所示，在形成S/D外延层之后，在整个结构上方形成层间介电层(ILD)90并且之后通过CMP操作平坦化层间介电层90的上部，从而暴露牺牲栅电极层70的上表面。
用于ILD层90的材料包括包含Si、O、C和/或H的化合物(诸如SiCOH和SiOC)。诸如聚合物的有机材料可以用于ILD层90。此外，在一些实施例中，在形成ILD层90之前，在图24的结构上方形成氧化硅层92，并且之后在氧化硅层92上方进一步形成SiN层94。也可以在ILD层90上方形成SiN层96以保护ILD层90在牺牲栅极介电层的蚀刻期间免受蚀刻的影响。
随后，如图26A和图26B所示，去除牺牲栅电极70和牺牲栅极介电层75，从而暴露随后变成GAA FET的沟道层的鳍结构Fp和Fn。图26B是对应于图26A的线X2-X2的切割图。
在牺牲栅极结构的去除期间，ILD层90保护了S/D结构80P和80N。可以使用等离子体干蚀刻和/或湿蚀刻去除牺牲栅极结构。当牺牲栅电极70是多晶硅并且ILD层90是氧化硅时，诸如TMAH溶液的湿蚀刻剂可以用于选择性地去除牺牲栅电极70。之后，使用等离子体干蚀刻和/或湿蚀刻去除牺牲栅极介电层75。
在去除牺牲栅极结构之后，形成沟道层的布线结构。在本发明的一些实施例中，分别形成n-沟道层(n-型FET)的布线结构和p-沟道层(p-型FET)的布线结构。
如图27所示，p-型区域由保护层57覆盖。此外，去除第一半导体层20N，从而形成第二半导体层25N的布线结构。
图28A至图29C示出了本发明的一个实施例中蚀刻沟道区域中的第一半导体层20N的工艺。图28A至图28C示出了去除第一半导体层20N之前的结构，并且图29A至图29C示出了去除第一半导体层20N之后的结构。图28A和图29A示出了沿着Y方向的截面图，图28B和图29B示出了沟道区域的沿着X方向的截面图，并且图28C和图29C示出了S/D区域的沿着X方向的截面图。
如图28A至图28C所示，在n-型FET的位于第一ILD层90和侧壁间隔件76下方的S/D区域处形成S/D外延层80N。如图29A至图29C所示，通过使用湿蚀刻操作从沟道区域去除第一半导体层20N。可以采用与用于S/D区域的蚀刻操作类似的蚀刻操作用于沟道区域的蚀刻操作。
在本发明的一个实施例中，S/D外延层80N由SiP、SiC或SiCP形成，而第一半导体层20N由SiGe形成。相应地，第一半导体层20N的蚀刻停止在S/D外延层80N处。该结构可以防止栅电极接触S/D外延层。
在其它实施例中，通过从沟道区域选择性地去除第二半导体层25N而由第一半导体层20N形成布线结构。
在形成n-型FET的布线结构(沟道层)之后，去除保护层57，并且在形成p-型FET的沟道层时，保护层覆盖n-型区域。
对于p-型FET，如图30A和图30B所示，部分地蚀刻第二半导体层25P。图30A示出了蚀刻第二半导体层25P之前的结构，并且图30B示出了部分地蚀刻第二半导体层25P之后的结构。如图30B所示，邻近的第一半导体层20P没有完全地分隔开而是通过蚀刻的第二半导体层25P连接。因此，p-型FET的沟道层包括第一半导体层和第二半导体层。在这种情况下，保持了通过剩余的第二半导体层25P施加至第一半导体层20P的应力，同时可以获得S/D层80P的相对更大的表面面积。
在一些实施例中，如图30C所示，蚀刻的第二半导体层25P基本具有矩形截面形状。在一些实施例中，蚀刻的第二半导体层25P的厚度W4在约1nm至约15nm的范围内。
如图31所示，在形成n-型FET和p-型FET的沟道层之后，在每个沟道层周围均形成栅极介电层100，并且在栅极介电层100上形成栅电极层110。应该注意，在图30C中示出的结构可以应用于图31中示出的结构中。
在特定实施例中，栅极介电层100包括介电材料104(诸如氧化硅、氮化硅或高k介电材料)其它合适的介电材料和/或它们的组合的一层或多层。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层100包括在沟道层和介电材料104之间形成的界面层102。
可以由CVD、ALD或任何合适的方法形成栅极介电层100。在一个实施例中，使用诸如ALD的高度共形沉积工艺来形成栅极介电层100以确保在每个沟道层周围形成的栅极介电层均具有均匀的厚度。在一个实施例中，栅极介电层100的厚度在约1nm至约6nm的范围内。
在栅极介电层100上形成栅电极层110以围绕每个沟道层。栅电极层110包括导电材料(诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、钽、镍、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合)的一层或多层。
可以由CVD、ALD、电镀或其它合适的方法形成栅电极层110。栅电极层也沉积在ILD层90的上表面上方。之后，例如，通过使用CMP来平坦化形成在ILD层90上方的栅极介电层和栅电极层，直至暴露ILD层90或SiN层96的顶面。
在本发明的特定实施例中，一个或多个功函调整层(未示出)介于栅极介电层100和栅电极110之间。功函调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两种或多种的多层的导电材料制成。对于n-沟道FET，TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi的一种或多种用作功函调整层，并且对于p-沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种用作功函调整层。可以通过ALD、PVD、CVD、电子束蒸发或其它合适的工艺来形成功函调整层。此外，可以使用不同的金属层分别形成n-沟道FET和p-沟道FET的功函调整层。
图32A和图35B示出了用于形成本发明的其它实施例中的S/D区域的工艺。与图12A至图15B类似，图32A、图33A、图34A和图35A示出了S/D区域的沿着X方向的截面图，并且图32B、图33B、图34B和图35B示出了鳍结构的沿着Y方向的截面图。图32A至图35B示出了n-型FET的S/D区域并且可以对p-型FET施加基本类似的操作。不同于图12A至图15B，从S/D区域去除第二半导体层。
图32A和图32B示出了暴露鳍结构Fn的S/D区域之后的结构。图33A和图33B示出了去除鳍结构Fn的S/D区域处的第二半导体层25N之后的结构。此外，在一些实施例中，如图34A和图34B所示，蚀刻剩余的第一半导体层20N，从而减小第一半导体层的直径。
与图14A和图14B类似，如图33B和34B所示，水平蚀刻位于牺牲栅极结构下方的第二半导体层25N。第二半导体鳍25N的端部位于侧壁间隔件之下。蚀刻的量W3多于约0nm并且少于侧壁间隔件76的厚度。在一些实施例中，W3在约1nm至约5nm的范围内，并且在其它实施例中，在约2nm至约4nm的范围内。
随后，如图35A和图35B所示，在第一半导体层20N周围形成n-型FET的S/D外延层80N。S/D外延层80N包括SiC、SiP和SiCP的一个或多个。如图35A所示，S/D外延层80N包裹在第一半导体层20N周围。
图36和图37示出了用于形成本发明的一个实施例中的沟道层的工艺。
图36是去除牺牲栅极结构之后的n-型FET的结构，该结构是图35B之后的结构，并且基本对应于图28A。在这个实施例中，如图37所示，从沟道区域去除第一半导体层20N。不同于图29A，由于在S/D区域中的各第一半导体层之间形成S/D外延层80N，因此S/D外延层80N不能用作蚀刻沟道区域中的第一半导体层20N的蚀刻停止层。相应地，例如，通过蚀刻时间控制第一半导体层20N的蚀刻。
图38是去除牺牲栅极结构之后的p-型FET的结构，该结构是图35B之后的结构，并且基本对应于图28A。与图30B和图30C类似，如图39A和图39B所示，部分地蚀刻第二半导体层25P。
图40示出了根据本发明的各个实施例的针对沟道层的S/D蚀刻和栅极蚀刻的可能的组合以及相应的图。
应该明白，GAA FET进一步经受CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件。
此处描述的各个实施例或实例提供了超越现有技术的若干优势。例如，在本发明中，S/D外延层可以在沟道蚀刻操作中用作蚀刻停止层，从而防止金属栅电极接触S/D区域。因此，GAA FET包括堆叠的纳米线(Si和/或SiGe)，在堆叠的纳米线的制造工艺中，在同一工艺步骤中实施栅极和源极/漏极处的选择性蚀刻。在GAA FET中，源极/漏极层完全地或部分地外延生长在蚀刻的Si或SiGe堆叠层上，这增大了用于置放接触件定位的表面面积。此外，由于上述配置，可以生长具有掺杂剂的更多失误S/D外延层，这减小了S/D外延层与S/D外延层上的接触插塞之间的接触电阻。
应该明白，不是所有的优势都有必要已经在此处讨论，没有特定的优势对所有实施例或实例都是需要的，并且其它实施例或实例可以提供不同的优势。
根据本发明的一个方面，在制造半导体器件的方法中，在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层的堆叠结构。将堆叠结构图案化成鳍结构。在鳍结构上方形成牺牲栅极结构，从而使得牺牲栅极结构覆盖鳍结构的部分而鳍结构的剩余部分保持暴露。该剩余部分为源极/漏极区域并且由牺牲栅极结构覆盖的鳍结构的部分为沟道区域。去除鳍结构的源极/漏极区域中的第二半导体层，从而使得源极/漏极区域中的第一半导体层暴露并且彼此间隔开。使沟道区域中的第二半导体层在垂直于第一方向的第二方向上向内朝着牺牲栅极结构凹进。在源极/漏极区域中的暴露的第一半导体层上形成外延源极/漏极结构，从而使得外延源极/漏极结构包裹在源极/漏极区域中的暴露的第一半导体层的每个周围。去除牺牲栅极结构以暴露鳍结构的沟道区域。在去除牺牲栅极结构之后，去除鳍结构的暴露的沟道区域中的第二半导体层，从而暴露沟道区域中的第一半导体层。在沟道区域中的暴露的第一半导体层周围形成栅极介电层和栅电极层。
在一些实施例中，该方法还包括：在使所述第二半导体层水平凹进之后，部分地蚀刻所述源极/漏极区域中的暴露的所述第一半导体层。
在一些实施例中，所述第一半导体层由Si或Si基化合物制成。
在一些实施例中，所述第二半导体层由SiGe制成。
在一些实施例中，所述外延源极/漏极结构包括SiP、SiCP和SiC中的至少一个。
在一些实施例中，所述外延源极/漏极结构包括SiGe或Ge。
在一些实施例中，该方法还包括：在所述牺牲栅极结构的两个侧壁上形成侧壁间隔件，其中，在使所述第二半导体层水平凹进之后，所述第二半导体层的至少一个端面位于所述侧壁间隔件的一个的下方。
在一些实施例中，在去除所述源极/漏极区域中的所述第二半导体层中，通过湿蚀刻去除所述第二半导体层。
在一些实施例中，在去除暴露的所述沟道区域中的所述第二半导体层中，通过湿蚀刻去除所述第二半导体层。
根据本发明的另一方面，在制造半导体器件的方法中，在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层的堆叠结构。将堆叠结构图案化成第一鳍结构和第二鳍结构。在第一鳍结构和第二鳍结构上方形成牺牲栅极结构，从而使得牺牲栅极结构覆盖第一鳍结构的部分和第二鳍结构的部分，而第一鳍结构和第二鳍结构的剩余部分保持暴露。该剩余部分分别为第一鳍结构和第二鳍结构的源极/漏极区域。由牺牲栅极结构覆盖的第一鳍结构的部分为第一鳍结构的沟道区域并且由牺牲栅极结构覆盖的第二鳍结构的部分为第二鳍结构的沟道区域。用第一保护层覆盖第二鳍结构。去除第一鳍结构的源极/漏极区域中的第二半导体层，从而使得第一鳍结构的源极/漏极区域中的第一半导体层暴露并且彼此间隔开。使第一鳍结构的沟道区域中的第二半导体层在垂直于第一方向的第二方向上向内朝着牺牲栅极结构凹进。在第一鳍结构的源极/漏极区域中的暴露的第一半导体层上形成第一外延源极/漏极结构，从而使得第一外延源极/漏极结构包裹在第一鳍结构的源极/漏极区域中的暴露的第一半导体层的每个周围。去除第一鳍结构上方的牺牲栅极结构以暴露第一鳍结构的沟道区域。 在去除牺牲栅极结构之后，去除第一鳍结构的暴露的沟道区域中的第二半导体层，从而暴露第一鳍结构的沟道区域中的第一半导体层。在第一鳍结构的沟道区域中的暴露的第一半导体层周围形成栅极介电层和栅电极层。
在一些实施例中，该方法还包括：去除所述第一保护层；用第二保护层覆盖所述第一鳍结构，从所述第二鳍结构去除所述第二鳍结构的所述沟道区域中的所述第二半导体层；去除所述第二鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述第二鳍结构的所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；使所述第二鳍结构的所述沟道区域中的所述第二半导体层在所述第二方向上向内朝着所述牺牲栅极结构凹进；在所述第二鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层上形成第二外延源极/漏极结构，从而使得所述第二外延源极/漏极结构包裹在所述第二鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；去除所述第二鳍结构上方的所述牺牲栅极结构以暴露所述第二鳍结构的所述沟道区域；在去除所述牺牲栅极结构之后，去除所述第二鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第二鳍结构的所述沟道区域中的所述第一半导体层；以及在所述第二鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
在一些实施例中，该方法还包括：去除所述第一保护层；用第二保护层覆盖所述第一鳍结构，从所述第二鳍结构去除所述第二鳍结构的所述沟道区域中的所述第二半导体层；在所述第二鳍结构的所述源极/漏极区域中的所述第一半导体层和所述第二半导体层上方形成第二外延源极/漏极结构；去除所述第二鳍结构上方的所述牺牲栅极结构以暴露所述第二鳍结构的所述沟道区域；在去除所述牺牲栅极结构之后，去除所述第二鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第二鳍结构的所述沟道区域中的所述第一半导体层；以及在所述第二鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
在一些实施例中，所述第一半导体层由Si或Si基化合物制成。
在一些实施例中，所述第二半导体层由SiGe制成。
在一些实施例中，所述第一外延源极/漏极结构包括SiGe或Ge，以及所述第二外延源极/漏极结构包括SiP、SiCP和SiC的至少一个。
在一些实施例中，所述第一半导体层由Si或Si基化合物制成。
在一些实施例中，所述第二半导体层由SiGe制成。
在一些实施例中，所述第一外延源极/漏极结构包括SiGe，以及所述第二外延源极/漏极结构包括SiP、SiCP和SiC的至少一个。
根据本发明的另一方面，半导体器件包括设置在衬底上方的第一沟道层、设置在衬底上方的第一源极/漏极区域、设置在每个第一沟道层上并且包裹每个第一沟道层的栅极介电层以及设置在栅极介电层上并且包裹每个第一沟道层的栅电极层。第一沟道层的每个均包括由第一半导体材料制成的半导体线。半导体线延伸至第一源极/漏极区域。第一源极/漏极中的半导体线由第二半导体材料包裹围绕。
在一些实施例中，所述第一半导体材料是Si并且所述第二半导体材料是SiP、SiCP和SiC中的至少一个。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，包括：
在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层的堆叠结构；
将所述堆叠结构图案化成鳍结构；
在所述鳍结构上方形成牺牲栅极结构，从而使得所述牺牲栅极结构覆盖所述鳍结构的部分而所述鳍结构的剩余部分保持暴露，所述剩余部分为源极/漏极区域并且所述鳍结构中由所述牺牲栅极结构覆盖的所述部分为沟道区域；
去除所述鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；
使所述沟道区域中的所述第二半导体层在垂直于所述第一方向的第二方向上向内朝着所述牺牲栅极结构凹进；
在所述源极/漏极区域中的暴露的所述第一半导体层上形成外延源极/漏极结构，从而使得所述外延源极/漏极结构包裹在所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；
去除所述牺牲栅极结构以暴露所述鳍结构的所述沟道区域；
在去除所述牺牲栅极结构之后，去除所述鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述沟道区域中的所述第一半导体层；以及
在所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
2.根据权利要求1所述的方法，还包括：在使所述第二半导体层水平凹进之后，部分地蚀刻所述源极/漏极区域中的暴露的所述第一半导体层。
3.根据权利要求1所述的方法，其中，所述第一半导体层由Si或Si基化合物制成。
4.根据权利要求3所述的方法，其中，所述第二半导体层由SiGe制成。
5.根据权利要求1所述的方法，还包括：在所述牺牲栅极结构的两个侧壁上形成侧壁间隔件，
其中，在使所述第二半导体层水平凹进之后，所述第二半导体层的至少一个端面位于所述侧壁间隔件的一个的下方。
6.一种制造半导体器件的方法，包括：
在衬底上方形成交替地堆叠在第一方向上的第一半导体层和第二半导体层的堆叠结构；
将所述堆叠结构图案化成第一鳍结构和第二鳍结构；
在所述第一鳍结构和所述第二鳍结构上方形成牺牲栅极结构，从而使得所述牺牲栅极结构覆盖所述第一鳍结构的部分和所述第二鳍结构的部分，而所述第一鳍结构和所述第二鳍结构的剩余部分保持暴露，所述剩余部分分别为所述第一鳍结构和所述第二鳍结构的源极/漏极区域，并且所述第一鳍结构的由所述牺牲栅极结构覆盖的所述部分为所述第一鳍结构的沟道区域以及所述第二鳍结构的由所述牺牲栅极结构覆盖的所述部分为所述第二鳍结构的沟道区域；
用第一保护层覆盖所述第二鳍结构；
去除所述第一鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述第一鳍结构的所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；
使所述第一鳍结构的所述沟道区域中的所述第二半导体层在垂直于所述第一方向的第二方向上向内朝着所述牺牲栅极结构凹进；
在所述第一鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层上形成第一外延源极/漏极结构，从而使得所述第一外延源极/漏极结构包裹在所述第一鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；
去除所述第一鳍结构上方的所述牺牲栅极结构以暴露所述第一鳍结构的所述沟道区域；
在去除所述牺牲栅极结构之后，去除所述第一鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第一鳍结构的所述沟道区域中的所述第一半导体层；以及
在所述第一鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
7.根据权利要求6所述的方法，还包括：
去除所述第一保护层；
用第二保护层覆盖所述第一鳍结构，从所述第二鳍结构去除所述第二鳍结构的所述沟道区域中的所述第二半导体层；
去除所述第二鳍结构的所述源极/漏极区域中的所述第二半导体层，从而使得所述第二鳍结构的所述源极/漏极区域中的所述第一半导体层暴露并且彼此间隔开；
使所述第二鳍结构的所述沟道区域中的所述第二半导体层在所述第二方向上向内朝着所述牺牲栅极结构凹进；
在所述第二鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层上形成第二外延源极/漏极结构，从而使得所述第二外延源极/漏极结构包裹在所述第二鳍结构的所述源极/漏极区域中的暴露的所述第一半导体层的每个的周围；
去除所述第二鳍结构上方的所述牺牲栅极结构以暴露所述第二鳍结构的所述沟道区域；
在去除所述牺牲栅极结构之后，去除所述第二鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第二鳍结构的所述沟道区域中的所述第一半导体层；以及
在所述第二鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
8.根据权利要求6所述的方法，还包括：
去除所述第一保护层；
用第二保护层覆盖所述第一鳍结构，从所述第二鳍结构去除所述第二鳍结构的所述沟道区域中的所述第二半导体层；
在所述第二鳍结构的所述源极/漏极区域中的所述第一半导体层和所述第二半导体层上方形成第二外延源极/漏极结构；
去除所述第二鳍结构上方的所述牺牲栅极结构以暴露所述第二鳍结构的所述沟道区域；
在去除所述牺牲栅极结构之后，去除所述第二鳍结构的暴露的所述沟道区域中的所述第二半导体层，从而暴露所述第二鳍结构的所述沟道区域中的所述第一半导体层；以及
在所述第二鳍结构的所述沟道区域中的暴露的所述第一半导体层周围形成栅极介电层和栅电极层。
9.一种半导体器件，包括：
第一沟道层，设置在衬底上方；
第一源极/漏极区域，设置在所述衬底上方；
栅极介电层，设置在所述第一沟道层的每个上并且包裹所述第一沟道层的每个；以及
栅电极层，设置在所述栅极介电层上并且包裹所述第一沟道层的每个，其中：
所述第一沟道层的每个均包括由第一半导体材料制成的半导体线；
所述半导体布线延伸至所述第一源极/漏极区域，以及
所述第一源极/漏极中的所述半导体线由第二半导体材料包裹围绕。
10.根据权利要求9所述的方法，其中，所述第一半导体材料是Si并且所述第二半导体材料是SiP、SiCP和SiC中的至少一个。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110676304A (zh) * 2018-07-02 2020-01-10 台湾积体电路制造股份有限公司 制造半导体器件的方法和半导体器件
CN110885685A (zh) * 2018-09-07 2020-03-17 三星电子株式会社 蚀刻组合物和使用其制造半导体器件的方法
CN111199886A (zh) * 2018-10-31 2020-05-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN111243958A (zh) * 2018-11-28 2020-06-05 台湾积体电路制造股份有限公司 形成介电层的方法、半导体结构及其形成方法
CN111566803A (zh) * 2017-12-04 2020-08-21 东京毅力科创株式会社 用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法
CN112447713A (zh) * 2019-09-05 2021-03-05 台湾积体电路制造股份有限公司 制造半导体器件的方法和半导体器件
CN113130655A (zh) * 2019-12-31 2021-07-16 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US11973144B2 (en) 2021-11-29 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor and a semiconductor device

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US9853101B2 (en) * 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
US9583399B1 (en) * 2015-11-30 2017-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
CN107452793B (zh) * 2016-06-01 2020-07-28 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9831324B1 (en) 2016-08-12 2017-11-28 International Business Machines Corporation Self-aligned inner-spacer replacement process using implantation
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10943834B2 (en) * 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10269934B2 (en) 2017-03-23 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing tunnel field effect transistor
US10535780B2 (en) * 2017-05-08 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including an epitaxial layer wrapping around the nanowires
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
KR102620595B1 (ko) * 2018-01-22 2024-01-03 삼성전자주식회사 소자분리막을 갖는 반도체 소자 및 그 제조 방법
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10483375B1 (en) 2018-07-17 2019-11-19 International Business Machines Coporation Fin cut etch process for vertical transistor devices
US11038043B2 (en) * 2018-07-31 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11069793B2 (en) 2018-09-28 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
KR20210000529A (ko) * 2019-06-25 2021-01-05 삼성전자주식회사 집적 회로 반도체 소자
US10985265B2 (en) * 2019-08-22 2021-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150084041A1 (en) * 2013-09-24 2015-03-26 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
CN104576396A (zh) * 2013-10-10 2015-04-29 格罗方德半导体公司 利于制造环绕式栅极纳米线场效电晶体的方法
CN104813477A (zh) * 2012-12-21 2015-07-29 英特尔公司 具有成分坡度变化的半导体沟道的非平面ⅲ-n晶体管

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987794B2 (en) * 2011-12-23 2015-03-24 Intel Coporation Non-planar gate all-around device and method of fabrication thereof
KR101410854B1 (ko) * 2013-04-01 2014-06-23 한국전기연구원 다중수소결합에 의해 고차구조를 지니는 탄소나노소재와 금속나노소재를 하이브리드하여 형성된 고전도성 소재 및 그 제조방법
US9570609B2 (en) * 2013-11-01 2017-02-14 Samsung Electronics Co., Ltd. Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
US9443978B2 (en) * 2014-07-14 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor device having gate-all-around transistor and method of manufacturing the same
US9391163B2 (en) * 2014-10-03 2016-07-12 International Business Machines Corporation Stacked planar double-gate lamellar field-effect transistor
US9576856B2 (en) * 2014-10-27 2017-02-21 Globalfoundries Inc. Fabrication of nanowire field effect transistor structures
US9583399B1 (en) * 2015-11-30 2017-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104813477A (zh) * 2012-12-21 2015-07-29 英特尔公司 具有成分坡度变化的半导体沟道的非平面ⅲ-n晶体管
US20150084041A1 (en) * 2013-09-24 2015-03-26 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
CN104576396A (zh) * 2013-10-10 2015-04-29 格罗方德半导体公司 利于制造环绕式栅极纳米线场效电晶体的方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111566803A (zh) * 2017-12-04 2020-08-21 东京毅力科创株式会社 用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法
CN111566803B (zh) * 2017-12-04 2024-02-23 东京毅力科创株式会社 用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法
CN110676304B (zh) * 2018-07-02 2022-11-01 台湾积体电路制造股份有限公司 制造半导体器件的方法和半导体器件
CN110676304A (zh) * 2018-07-02 2020-01-10 台湾积体电路制造股份有限公司 制造半导体器件的方法和半导体器件
CN110885685A (zh) * 2018-09-07 2020-03-17 三星电子株式会社 蚀刻组合物和使用其制造半导体器件的方法
CN110885685B (zh) * 2018-09-07 2023-07-18 三星电子株式会社 蚀刻组合物和使用其制造半导体器件的方法
CN111199886A (zh) * 2018-10-31 2020-05-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN111199886B (zh) * 2018-10-31 2022-11-01 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN111243958A (zh) * 2018-11-28 2020-06-05 台湾积体电路制造股份有限公司 形成介电层的方法、半导体结构及其形成方法
CN111243958B (zh) * 2018-11-28 2023-08-22 台湾积体电路制造股份有限公司 形成介电层的方法、半导体结构及其形成方法
US11842927B2 (en) 2018-11-28 2023-12-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure
CN112447713A (zh) * 2019-09-05 2021-03-05 台湾积体电路制造股份有限公司 制造半导体器件的方法和半导体器件
CN113130655A (zh) * 2019-12-31 2021-07-16 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN113130655B (zh) * 2019-12-31 2024-02-06 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US11973144B2 (en) 2021-11-29 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor and a semiconductor device

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