CN109727867A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN109727867A
CN109727867A CN201810162001.4A CN201810162001A CN109727867A CN 109727867 A CN109727867 A CN 109727867A CN 201810162001 A CN201810162001 A CN 201810162001A CN 109727867 A CN109727867 A CN 109727867A
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layer
source
fin structure
drain
semiconductor
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CN109727867B (zh
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马克·范·达尔
戈本·多恩伯斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了半导体器件及其形成方法。在制造半导体器件的方法中，形成鳍结构，该鳍结构具有底部、设置在底部上方的中间部分以及设置在中间部分上方的上部。去除鳍结构的源极/漏极区域处的中间部分，从而在底部和上部之间形成间隔。在间隔中形成绝缘层。在上部上方形成源极/漏极接触层。源极/漏极接触层通过绝缘层与鳍结构的底部分隔开。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体集成电路，并且更具体地涉及具有全环栅场效应晶体管的半导体器件及其制造工艺。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米级技术工艺节点，来自制造和设计问题的挑战已经引起了诸如多栅极场效应晶体管(包括fin FET(FinFET)和全环栅(GAA)FET)的三维设计的发展。在GAA FET中，沟道区域由栅极介电层和栅电极层包裹的半导体线形成。因为栅极结构从所有侧面围绕(包裹)沟道区域，因此晶体管实质具有控制通过沟道区域的电流的四个栅极。
发明内容
根据本发明的一个方面，提供了一种制造半导体器件的方法，所述方法包括：形成鳍结构，所述鳍结构具有底部、设置在所述底部上方的中间部分以及设置在所述中间部分上方的上部；去除所述鳍结构的源极/漏极区域处的所述中间部分，从而在所述底部和所述上部之间形成间隔；在所述间隔中形成绝缘层；以及在所述上部上方形成源极/漏极接触层，其中，所述源极/漏极接触层通过所述绝缘层与所述鳍结构的底部分隔开。
根据本发明的另一个方面，提供了一种制造半导体器件的方法，所述方法包括：形成鳍结构，所述鳍结构具有底部、设置在所述底部上方的中间部分以及设置在所述中间部分上方的上部；在所述鳍结构上方形成介电层；在所述鳍结构的沟道区域上方形成金属栅极结构；图案化所述介电层，从而形成其中暴露所述鳍结构的所述上部和所述鳍结构的所述中间部分的至少部分的开口；去除所述开口中的所述鳍结构的源极/漏极区域处的所述中间部分，从而在所述底部和所述上部之间形成间隔；在所述间隔中形成绝缘层；以及在所述上部上方形成源极/漏极接触层，其中，所述源极/漏极接触层通过所述绝缘层与所述鳍结构的所述底部分隔开。
根据本发明的又一个方面，提供了一种半导体器件，包括：半导体线结构，具有沟道区域和源极/漏极区域，其中：源极/漏极接触层形成在所述源极/漏极区域上方，源极/漏极接触层嵌入在介电层内，隔离绝缘层设置在所述介电层和衬底之间，以及所述源极/漏极区域的底部通过绝缘层与所述衬底分隔开，所述绝缘层由与所述隔离绝缘层和所述介电层不同的材料制成。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以任意地增大或缩小。
图1A和图1B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图2A和图2B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图3A和图3B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图4A和图4B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图5A和图5B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图6A和图6B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图7A和图7B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图8A和图8B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图9A、图9B和图9C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图10A和图10B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图11A和图11B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图12A和图12B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图13A和图13B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图14A和图14B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图15A和图15B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图16A、图16B和图16C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图17A、图17B和图17C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图18A和图18B示出了根据本发明的另一实施例的具有GAA FET的半导体器件。
图19A和图19B示出了根据本发明的另一实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图20A和图20B示出了根据本发明的另一实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图21A、图21B和图21C示出了根据本发明的另一实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。
图22A和图22B示出了根据本发明的另一实施例的具有GAA FET的半导体器件。
图23A和图23B示出了根据本发明的另一实施例的具有GAA FET的半导体器件。
图24A和图24B示出了根据本发明的另一实施例的具有GAA FET的半导体器件。
图25A和图25B是显示本实施例的效果的模拟和实验性结果。
图26A和图26B是显示本实施例的效果的模拟和实验性结果。
图27A和图27B是显示本实施例的效果的模拟和实验性结果。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简明和清楚，各个部件可以以不同比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。此外，术语“由...制成”可以意味着“包括”或者“由...组成”。
全环栅FET(GAA-FET)通常包括具有沟道区域和设置在沟道区域的两端上的源极/漏极区域的一个或多个半导体线。为了制造半导体线，形成其中一个(或多个)为牺牲层的不同半导体材料的的堆叠层，并且之后去除牺牲层，从而留下半导体线。在源极/漏极区域中，牺牲层可以保留在堆叠层的底部处，这可能产生寄生晶体管。GAA FET中的寄生晶体管对关态漏电流有不利的影响。具体地，当诸如Ge的窄带间隙材料用作沟道材料时，关态漏电流变得更成问题。
本发明提供了可以减小关态漏电流的诸如GAA FET的半导体器件。
图1A至图17B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序。应该理解，可以在图1A至图17B所示的工艺之前、期间和之后提供额外的操作，并且对于方法的额外的实施例，可以替换或消除以下所描述的一些操作。操作/工艺的顺序可以互换。在图1A至图17B中，“B”图(图1B、图2B…)示出了平面图(从上面看)并且“A”图(图1A、图2A…)示出了沿着Y方向(线Y1-Y1或Y2-Y2)的截面图。
图1A和图1B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图1A是对应于图1B的线Y1-Y1的截面图。
如图1A和图1B所示，在衬底10上方外延形成第一半导体层20，并且在第一半导体层20上方外延形成第二半导体层25。
在一个实施例中，衬底10包括至少位于其表面部分上的单晶半导体层。衬底10可以包括单晶半导体材料，诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在一个实施例中，衬底10由Si制成。
衬底10在其表面区域中可以包括一个或多个缓冲层(未示出)。缓冲层可以用于将衬底的晶格常数逐渐转变为源极/漏极区域的晶格常数。缓冲层可以由外延生长的单晶半导体材料形成，单晶半导体材料诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在具体实施例中，衬底10包括在硅衬底10上外延生长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从缓冲层最底部的30原子百分比的锗增加至缓冲层最顶部的70原子百分比的锗。衬底10可以包括已适当掺杂有杂质(例如，p型或n型电导率)的各个区域。
作为牺牲层的第一半导体层20包括与衬底10不同的半导体材料。在一些实施例中，第一半导体层20由外延生长的单晶半导体材料制成，单晶半导体材料诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在一个实施例中，第一半导体层由SixGe1-x制成，其中，0.1<x<0.9(以下可简称为SiGe)。在一些实施例中，第一半导体层20的厚度在从约5nm至约30nm的范围内，并且在其它实施例中，在从约10nm至约20nm的范围内。
第二半导体层25包括与第一半导体层20不同的半导体材料。在一些实施例中，第二半导体层25由外延生长的单晶半导体材料制成，单晶半导体材料诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在一个实施例中，第二半导体层由SiyGe1-y制成，其中，x＜y。在某些实施例中，第二半导体层由Si制成。在一些实施例中，第二半导体层25的厚度在从约10nm至约80nm的范围内，并且在其它实施例中，在从约15nm至约30nm的范围内。
图2A和图2B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图2A是对应于图2B的线Y1-Y1的截面图。
如图2A和图2B所示，通过一次或多次光刻和蚀刻操作形成鳍结构21。可以通过任何合适的方法图案化鳍结构21。例如，可以使用包括双重图案化或多重图案化工艺的一次或多次光刻工艺图案化鳍结构。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，允许待形成的图案具有例如比使用单个直接光刻工艺另外获得的节距更小的节距。例如，在一个实施例中，在衬底上方形成伪层并且使用光刻工艺图案化伪层。使用自对准工艺在图案化的伪层旁边形成间隔件。之后，去除伪层，此后，剩余的间隔件可以用于图案化鳍。
在其它实施例中，可以通过使用硬掩模图案22作为蚀刻掩模来图案化鳍结构。在一些实施例中，硬掩模图案22包括第一掩模层和设置在第一掩模层上的第二掩模层。第一掩模层是由可以通过热氧化形成的氧化硅制成的垫氧层。第二掩模层由通过包括化学汽相沉积(CVD)(包括低压CVD(LPCVD)和等离子体增强CVD(PECVD))、物理汽相沉积(PVD)、原子层沉积(ALD)或其它合适的工艺形成的氮化硅(SiN)制成。通过使用包括光刻和蚀刻的图案化操作将沉积的掩模层图案化成硬掩模图案22。之后，通过使用硬掩模图案将第二半导体层25、第一半导体层20和衬底10图案化成在X方向上延伸的鳍结构21。在图2A和图2B中，两个鳍结构21在Y方向上布置。但是，鳍结构的数量不限制于两个，并且可以包括三个或四个。在一些实施例中，可以在鳍结构的两侧上形成一个或多个伪鳍结构，以提高图案化操作中的图案保真度。如图2A所示，鳍结构的每个均具有底部11(衬底10的部分)、设置在底部上方的中间部分20(第一半导体层)和设置在中间部分上方的上部25(第二半导体层)。
在一些实施例中，鳍结构的上部沿着Y方向的宽度在约5nm至约40nm的范围内，并且在其它的实施例中，在约10nm至约20nm的范围内。在一些实施例中，鳍结构的沿着Z方向的高度在从约100nm至约200nm的范围内。
图3A和图3B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图3A是对应于图3B的线Y1-Y1的截面图。
在形成鳍结构21之后，在衬底10上方形成包括绝缘材料的一层或多层的第一绝缘材料层29，使得鳍结构21完全嵌入在第一绝缘材料层29内。用于第一绝缘材料层29的绝缘材料可以包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD或任何其它合适的膜形成方法形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiCN、氟掺杂的硅酸盐玻璃(FSG)或低K介电材料。在一些实施例中，第一绝缘材料层29由氧化硅制成。可以在第一绝缘材料层29的形成之后实施退火操作。之后，如图3A所示，实施诸如化学机械抛光(CMP)方法和/或回蚀刻方法的平坦化操作，从而使得硬掩模图案22被去除，并且第二半导体层25的上表面从第一绝缘材料层29处暴露。
在一些实施例中，在形成第一绝缘材料层29之前，在鳍结构上方形成一个或多个鳍衬垫层28。鳍衬垫层28可以由SiN或硅氮化物基材料(例如，SiON或SiCN)制成。
图4A和图4B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图4A是对应于图4B的线Y1-Y1的截面图。
之后，如图4A所示，使第一绝缘材料层29凹进以形成第一隔离绝缘层30，使得鳍结构21的上部暴露。由于这种操作，鳍结构21通过第一隔离绝缘层30(也称为浅沟槽隔离(STI))彼此电隔离。在一些实施例中，在凹进蚀刻之后，暴露的鳍结构的高度H1在约40nm至约100nm的范围内，并且在其它的实施例中，在约60nm至约80nm的范围内。
如图4A所示，第一半导体层20的部分从第一隔离绝缘层30暴露。在其它实施例中，第一半导体层20完全地从隔离绝缘层30暴露。
图5A和图5B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图5A是对应于图5B的线Y2-Y2的截面图。
如图5A和图5B所示，在形成第一隔离绝缘层30之后，形成伪栅极结构40。伪栅极结构40包括伪栅极介电层和伪栅电极层。伪栅极介电层包括绝缘材料的一层或多层，诸如硅氧化物基材料。在一个实施例中，使用CVD形成的氧化硅。在一些实施例中，伪栅极介电层的厚度在约1nm至约5nm的范围内。
首先通过在暴露的鳍结构21和第一隔离绝缘层30的上表面上方毯式沉积伪栅极介电层来形成伪栅极结构40。之后，在伪栅极介电层上毯式沉积伪栅电极层，从而使得鳍结构完全地嵌入在伪栅电极层内。伪栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中，伪栅电极层由多晶硅制成。在一些实施例中，伪栅电极层的厚度在约100nm至约300nm的范围内。在一些实施例中，伪栅电极层经受平坦化操作。使用包括LPCVD和PECVD的CVD、PVD、ALD或其它合适的工艺沉积伪栅极介电层和伪栅电极层。随后，在伪栅极层上方形成掩模层。该掩模层可以是光刻胶图案或硬掩模图案。
下一步，如图5A和图5B所示，对掩模层实施图案化操作并且图案化伪栅电极层以形成伪栅电极结构40。如图5B所示，通过图案化伪栅极结构，在伪栅极结构的相对侧上部分地暴露将要成为源极/漏极区域的鳍结构21的上部。在本发明中，源极和漏极可互换使用并且它们的结构基本相同。在图5B中，分别在两个鳍结构21的上方形成两个伪栅极结构40，以及在两个鳍结构21上方形成一个伪栅极结构40。然而，该布局不限于图5B。
在一些实施例中，伪栅极结构40在X方向上的宽度在约5nm至约30nm的范围内，并且在其它实施例中，在约7nm至约15nm的范围内。在一些实施例中，伪栅极结构的间距在约10nm至约50nm的范围内，并且在其它实施例中，在约15nm至约40nm的范围内。
图6A和图6B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图6A是对应于图6B的线Y2-Y2的截面图。
在形成伪栅极结构40之后，通过使用CVD或其它合适的方法共形地形成用于侧壁间隔件45的绝缘材料的毯式层。毯式层以共形地方式沉积，使得其形成为在垂直表面(诸如侧壁)、水平表面和伪栅极结构的顶面上具有基本相等的厚度。在一些实施例中，毯式层沉积至在从约2nm至约20nm的范围内的厚度。在一个实施例中，毯式层的绝缘材料与第一隔离绝缘层和第二隔离绝缘层的材料不同，并且由诸如SiN、SiON、SiOCN或SiCN和它们的组合的硅氮化物基材料制成。在一些实施例中，毯式层(侧壁间隔件45)由SiN制成。如图6A和图6B所示，通过各向异性蚀刻在伪栅极结构40的相对侧壁上形成侧壁间隔件45。
图7A和图7B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图7A是对应于图7B的线Y2-Y2的截面图。
如图7A和图7B所示，在形成侧壁间隔件45之后，形成层间介电(ILD)层50。用于ILD层50的材料包括包含Si、O、C和/或H的化合物，诸如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于ILD层50。在形成ILD层50之后，实施诸如CMP的平坦化操作，使得伪栅极结构40的伪栅电极层的顶部暴露。
图8A和图8B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图8A是对应于图8B的线Y2-Y2的截面图。
下一步，如图8A和图8B所示，去除伪栅极结构40，从而形成栅极间隔48，其中，分别暴露了鳍结构21的上部(第二半导体层25和至少一部分的第一半导体层20)。没有去除侧壁间隔件45。
可以使用等离子体干蚀刻和/或湿蚀刻去除伪栅极结构。当伪栅电极层是多晶硅并且ILD层50是氧化硅时，诸如TMAH溶液的湿蚀刻剂可以用于选择性地去除伪栅电极层。之后，使用等离子体干蚀刻和/或湿蚀刻去除伪栅极介电层。
图9A至图9C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图9A是对应于图9B的线Y2-Y2的截面图，并且图9C是对应于图9B的线X1-X1的截面图。
如图9A所示，在栅极间隔48中，去除第一半导体层20，从而形成间隔19。当第一半导体层20是Ge或SiGe并且第二半导体层25和衬底10是Si时，可以使用诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第一半导体层20。通过去除栅极间隔48中的第一半导体层20，形成具有沟道区域的半导体线结构。根据第二半导体层25的高宽比，半导体线结构也可以称为半导体鳍结构。
图10A和图10B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图10A是对应于图10B的线Y2-Y2的截面图。
如图10A和图10B所示，在形成沟道层之后，在沟道区域(第二半导体层25)和周围区上方形成栅极介电层23。在某些实施例中，栅极介电层23包括介电材料的一层或多层，介电材料诸如氧化硅、氮化硅或高k介电材料、其它合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层23包括形成在沟道层和介电材料之间的界面层。
可以通过CVD、ALD或任何合适的方法形成栅极介电层23。在一个实施例中，使用诸如ALD的高度共形沉积工艺形成栅极介电层23，以确保在每个沟道层周围形成的栅极介电层具有均匀的厚度。在一个实施例中，栅极介电层23的厚度在约1nm至约6nm的范围内。
图11A至图12B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图11B和图12B相同。图11A是对应于图11B的线Y2-Y2的截面图。图12A是对应于图12B的线Y1-Y1的截面图。
随后，在栅极介电层23上形成栅电极层60。栅电极层60包括导电材料的一层或多层，导电材料诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合。
可以通过CVD、ALD、电镀或其它合适的方法形成栅电极层60。也在ILD层50的上表面上方沉积栅极介电层和栅电极层。之后，如图11A所示，通过使用例如CMP来平坦化形成在ILD层50上方的栅极介电层和栅电极层，直至暴露ILD层50的顶面。
在本发明的某些实施例中，一个或多个功函调整层(未示出)可以介于栅极介电层23与栅电极60之间。功函调整层由导电材料制成，导电材料诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两种或多种的多层。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi的一种或多种用作功函调整层，而对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种用作功函调整层。可以通过ALD、PVD、CVD、电子束蒸发或其他适当的工艺形成功函调整层。此外，可以使用不同的金属层分别形成用于n沟道FET和p沟道FET的功函调整层。
图12A示出了形成栅电极层60之后的源极/漏极区域。如图12A所示，第一半导体层20保留在鳍结构中。
图13A和图13B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图13A是对应于图13B的线Y1-Y1截面图。
如图13A和图13B所示，通过一个或多个光刻和蚀刻操作图案化ILD层50，从而形成第一源极/漏极开口58。在第一源极/漏极开口58中，暴露第二半导体层25和至少一部分的第一半导体层20。
在一些实施例中，在形成第一源极/漏极开口58之前或之后，用适当的掺杂剂掺杂将成为源极/漏极区域的第二半导体层25。在其它实施例中，在形成第一源极/漏极开口58之前或之后，在第二半导体层25上方形成一个或多个外延层。
在图13A和图13B中，形成暴露两个鳍结构的一个源极/漏极开口58。然而，该配置不限于此。在一些实施例中，在一个鳍结构上方形成一个源极/漏极开口58，并且在其它实施例中，在三个或更多鳍结构上方形成一个源极/漏极开口58。
图14A和图14B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图14A是对应于图14B的线Y1-Y1的截面图。
如图14A所示，在第一源极/漏极开口58中，去除第一半导体层20，从而形成间隔27。当第一半导体层20是Ge或SiGe并且第二半导体层25和衬底10是Si时，可以使用诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第一半导体层20。通过去除第一源极/漏极开口58中的第一半导体层20，源极/漏极区域与衬底10(鳍结构中从衬底10突出的底部)分隔开。
图15A和图15B示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图15A是对应于图15B的线Y1-Y1的截面图。
之后，如图15A所示，形成包括绝缘材料的一层或多层的绝缘材料层70来填充第一源极/漏极开口。用于绝缘材料层70的绝缘材料与ILD层50的绝缘材料不同，并且可以包括通过LPCVD(低压化学汽相沉积)、等离子体CVD、原子层沉积(ALD)或可流动CVD或任何其它合适的膜形成方法形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、氟掺杂的硅酸盐玻璃(FSG)或低K介电材料。在一些实施例中，绝缘材料层70包括SiCO或SiOCN。可以在绝缘材料层70的形成之后实施退火操作。
图16A至图16C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图16A是对应于图16B的线Y1-Y1的截面图，并且图16C是对应于图16B的线X1-X1的截面图。
之后，如图16A和图16B所示，使绝缘材料层70凹进，从而形成第二源极/漏极开口72。由于绝缘材料层70由与ILD层50的不同的材料制成，因此可以相对于ILD层50选择性地蚀刻绝缘材料层70。在某些实施例中，可以在没有暴露绝缘材料层70并且覆盖绝缘材料层70周围的ILD层的光刻胶掩模的情况下蚀刻绝缘材料层70。
绝缘材料层70的位于第二半导体层25下方的厚度H2与第一半导体层20的厚度基本相同，并且在一些实施例中，在约5nm至约30nm的范围内，并且在其它实施例中，在约10nm至约20nm的范围内。在一些实施例中，绝缘材料层70的位于第一隔离绝缘层30上的厚度H3在约2nm至约20nm的范围内，并且在其它实施例中，在约5nm至约15nm的范围内。
图17A至图17C示出了根据本发明的实施例的用于制造具有GAA FET的半导体器件的工艺顺序的各个阶段的一个。图17A是对应于图17B的线Y1-Y1的截面图，并且图17C是对应于图17B的线X1-X1的截面图。
在使绝缘材料层70凹进之后，在第二源极/漏极开口72中形成导电材料。如图17A和图17B所示，在第二源极/漏极开口72中和上方形成导电材料并且之后实施诸如CMP操作的平坦化操作以形成源极/漏极接触层80。导电材料包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN或任何其它合适的材料的一层或多层。
在一些实施例中，如图18A和图18B所示，在形成导电材料之前，在第二半导体层25上方形成硅化物层75。硅化物层包括WSi、CoSi、NiSi、TiSi、MoSi和TaSi的一种或多种。当第二半导体层包括Ge时，形成Ge和金属的合金(例如，TiGe、NiGe或CoGe)，并且当外延层包括Si和Ge时，形成Si、Ge和金属的合金(例如，NiSiGe或TiSiGe)。当第二半导体层包括III-V族半导体时，形成诸如Ni-InAlAs的合金。
应该理解，GAA FET经受进一步CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件。
如图17A至图18B所示，源极/漏极区域的底部(第二半导体层25)通过绝缘材料层70与衬底10(鳍结构的从衬底10突出的底部)分隔开，该绝缘材料层70由与隔离绝缘层30和ILD层50不同的材料制成。由于这种结构，源极/漏极区域与衬底电隔离并且没有形成寄生晶体管。
图19A至图23B示出了根据本发明的另一实施例的用于制造具有GAAFET的半导体器件的工艺顺序。应该理解，可以在图19A至图23B所示的工艺之前、期间和之后提供额外的操作，并且对于方法的额外的实施例，可以替换或消除以下描述的一些操作。操作/工艺的顺序可以互换。在以下实施例中，可以采用与参照图1A至图18B描述的上述实施例相同或类似的材料、配置、尺寸和/或工艺，因此可以省略它们详细的说明。
在上述实施例中，由鳍结构形成一个沟道层(半导体线)。在参照图19A至图23B的实施例中，由一个鳍结构形成垂直布置的多个半导体线。
图19A和图19B示出了根据本发明的另一实施例的用于制造具有GAAFET的半导体器件的工艺顺序的各个阶段的一个。图19A是对应于图19B的线Y1-Y1的截面图。
在形成第一源极/漏极开口58之后，图19A和图19B相当于图13A和图13B。如图19A所示，鳍结构121包括交替堆叠的第一半导体层120和122以及第二半导体层125的多个层。在一个实施例中，第一半导体层120和122由SiGe制成，并且第二半导体层125由Si制成。第一和第二半导体层交替外延形成在衬底10上方并且通过实施与如上所述的图1A至图2B类似的图案化操作形成鳍结构121。在一些实施例中，最底第一半导体层120的厚度大于剩余的第一半导体层122的厚度。虽然图19A示出了四个第二半导体层125，但是第二半导体层的数量可以是两个、三个或多于四个。
图20A和图20B示出了根据本发明的另一实施例的用于制造具有GAAFET的半导体器件的工艺顺序的各个阶段的一个。图20A是对应于图20B的线Y1-Y1的截面图。
之后，如图20A所示，与参照图14A至图16B说明的操作类似，去除第一源极/漏极开口58中的第一半导体层120和122，并且形成凹进的绝缘材料层70。在一些实施例中，在最底第二半导体层125和绝缘材料层70之间形成间隔。在其它实施例中，最底第二半导体层125的一部分嵌入在绝缘材料层70内。
图21A至图21C示出了根据本发明的另一实施例的用于制造具有GAAFET的半导体器件的工艺顺序的各个阶段的一个。图21A是对应于图21B的线Y1-Y1的截面图，并且图21C是对应于图21B的线X1-X1的截面图。
如图21A和图21B所示，与参照图17A和图17B说明的操作类似，形成源极/漏极接触层80。
在一些实施例中，如图22A和图22B所示，在形成导电材料之前，在第二半导体层25上方形成硅化物层75。
图23A是对应于图23B的线Y2-Y2的截面图，其相当于图11A和图11B。如图23A所示，多个沟道层125垂直布置并且沟道层125的每个均由栅极介电层92和栅电极层94包裹。
与参照图5A至图11B说明的操作类似，在具有第一和第二半导体层的堆叠层的鳍结构的上部上方形成伪栅极结构。之后，在伪栅极结构的相对侧面上形成侧壁间隔件。下一步，去除伪栅极结构，并且因此形成由侧壁间隔件层围绕的栅极间隔，其中，暴露了鳍结构的上部。从栅极间隔中的上部去除第一半导体层。通过去除第一半导体层，获得由第二半导体层形成的半导体线。形成包裹第二半导体层的栅极介电层。之后，在栅极介电层上方形成金属栅电极层，从而获得图23A和图23B的结构。
图24A和图24B示出了根据本发明的另一实施例的具有FinFET的半导体器件。在以下实施例中，可以采用与参照图1A至图23B描述的上述实施例相同或类似的材料、配置、尺寸和/或工艺，并且可以省略它们详细的说明。
在这种实施例中，如图24A所示，采用由第二半导体层形成的鳍结构25作为FET的沟道区域，而源极/漏极结构具有与图17A或图18A所示的相同的结构。鳍结构25设置在没有被去除的第一半导体层20上方。应该理解，GAA FET经受进一步CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件
图25A至图25B示出了模拟(模型)和实验之间的对应关系。这些图显示了具有三个垂直堆叠的Ge纳米线器件(2个鳍结构)且Lg＝70nm的栅极在Vds＝-0.05V和-0.65V下的Id/Vg性质。图25A示出了线性图并且图25B示出了对数图。实线是实验结果并且点(黑色和白色)是模拟结果。从图25A至图25B可以证实，用于模拟的模型较好的再现实际的器件行为。
当SiGe层(牺牲层)保持在最底纳米线和衬底(底部鳍)之间时，鳍结构和纳米线的隔离是充分的。相反地，在上述实施例中，用介电层70替换硅锗层。图26A和图26B显示了具有三个垂直堆叠的Ge纳米线器件(2个鳍结构)且Lg＝30nm的栅极在Vds＝-0.05V和-0.65V下的模拟的Is/Vg性质。图26A示出了三个单独的NW FET和寄生底部FinFET的线性图并且图26B示出了三个单独的NW FET和寄生底部FinFET的对数图。各个NW FET的亚阈值斜率接近理想的60mV/dec，而寄生器件的斜率较差。因此，应该理解，通过介电层70隔离鳍可以改进器件性能。
图27A和图27B示出了通过模拟获得的截止电流性质。图27A和图27B示出了在Vg＝0V和Vds＝-0.65V(关态条件)下，在Lg＝70nm(图27A)和Lg＝30nm(图27B)处的三个垂直堆叠的Ge纳米线器件的空穴电流密度图。具体地，在Lg＝30nm处，在寄生底部FinFET中观察到高空穴电流密度，这解释了在按比例缩小栅极长度的情况下较差的短沟道效应控制(即，较高的亚阈值斜率)导致不期望的高关态泄漏的原因。再者，这些图显示了从堆叠的纳米线器件去除寄生晶体管的必要性。如上所述，在本发明的FET中，源极/漏极区域与衬底(底部鳍)隔离，因此不存在寄生晶体管。
本文描述的各个实施例或实例提供了超越现有技术的若干优势。例如，在本发明中，由于绝缘材料层介于源极/漏极区域的底部和衬底(衬底的突出部分为鳍结构的底部)之间，因此可以防止寄生晶体管的形成并且减小了关态漏电流。此外，通过使用与ILD层和/或隔离绝缘层不同的绝缘材料作为绝缘材料层，形成绝缘材料层的工艺变得更容易。
应该理解，不是所有的优势都有必要在此处讨论，没有特定的优势对于所有实施例或实例都是需要的，并且其它实施例或实例可以提供不同的优势。
根据本发明的一个方面，在制造半导体器件的方法中，形成鳍结构，该鳍结构具有底部、设置在底部上方的中间部分以及设置在中间部分上方的上部。去除鳍结构的源极/漏极区域处的中间部分，从而在底部和上部之间形成间隔。在间隔中形成绝缘层。在上部上方形成源极/漏极接触层。源极/漏极接触层通过绝缘层与鳍结构的底部分隔开。在以上或以下的一个或多个实施例中，在该方法中，在去除中间部分之前，在鳍结构上方形成介电层，并且图案化介电层，从而形成其中暴露鳍结构的上部和鳍结构的中间部分的至少一部分的开口。去除开口中的中间部分并且在开口中形成绝缘层。在以上或以下的一个或多个实施例中，绝缘层和介电层由彼此不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层由SiCO制成。在以上或以下的一个或多个实施例中，介电层由氧化硅制成。在以上或以下的一个或多个实施例中，中间部分由SixGe1-x制成并且上部由SiyGe1-y制成，其中，x＜y。在以上或以下的一个或多个实施例中，中间部分由SixGe1-x制成，其中，0.1＜x＜0.9，并且上部和底部由Si制成。
根据本发明的另一方面，在制造半导体器件的方法中，形成鳍结构，该鳍结构具有底部、设置在底部上方的中间部分以及设置在中间部分上方的上部。在鳍结构上方形成介电层。在鳍结构的沟道区域上方形成金属栅极结构。图案化介电层，从而形成其中暴露鳍结构的上部和鳍结构的中间部分的至少一部分的开口。去除开口中的鳍结构的源极/漏极区域处的中间部分，从而在底部和上部之间形成间隔。在间隔中形成绝缘层。在上部上方形成源极/漏极接触层。源极/漏极接触层通过绝缘层与鳍结构的底部分隔开。在以上或以下的一个或多个实施例中，金属栅极结构通过以下操作形成：在鳍结构的沟道区域上方形成伪栅极结构，在伪栅极结构的相对侧面上形成侧壁间隔件，去除伪栅极结构，从而形成由侧壁间隔件层围绕的栅极间隔，其中，暴露沟道区域，在暴露的沟道区域上方形成栅极介电层，并且在栅极介电层上方形成金属栅电极层。在以上或以下的一个或多个实施例中，暴露的沟道区域包括鳍结构的上部和中间部分的至少一部分，并且在形成栅极介电层之前去除中间部分。在以上或以下的一个或多个实施例中，绝缘层和介电层由彼此不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层、介电层和侧壁间隔件层由彼此不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层由SiCO制成。在以上或以下的一个或多个实施例中，介电层由氧化硅制成。在以上或以下的一个或多个实施例中，中间部分由SixGe1-x制成并且上部由SiyGe1-y制成，其中，x＜y。在以上或以下的一个或多个实施例中，中间部分由SixGe1-x制成，其中，0.1＜x＜0.9，并且上部和底部由Si制成。
根据本发明的另一方面，在制造半导体器件的方法中，形成鳍结构。该鳍结构具有底部、设置在底部上方的中间部分以及设置在中间部分上方的上部。上部包括一个或多个第一半导体层和一个或多个第二半导体层的堆叠层。去除鳍结构的源极/漏极区域处的中间部分，从而在底部和上部之间形成间隔。在间隔中形成绝缘层。在上部上方形成源极/漏极接触层。源极/漏极接触层通过绝缘层与鳍结构的底部分隔开。在以上或以下的一个或多个实施例中，当去除中间部分时，从上部去除一个或多个第一半导体层，并且源极/漏极接触层包裹一个或多个第二半导体层。在以上或以下的一个或多个实施例中，鳍结构的底部嵌入在隔离绝缘层内，并且绝缘层和隔离绝缘层由彼此不同的材料制成。在以上或以下的一个或多个实施例中，在方法中，在鳍结构的上部上方形成伪栅极结构，在伪栅极结构的相对侧面上形成侧壁间隔件，去除伪栅极结构，从而形成其中暴露上部的由侧壁间隔件层围绕的栅极间隔，从栅极间隔中的鳍结构的上部去除一个或多个第一半导体层，形成包裹一个或多个第二半导体层的栅极介电层，并且在栅极介电层上方形成金属栅电极层。
根据本发明的一个方面，半导体器件包括具有沟道区域和源极/漏极区域的半导体线结构。在源极/漏极区域上方形成源极/漏极接触层。源极/漏极接触层嵌入在介电层内。隔离绝缘层设置在介电层和衬底之间。源极/漏极区域的底部通过绝缘层与衬底分隔开，该绝缘层由与隔离绝缘层和介电层不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层由SiCO制成。在以上或以下的一个或多个实施例中，介电层由氧化硅制成。在以上或以下的一个或多个实施例中，衬底包括位于源极/漏极区域之下的突出件，并且绝缘层设置在源极/漏极区域的底部和突出件之间。在以上或以下的一个或多个实施例中，半导体线结构的源极/漏极区域和突出件由相同的材料制成。在以上或以下的一个或多个实施例中，半导体器件还包括包含栅极介电层和金属栅电极层的栅极结构，并且栅极介电层包裹半导体线结构的沟道区域。在以上或以下的一个或多个实施例中，在源极/漏极区域和源极/漏极接触层之间设置硅化物层。在以上或以下的一个或多个实施例中，源极/漏极接触层的底部通过绝缘层与隔离绝缘层分隔开。
根据本发明的另一方面，半导体器件包括具有沟道区域和源极/漏极区域的第一半导体线结构和具有沟道区域和源极/漏极区域的第二半导体线结构。在第一半导体线结构的源极/漏极区域和第二半导体线结构的源极/漏极区域上方形成源极/漏极接触层。源极/漏极接触层嵌入在介电层内。隔离绝缘层设置在介电层和衬底之间。第一半导体线结构的源极/漏极区域的底部和第二半导体线结构的源极/漏极区域的底部通过绝缘层与衬底分隔开，该绝缘层由与隔离绝缘层和介电层不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层由SiCO制成并且介电层和隔离绝缘层由氧化硅制成。在以上或以下的一个或多个实施例中，衬底包括位于第一半导体线结构的源极/漏极区域之下的第一突出件和位于第二半导体线结构的源极/漏极区域之下的第二突出件。绝缘层设置在第一半导体线结构的源极/漏极区域的底部和第一突出件之间以及第二半导体线结构的源极/漏极区域的底部和第二突出件之间。在以上或以下的一个或多个实施例中，第一和第二半导体线结构和衬底由相同的材料制成。在以上或以下的一个或多个实施例中，第一和第二半导体线结构和衬底由不同的材料制成。在以上或以下的一个或多个实施例中，半导体器件还包括包含栅极介电层和金属栅电极层的第一栅极结构和包含栅极介电层和金属栅电极层的第二栅极结构，并且第一栅极结构的栅极介电层包裹第一半导体线结构的沟道区域，并且第二栅极结构的栅极介电层包括第二半导体线结构的沟道区域。在以上或以下的一个或多个实施例中，第一硅化物层设置在第一半导体线结构的源极/漏极区域和源极/漏极接触层之间，并且第二硅化物层设置在第二半导体线结构的源极/漏极区域和源极/漏极接触层之间。在以上或以下的一个或多个实施例中，源极/漏极接触层的底部通过绝缘层与隔离绝缘层分隔开。
根据本发明的另一方面，半导体器件包括半导体线结构，半导体线结构具有沟道区域和源极/漏极区域。在源极/漏极区域上方形成包裹半导体线的源极/漏极接触层。源极/漏极接触层嵌入在介电层内。隔离绝缘层设置在介电层和衬底之间。源极/漏极区域的底部通过绝缘层与衬底分隔开，该绝缘层由于隔离绝缘层和介电层不同的材料制成。在以上或以下的一个或多个实施例中，绝缘层由SiCO制成。在以上或以下的一个或多个实施例中，衬底包括位于源极/漏极区域之下的突出件，并且绝缘层设置在源极/漏极区域的底部和突出件之间。在以上或以下的一个或多个实施例中，突出件从衬底连续地延伸并且由与衬底相同的材料制成。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
形成鳍结构，所述鳍结构具有底部、设置在所述底部上方的中间部分以及设置在所述中间部分上方的上部；
去除所述鳍结构的源极/漏极区域处的所述中间部分，从而在所述底部和所述上部之间形成间隔；
在所述间隔中形成绝缘层；以及
在所述上部上方形成源极/漏极接触层，
其中，所述源极/漏极接触层通过所述绝缘层与所述鳍结构的底部分隔开。
2.根据权利要求1所述的方法，还包括，在去除所述中间部分之前；
在所述鳍结构上方形成介电层；以及
图案化所述介电层，从而形成其中暴露所述鳍结构的所述上部和所述鳍结构的所述中间部分的至少部分的开口，
其中，去除所述开口中的所述中间部分并且在所述开口中形成所述绝缘层。
3.根据权利要求2所述的方法，其中，所述绝缘层和所述介电层由彼此不同的材料制成。
4.根据权利要求3所述的方法，其中，所述绝缘层由SiCO制成。
5.根据权利要求3所述的方法，其中，所述介电层由氧化硅制成。
6.一种制造半导体器件的方法，所述方法包括：
形成鳍结构，所述鳍结构具有底部、设置在所述底部上方的中间部分以及设置在所述中间部分上方的上部；
在所述鳍结构上方形成介电层；
在所述鳍结构的沟道区域上方形成金属栅极结构；
图案化所述介电层，从而形成其中暴露所述鳍结构的所述上部和所述鳍结构的所述中间部分的至少部分的开口；
去除所述开口中的所述鳍结构的源极/漏极区域处的所述中间部分，从而在所述底部和所述上部之间形成间隔；
在所述间隔中形成绝缘层；以及
在所述上部上方形成源极/漏极接触层，
其中，所述源极/漏极接触层通过所述绝缘层与所述鳍结构的所述底部分隔开。
7.根据权利要求6所述的方法，其中，所述金属栅极结构通过以下方法形成：
在所述鳍结构的所述沟道区域上方形成伪栅极结构；
在所述伪栅极结构的相对两侧上形成侧壁间隔件；
去除所述伪栅极结构，从而形成由侧壁间隔件层围绕的栅极间隔，在所述栅极间隔中，暴露所述沟道区域；
在暴露的所述沟道区域上方形成栅极介电层；以及
在所述栅极介电层上方形成金属栅电极层。
8.根据权利要求7所述的方法，其中：
暴露的所述沟道区域包括所述鳍结构的所述上部和所述中间部分的至少部分，以及
在形成所述栅极介电层之前去除所述中间部分。
9.一种半导体器件，包括：
半导体线结构，具有沟道区域和源极/漏极区域，其中：
源极/漏极接触层形成在所述源极/漏极区域上方，
源极/漏极接触层嵌入在介电层内，
隔离绝缘层设置在所述介电层和衬底之间，以及
所述源极/漏极区域的底部通过绝缘层与所述衬底分隔开，所述绝缘层由与所述隔离绝缘层和所述介电层不同的材料制成。
10.根据权利要求9所述的半导体器件，其中，所述绝缘层由SiCO制成。
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