CN109585555A - 制造半导体器件的方法和半导体器件 - Google Patents

制造半导体器件的方法和半导体器件 Download PDF

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CN109585555A
CN109585555A CN201810911580.8A CN201810911580A CN109585555A CN 109585555 A CN109585555 A CN 109585555A CN 201810911580 A CN201810911580 A CN 201810911580A CN 109585555 A CN109585555 A CN 109585555A
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Prior art keywords
semiconductor layer
semiconductor
layer
drain
source
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CN201810911580.8A
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CN109585555B (zh
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余绍铭
李东颖
云惟胜
杨富祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/940,329 external-priority patent/US10497624B2/en
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Priority to CN202210374852.1A priority Critical patent/CN114664927A/zh
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Abstract

制造半导体器件的方法，包括：在半导体衬底上方形成具有第一组成的第一半导体层，以及在第一半导体层上方形成具有第二组成的第二半导体层。在第二半导体层上方形成具有第一组成的另一第一半导体层。在另一第一半导体层上方形成具有第三组成的第三半导体层。图案化第一半导体层、第二半导体层和第三半导体层以形成鳍结构。去除第三半导体层的部分，从而形成包括第二半导体层的纳米线，并且形成围绕纳米线导电材料。第一半导体层、第二半导体层和第三半导体层包括不同的材料。本发明实施例涉及制造半导体器件的方法和半导体器件。

Description

制造半导体器件的方法和半导体器件
技术领域
本发明实施例涉及制造半导体集成电路的方法，并且更具体地，涉及制造包括鳍式场效应晶体管(FinFET)和全环栅(GAA)FET的半导体器件的方法和半导体器件。
背景技术
在追求更高的器件密度、更高的性能和更低的成本的过程中，随着半导体工业已经进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如多栅极场效应晶体管(FET)(包括鳍式场效应晶体管(FinFET)和全环栅(GAA)FET)的三维设计的发展。在FinFET中，栅电极邻近于沟道区域的三个侧面，其中，栅极介电层插入在它们之间。因为栅极结构围绕(包裹)鳍的三个表面，所以晶体管实质具有三个栅极来控制通过鳍或沟道区域的电流。不幸地，第四侧(沟道的底部)远离栅电极，并且因此不在邻近的栅极控制下。相比之下，在GAA FET中，沟道区域的所有侧面均由栅电极围绕，这允许沟道区域中更充分的耗尽，并且由于更陡峭的亚阈值电流摆幅(SS)和更小的漏致势垒降低(DIBL)而使得短沟道效应减少。随着晶体管尺寸持续按比例缩小至10至15nm以下的技术节点，需要GAA FET的进一步改进。
发明内容
根据本发明的一些实施例，提供了一种制造半导体器件的方法，包括：在半导体衬底上方形成具有第一组成的第一半导体层；在所述第一半导体层上方形成具有第二组成的第二半导体层；在所述第二半导体层上方形成具有所述第一组成的另一第一半导体层；在所述另一第一半导体层上方形成具有第三组成的第三半导体层；图案化所述第一半导体层、所述第二半导体层和所述第三半导体层以形成鳍结构；去除所述第三半导体层的部分，从而形成包括所述第二半导体层的纳米线；以及形成围绕所述纳米线的导电材料，其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：在半导体衬底上方形成鳍结构，其中，第一半导体层A、第二半导体层B和第三半导体层C以重复序列ABAC堆叠，其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料；形成牺牲栅极结构，所述牺牲栅极结构限定所述鳍结构上方的栅极区域；从所述鳍结构的未由所述牺牲栅极结构覆盖的源极/漏极区域去除所述第三半导体层；在所述源极/漏极区域中形成源极/漏极外延层；去除所述牺牲栅极结构；从所述栅极区域去除所述第三半导体层；以及在所述栅极区域中形成栅电极结构，其中，所述栅电极结构包裹环绕所述第一半导体层和所述第二半导体层。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：至少一条半导体纳米线，设置在半导体衬底上方；栅极结构，包裹环绕所述至少一条半导体纳米线；以及源极/漏极结构，设置在所述栅极结构的相对侧上的所述半导体衬底上方，其中，所述至少一条半导体纳米线包括由第一半导体材料组成的两个相对的层，第二半导体材料的层夹在所述两个相对的层之间，所述第二半导体材料与所述第一半导体材料不同。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的实施例的示出制造工艺阶段的一个的GAA FET半导体器件的等轴视图。
图2示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图3示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图4示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图5示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图6A、图6B和图6C示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图7示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图8示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图9示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。
图10A和图10B示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图10A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图10B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。
图11A至图11D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图11A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图11B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图11C是沿着图1的线C-C截取的截面图。图11D是沿着图1的线D-D截取的截面图。
图12A至图12D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图12A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图12B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图12C是沿着图1的线C-C截取的截面图。图12D是沿着图1的线D-D截取的截面图。图12E是另一实施例的沿着图1的线B-B截取的截面图。
图13A至图13D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图13A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图13B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图13C是沿着图1的线C-C截取的截面图。图13D是沿着图1的线D-D截取的截面图。图13E是另一实施例的沿着图1的线C-C截取的截面图并且图13F是另一实施例的沿着图1的线B-B截取的截面图。
图14A至图14D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图14A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图14B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图14C是沿着图1的线C-C截取的截面图。图14D是沿着图1的线D-D截取的截面图。图14E是另一实施例的沿着图1的线C-C截取的截面图并且图14F是另一实施例的沿着图1的线B-B截取的截面图。
图15A至图15D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图15A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图15B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图15C是沿着图1的线C-C截取的截面图。图15D是沿着图1的线D-D截取的截面图。图15E是另一实施例的沿着图1的线C-C截取的截面图并且图15F是另一实施例的沿着图1的线B-B截取的截面图。图15G是图15A中的鳍结构的详细的截面图。
图16A至图16D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图16A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图16B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图16C是沿着图1的线C-C截取的截面图。图16D是沿着图1的线D-D截取的截面图。图16E是另一实施例的沿着图1的线C-C截取的截面图并且图16F是另一实施例的沿着图1的线B-B截取的截面图。
图17A至图17D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图17A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图17B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图17C是沿着图1的线C-C截取的截面图。图17D是沿着图1的线D-D截取的截面图。图17E是另一实施例的沿着图1的线C-C截取的截面图并且图17F是另一实施例的沿着图1的线B-B截取的截面图。
图18A至图18D示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个。图18A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图18B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图18C是沿着图1的线C-C截取的截面图。图18D是沿着图1的线D-D截取的截面图。图18E是另一实施例的沿着图1的线C-C截取的截面图并且图18F是另一实施例的沿着图1的线B-B截取的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限于公开的范围或值，但可能取决于工艺条件和/或器件所需的性能。此外，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。此外，术语“由…制成”可能意味着“包括”或“由…组成”。在本发明中，除非另有描述，否则短语“A、B和C中的一个”意味着“A、B和/或C”(A、B、C、A和B、A和C、B和C或A、B和C)，而不意味着来自A的一个元件、来自B的一个元件和来自C的一个元件。
在本发明中，提供了用于制造GAA FET和堆叠沟道FET的方法。应该注意，在本发明中，源极和漏极可互换使用并且它们的结构基本相同。
图1示出了根据本发明的实施例的示出制造工艺阶段的一个的GAA FET半导体器件的等轴视图。在X方向上延伸的一个或多个栅电极100设置在在Y方向上延伸的一个或多个鳍结构35上方。X方向基本上垂直于Y方向。鳍结构35形成在半导体衬底10上。鳍结构35的下部嵌入在隔离绝缘层45内，并且栅电极100包裹环绕半导体纳米线20。
图2至图18F示出了根据本发明的实施例的用于制造GAA FET的示例性顺序工艺。应该理解，可以在图2至图18F所示的工艺之前、期间和之后提供额外的操作，并且对于该方法的额外实施例，可以替换或消除下面描述的一些操作。操作/工艺的顺序可以互换。
图2示出了根据本发明的实施例的制造半导体FET器件的各个阶段的一个的截面图。如图2所示，提供了半导体衬底10。在一些实施例中，衬底10在至少其表面部分上包括单晶半导体层。衬底10可以包括单晶半导体材料，诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在某些实施例中，衬底10由晶体Si制成。
衬底10可以包括位于其表面区域中的一个或多个缓冲层(未示出)。缓冲层可用于将衬底的晶格常数逐渐改变为源极/漏极区域的晶格常数。缓冲层可以由外延生长单晶半导体材料形成，单晶半导体材料诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。
如图2所示，将杂质离子(掺杂剂)12注入至硅衬底10中以形成阱区域。实施离子注入以防止穿通效应。衬底10可以包括已经适当地掺杂有杂质(例如，p型或n型电导率)的各个区域。掺杂剂12是例如用于n型Fin FET的硼(BF2)和用于p型FinFET的磷。
之后，如图3所示，在衬底10上方形成第一半导体层15。在一些实施例中，第一半导体层15由第一半导体材料形成。在一些实施例中，第一半导体材料包括第一IV族元素和第二IV族元素。IV族元素选自由C、Si、Ge、Sn和Pb组成的组。在一些实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在某些实施例中，第一半导体材料是Si1-xGex，其中，0.3≤x≤0.9，并且在其他实施例中，0.4≤x≤0.7。
如图4所示，随后在第一半导体层15上方形成第二半导体层20。在一些实施例中，第二半导体层20由第二半导体材料形成。在一些实施例中，第二半导体材料包括第一IV族元素和第二IV族元素。在一些实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在一些实施例中，第一IV族元素和第二IV族元素在第二半导体材料中的量与在第一半导体材料中的量不同。在一些实施例中，第一半导体材料中的Ge的量大于第二半导体材料中的Ge的量。在某些实施例中，第二半导体材料是Si1-yGey，其中，0.1≤y≤0.5并且x>y，并且在其他实施例中，0.2≤y≤0.4。
下一步，如图5所示，在第二半导体层20上方形成另一第一半导体层15。另一第一半导体层15由与以上参照图3公开的相同的半导体材料形成。在另一第一半导体层15上方形成第三半导体层25。在一些实施例中，第三半导体层25由IV族元素制成。在一些实施例中，第三半导体层25由与衬底10相同的材料制成。
在一些实施例中，第一半导体层15、第二半导体层20和第三半导体层25由具有不同晶格常数的材料制成，并且可以包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP的一层或多层。在一些实施例中，第一半导体层15、第二半导体层20和第三半导体层25由不同的材料制成。在一个实施例中，第一半导体层15由Si1-xGex制成，其中，0.3≤x≤0.7，第二半导体层20由Si1-yGey制成，其中，0.2≤y≤0.5，其中，x>y，并且第三半导体层25由Si制成。
在一些实施例中，第一半导体层15的厚度为约0.5nm至约5nm，第二半导体层20的厚度为约3nm至约20nm，并且第三半导体层25的厚度为约2nm至约18nm。在其他实施例中，第一半导体层15的厚度为约0.5nm至约2nm，第二半导体层20的厚度为约5nm至约15nm，并且第三半导体层25的厚度为约3nm至约12nm。在一些实施例中，第二半导体层20的厚度大于第三半导体层25的厚度，并且第三半导体层25的厚度大于第一半导体层15的厚度。
第一半导体层15、第二半导体层20和第三半导体层25可以通过一个或多个外延或外延的(epi)工艺形成。外延工艺包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺。
下一步，在一些实施例中，如图6A所示，以重复序列ABAC堆叠额外的第一半导体层(A)15、第二半导体层(B)20和第三半导体层(C)25。在图6A中，示出了半导体层的三个重复序列ABAC，然而，重复序列的数量不限于三个，并且可以小至1(单层)，并且在一些实施例中，形成2至10个重复序列ABAC。在其他实施例中，如图6B所示，形成ACAB的重复序列。通过调整堆叠层的数量，可以调整GAA FET器件的驱动电流。
在衬底10由与第三半导体层25不同的材料制成的一些实施例中，形成在衬底10上的最下面的半导体层是第三半导体层(C)25。如图6C所示，在形成初始层第三半导体层(C)25之后，形成第一半导体层(A)15、第二半导体层(B)20、第一半导体层(A)15、第三半导体层(C)25的重复序列ABAC。
在一些实施例中，如图7所示，在最上面的半导体层上方形成掩模层30。掩模层30包括第一掩模层32和第二掩模层34。第一掩模层32是由氧化硅制成的垫氧化物层，其可以通过热氧化或化学汽相沉积(CVD)形成。第二掩模层34由CVD(包括低压CVD(LPCVD)和等离子体增强CVD(PECVD))、物理汽相沉积(PVD)、原子层沉积(ALD)或其他合适的工艺形成的氮化硅制成。通过使用包括光刻和蚀刻的图案化操作将掩模层30图案化成掩模图案。
下一步，如图8所示，通过使用图案化的掩模层来图案化第一半导体层15、第二半导体层20和第三半导体层25的堆叠层，从而堆叠层形成为在Y方向上延伸的鳍结构35。在图8中，两个鳍结构35布置在X方向上。但是鳍结构的数量不限于两个，并且可以小至一个以及三个或更多。在一些实施例中，在鳍结构35的两侧上形成一个或多个伪鳍结构以改进图案化操作中的图案保真度。如图8所示，鳍结构35具有由堆叠的半导体层15、20、25和阱部分40构成的上部。
在一些实施例中，鳍结构35的上部沿着X方向的宽度W1在从约5nm至约40nm的范围内，并且在其他实施例中在从约10nm至约30nm的范围内。在一些实施例中，鳍结构的沿着Z方向的高度H1在从约100nm至约200nm的范围内。
可以通过任何合适的方法图案化堆叠的鳍结构35。例如，可以使用一个或多个光刻工艺(包括双重图案化或多重图案化工艺)图案化该结构。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，从而允许创建具有例如比使用单一直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后去除牺牲层，并且之后可以使用剩余的间隔件来图案化堆叠的鳍结构35。
在形成鳍结构35之后，在衬底上方形成包括一个或多个绝缘材料层的绝缘材料层，使得鳍结构完全嵌入在绝缘层内。用于绝缘层的绝缘材料可以包括由LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、氟掺杂的硅酸盐玻璃(FSG)或低K介电材料。可以在绝缘层的形成之后实施退火操作。之后，实施诸如化学机械抛光(CMP)方法和/或回蚀刻方法的平坦化操作，从而使得最上面的第三半导体层25的上表面从绝缘材料层暴露。在一些实施例中，在形成绝缘材料层之前，在鳍结构上方形成鳍衬垫层50。鳍衬垫层50由Si3N4或基于氮化硅的材料(例如，SiON、SiCN或SiOCN)制成。
在一些实施例中，鳍衬垫层50包括在衬底10和鳍结构35的底部的侧壁上方形成的第一鳍衬垫层，以及形成在第一鳍衬垫层上的第二鳍衬垫层。在一些实施例中，每个衬垫层均具有介于约1nm和约20nm之间的厚度。在一些实施例中，第一鳍衬垫层包括氧化硅并且具有介于约0.5nm和约5nm之间的厚度，并且第二鳍衬垫层包括氮化硅并且具有介于约0.5nm和约5nm之间的厚度。可以通过诸如物理汽相沉积(PVD)、化学汽相沉积(CVD)或原子层沉积(ALD)的一个或多个工艺来沉积衬垫层，但是可以利用任何可接受的工艺。
之后，如图9所示，使绝缘材料层凹进以形成隔离绝缘层45，使得鳍结构35的上部暴露。通过该操作，鳍结构35通过隔离绝缘层45彼此电隔离，隔离绝缘层45也称为浅沟槽隔离(STI)。
在图9所示的实施例中，使隔离绝缘层45凹进直至暴露阱区域40的上部。在其他实施例中，不暴露阱区域40的上部。
如图10A和图10B所示，在形成隔离绝缘层45之后，形成牺牲(伪)栅极结构52。图10A是沿着X方向上(线A-A)的栅电极截取的截面图。图10B是沿着Y方向上(线B-B)的鳍结构截取的截面图。图10A和图10B示出了在暴露的鳍结构35上方形成牺牲栅极结构52之后的结构。牺牲栅极结构52形成在鳍结构35的将成为沟道区域的部分上方。牺牲栅极结构52限定了GAA FET的沟道区域。牺牲栅极结构52包括牺牲栅极介电层55和牺牲栅电极层60。牺牲栅极介电层55包括一个或多个绝缘材料层，绝缘材料诸如基于氧化硅的材料。在一个实施例中，使用由CVD形成的氧化硅。在一些实施例中，牺牲栅极介电层55的厚度在从约1nm至约5nm的范围内。
通过在鳍结构上方首先毯式沉积牺牲栅极介电层来形成牺牲栅极结构52。之后在牺牲栅极介电层上和鳍结构上方毯式沉积牺牲栅电极层，从而使得鳍结构完全嵌入在牺牲栅电极层内。牺牲栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中，牺牲栅电极层的厚度在从约100nm至约200nm的范围内。在一些实施例中，牺牲栅电极层经历平坦化操作。使用CVD(包括LPCVD和PECVD)、PVD、ALD或其他合适的工艺来沉积牺牲栅极介电层和牺牲栅电极层。随后，在牺牲栅电极层上方形成掩模层62。掩模层62包括垫氮化硅层65和氧化硅掩模层70。
下一步，如图10A和图10B所示，对掩模层62和牺牲栅电极层60实施图案化操作，并且将掩模层62和牺牲栅电极层60图案化成牺牲栅极结构52。牺牲栅极结构52包括牺牲栅极介电层55、牺牲栅电极层60(例如，多晶硅)以及包括氮化硅垫层65和氧化硅掩模层70的掩模层62。通过图案化牺牲栅极结构，在牺牲栅极结构的相对侧上部分地暴露第一、第二和第三半导体层的堆叠层，从而限定源极/漏极(S/D)区域。在本发明中，源极和漏极可互换使用，并且它们的结构基本相同。在图10A和图10B中，形成一个牺牲栅极结构52，但是牺牲栅极结构的数量不限于一个。在一些实施例中，在鳍结构的Y方向上布置两个或多个牺牲栅极结构。在某些实施例中，在牺牲栅极结构的两侧上形成一个或多个伪牺牲栅极结构以改进图案保真度。
如图11A至图11D所示，在形成牺牲栅极结构52之后，在暴露的鳍结构35和牺牲栅极结构52上方共形地形成由绝缘材料制成的覆盖层75。图11A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图11B是沿着Y方向(图1的线B-B)的鳍结构截取的截面图。图11C是沿着图1的线C-C截取的截面图。图11D是沿着图1的线D-D截取的截面图。覆盖层75以共形的方式沉积，使得其形成为在垂直表面(诸如，侧壁)、水平表面和牺牲栅极结构的顶部上分别具有基本相等的厚度。在一些实施例中，覆盖层75具有在从约2nm至约20nm的范围内的厚度，在其他实施例中，覆盖层75具有在从约5nm至约15nm的范围内的厚度。
在一些实施例中，覆盖层75包括第一覆盖层和第二覆盖层。第一覆盖层可以包括诸如SiOC和/或SiOCN的低k介电材料或任何其他合适的介电材料，并且第二覆盖层53可以包括Si3N4、SiON和SiCN中的一种或多种或任何其他合适的介电材料。在一些实施例中，第一覆盖层和第二覆盖层由不同的材料制成，使得它们可以被选择性地蚀刻。可以通过ALD或CVD或任何其他合适的方法形成第一覆盖层和第二覆盖层。
之后，如图12A至图12D所示，在一些实施例中，对覆盖层75进行各向异性蚀刻以去除形成在氧化硅掩模层70和源极/漏极区域上方的覆盖层75，并且之后向下去除源极/漏极区域中的第三半导体层25和衬底10的上部直至约隔离绝缘层45的上表面。图12A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图12B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图12C是沿着图1的线C-C截取的截面图。图12D是沿着图1的线D-D截取的截面图。使用合适的蚀刻操作去除第三半导体层25和衬底的上部。例如，当第三半导体层25是Si并且第一半导体层15和第二半导体层20是Ge或SiGe时，可以使用诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第三半导体层25。在一些实施例中，当形成p型FET时，去除第三半导体层25。
如图12C所示，使用合适的光刻和蚀刻技术，完全去除源极/漏极区域中的覆盖层75和牺牲栅极介电层55。
在其他实施例中，如图12E所示，使源极/漏极区域中的鳍结构向下凹进至约隔离绝缘层45的上表面。换句话说，去除源极/漏极区域中所有的第一、第二和第三半导体层以及衬底10的上部。图12E是沿着图1的线B-B截取的截面图。在一些实施例中，通过使用合适的蚀刻剂的凹槽蚀刻操作使鳍结构凹进。在一些实施例中，凹槽蚀刻操作是干蚀刻操作。在一些实施例中，当形成n型FET时，使源极/漏极区域中的鳍结构凹进。
随后，如图13A至图13D所示，形成源极/漏极外延层80。图13A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图13B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图13C是沿着图1的线C-C截取的截面图。图13D是沿着图1的线D-D截取的截面图。
源极/漏极外延层80包括用于n沟道FET的Si、SiP、SiC和SiCP或用于p沟道FET的Si、SiGe、Ge的一层或多层。对于P沟道FET，硼(B)也可以包含在源极/漏极中。通过使用CVD、ALD或分子束外延(MBE)的外延生长方法形成源极/漏极外延层80。如图13C所示，在一些实施例中，在鳍结构周围生长源极/漏极外延层80，并且生长的外延层在隔离绝缘层45之上合并并且随后限定空隙82。如图13D所示，源极/漏极外延层80形成为与设置在牺牲栅极结构52的侧面上方的覆盖层75接触。
在一些实施例中，源极/漏极外延层80的截面具有菱形形状、六边形形状、其他多边形形状或半圆形形状。
图13E和图13F示出了另一实施例，其中，源极/漏极外延层80形成在图12E的结构上。图13E是沿着图1的线C-C截取的截面图，并且图13F是沿着图1的线B-B截取的截面图。
随后，如图14A至图14D所示，形成层间介电(ILD)层85。图14A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图14B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图14C是沿着图1的线C-C截取的截面图。图14D是沿着图1的线D-D截取的截面图。
用于ILD层85的材料包括包含Si、O、C和/或H的化合物，诸如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于ILD层85。在形成ILD层85之后，实施诸如化学机械抛光(CMP)的平坦化操作，使得牺牲栅电极层60的顶部暴露。CMP也去除了覆盖层75的部分以及覆盖牺牲栅电极层60的上表面的掩模层62。
图14E和图14F示出了另一实施例，其中，ILD层85形成在图13E和图13F的结构上。图14E是沿着图1的线C-C截取的截面图，并且图14F是沿着图1的线B-B截取的截面图。
之后，如图15A至图15D所示，去除牺牲栅电极层60和牺牲栅极介电层55，从而形成栅极间隔90，其中，暴露鳍结构的沟道区域。图15A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图15B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图15C是沿着图1的线C-C截取的截面图。图15D是沿着图1的线D-D截取的截面图。
在牺牲栅极结构的去除期间，ILD层85保护S/D结构80。可以使用等离子体干蚀刻和/或湿蚀刻来去除牺牲栅极结构。当牺牲栅电极层60是多晶硅并且ILD层85是氧化硅时，可以使用诸如四甲基氢氧化铵(TMAH)溶液的湿蚀刻剂来选择性地去除牺牲栅电极层60。之后使用等离子体干蚀刻和/或湿蚀刻来去除牺牲栅极介电层55。
图15E是另一实施例的沿着图1的线C-C截取的截面图并且图15F是另一实施例的沿着图1的线B-B截取的截面图，其中，去除了图14F的牺牲栅电极层60和牺牲栅极介电层。
图15G是根据本发明的实施例的鳍结构的详细的截面图。在图15G所示的一个实施例中，第一半导体层15由具有约0.5nm至约5nm的厚度Z的Si0.5Ge0.5制成。第二半导体层20由具有约3nm至约20nm的厚度B的Si0.7Ge0.3制成。第三半导体层25由具有约2nm至约18nm的厚度A的Si制成。厚度A、B和Z的关系为B>A>Z。
如图16A至图16D所示，在去除牺牲栅极结构之后，去除鳍结构中的第三半导体层25，从而形成包括将第二半导体层20夹在中间的一对第一半导体层15的纳米线。图16A是沿着X方向上的栅电极(图1的线A-A)截取的截面图。图16B是沿着Y方向上的鳍结构(图1的线B-B)截取的截面图。图16C是沿着图1的线C-C截取的截面图。图16D是沿着图1的线D-D截取的截面图。
可以使用相对第一半导体层15和第二半导体层20而选择性蚀刻第三半导体层25的蚀刻剂来去除或蚀刻第三半导体层25。当第三半导体层25是Si并且第一半导体层15和第二半导体层20是Ge或SiGe时，可以使用诸如但不限于氢氧化铵(NH4OH)、四甲基氢氧化铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第三半导体层25。当第三半导体层25是Si并且衬底10是硅衬底时，第三半导体层25的蚀刻也去除了鳍结构的位于最下面的第一半导体层15下面的部分。当第三半导体层25和衬底10由不同的材料制成时，在一些实施例中实施额外的蚀刻操作以去除鳍结构的位于最下面的第一半导体层15下面的部分，以提供图16A和图16B所示的结构。在第三半导体层25和衬底10由不同的材料制成的其他实施例中，如图6C所示，在衬底10上形成初始第三半导体层25，其与其他第三半导体层25一起被去除，以提供图16A和图16B所示的结构。
图16E和图16F示出了另一实施例，其中，从图15F的结构去除第三半导体层25。图16E是沿着图1的线C-C截取的截面图，并且图16F是沿着图1的线B-B截取的截面图。
在一些实施例中，使用干蚀刻技术和湿蚀刻技术的组合来去除第三半导体层25。
在另一实施例中，通过使用合适的蚀刻技术去除第一半导体层15和第二半导体层20，并且获得由第三半导体层25制成的纳米线。
沟道区域中的半导体纳米线15、20的截面形状示出为矩形，但是可以是任何多边形形状(三角形、菱形等)、具有圆角的多边形形状、圆形或椭圆形(垂直或水平)。
如图17A至图17D所示，在形成第一半导体层15和第二半导体层20的半导体纳米线之后，在每个沟道层(第一半导体层15和第二半导体层20的线)周围形成栅极介电层95，并且在栅极介电层95上形成栅电极层100。图17A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图17B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图17C是沿着图1的线C-C截取的截面图。图17D是沿着图1的线D-D截取的截面图。
图17E和图17F示出了另一实施例，其中，在图16F的结构上形成栅极介电层95和栅电极层100。图17E是沿着图1的线C-C截取的截面图，并且图17F是沿着图1的线B-B截取的截面图。
在某些实施例中，栅极介电层95包括一个或多个介电材料层，介电材料诸如氧化硅、氮化硅或高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层95包括形成在沟道层和介电材料之间的界面层。
可以通过CVD、ALD或任何合适的方法形成栅极介电层95。在一个实施例中，使用诸如ALD的高度共形沉积工艺来形成栅极介电层95，以确保在每个沟道层周围形成具有均匀厚度的栅极介电层。在一些实施例中，栅极介电层95的厚度在从约1nm至约6nm的范围内。在一些实施例中，栅极介电层95也形成在暴露的源极/漏极外延层80上。
栅电极层100形成在栅极介电层95上以围绕每个沟道层。栅电极100包括一个或多个导电材料层，导电材料诸如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合。
可以通过CVD、ALD、电镀或其他合适的方法形成栅电极层100。栅电极层也沉积在ILD层85的上表面上方。之后通过使用例如CMP平坦化形成在ILD层85上方的栅极介电层和栅电极层，直至露出ILD层85的顶面。在一些实施例中，在平坦化操作之后，使栅电极层凹进并且在凹进的栅电极上方形成覆盖绝缘层(未示出)。覆盖绝缘层包括诸如Si3N4的一层或多层氮化硅基材料。可以通过沉积绝缘材料以及随后的平坦化操作形成覆盖绝缘层。
在本发明的某些实施例中，在栅极介电层95和栅电极100之间插入一个或多个功函调整层(未示出)。功函调整层由导电材料制成，导电材料诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层，或这些材料中的两种或多种的多层。对于n沟道FET，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种作为功函调整层，并且对于p沟道FET，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。可以通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺形成功函调整层。此外，对于可以使用不同的金属层的n沟道FET和p沟道FET，可以单独形成功函调整层。
在其他实施例中，在形成栅极介电层95和栅电极层100之前，去除设置在第二半导体层20的相对侧上的第一半导体层15，从而产生图18A至图18D所示的结构。可以通过诸如使用HF:HNO3:H2O的湿蚀刻的合适的蚀刻操作来去除第一半导体层15。图18A是沿着X方向上(图1的线A-A)的栅电极截取的截面图。图18B是沿着Y方向上(图1的线B-B)的鳍结构截取的截面图。图18C是沿着图1的线C-C截取的截面图。图18D是沿着图1的线D-D截取的截面图。通过使用合适的蚀刻技术，去除仅沟道区域中的设置在第二半导体层20的相对侧上的第一半导体层15。因此，在该实施例中，第一半导体层保留在源极/漏极区域80中。
图18E和图18F示出了另一实施例，其中，使源极/漏极区域中的鳍结构向下凹进至约隔离绝缘层45的上表面，如图18E所示，并且在凹槽中形成源极/漏极区域80。图18E是沿着图1的线C-C截取的截面图，并且图18F是沿着图1的线B-B截取的截面图。
随后，可以通过使用干蚀刻在ILD层85中形成接触孔(未示出)。在一些实施例中，蚀刻S/D外延层80的上部。在一些实施例中，在S/D外延层80上方形成硅化物层。硅化物层包括WSi、CoSi、NiSi、TiSi、MoSi和TaSi中的一种或多种。之后，在接触孔中形成导电材料(未示出)。导电材料包括Co、Ni、W、Ti、Ta、Cu、Al、TiN和TaN中的一种或多种。应该理解，GAA FET经历进一步的CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各个部件。
在图18A至图18F所示的一些实施例中，多条纳米线20中的每条在纳米线堆叠方向上分隔开的距离大于图17A至图17F中的多条纳米线15、20中的每条分隔开的距离。
在某些实施例中，半导体器件是n型GAA FET。在其他实施例中，半导体器件是p型GAA FET。在一些实施例中，在同一衬底10上提供一个或多个n型GAA FET和一个或多个p型GAA FET。
在本发明的实施例中，设置在第二半导体层的相对侧上的第一半导体层在蚀刻以去除沟道区域中的第三半导体层期间保护第二半导体层。在一些实施例中，具有比第二SiGe半导体层更高的Ge浓度的第一SiGe半导体层对用于去除Si第三半导体层的蚀刻剂具有高抵抗力，从而保护第二SiGe半导体层在第三半导体层蚀刻操作期间免受减薄。根据本发明形成的半导体器件具有改进的纳米线释放蚀刻的工艺窗口，使得器件良率更高。
上面概述了若干实施例或实例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例或实例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。
本发明的实施例是制造半导体器件的方法，包括：在半导体衬底上方形成具有第一组成的第一半导体层，以及在第一半导体层上方形成具有第二组成的第二半导体层。在第二半导体层上方形成具有第一组成的另一第一半导体层。在另一第一半导体层上方形成具有第三组成的第三半导体层。图案化第一半导体层、第二半导体层和第三半导体层以形成鳍结构。去除第三半导体层的部分，从而形成包括第二半导体层的纳米线，并且形成围绕纳米线导电材料。第一半导体层、第二半导体层和第三半导体层包括不同的材料。在实施例中，通过按顺序重复形成第一半导体层、形成第二半导体层、形成另一第一半导体层并且形成第三半导体层来形成第一半导体层、第二半导体层、另一第一半导体层和第三半导体层的交替堆叠件。在实施例中，在去除第三半导体层的部分之前，在鳍结构上方形成牺牲栅极结构。在实施例中，在去除第三半导体层的部分之前，去除鳍结构的未由牺牲栅极结构覆盖的部分，从而形成源极/漏极间隔。在实施例中，在源极/漏极间隔中形成源极/漏极区域。在实施例中，当形成纳米线时，去除半导体衬底的部分。在实施例中，第三半导体层和半导体衬底由相同的材料形成。在实施例中，相同的材料是硅。在实施例中，第一半导体材料是Si1-xGex，并且第二半导体材料是Si1-yGey，其中，x>y。
在本发明的另一实施例中，制造半导体器件的方法包括：在半导体衬底上方形成鳍结构，其中，第一半导体层A、第二半导体层B和第三半导体层C以重复序列ABAC堆叠。第一半导体层、第二半导体层和第三半导体层包括不同的材料。牺牲栅极结构限定鳍结构上方的栅极区域。从鳍结构的未由牺牲栅极结构覆盖的源极/漏极区域去除第三半导体层。在源极/漏极区域中形成源极/漏极外延层。去除牺牲栅极结构，并且从栅极区域去除第三半导体层。在栅极区域中形成栅电极结构，其中，栅电极结构包裹环绕第一和第二半导体层。在实施例中，当去除第三半导体层时，去除半导体衬底的部分。在实施例中，第三半导体层和半导体衬底由相同的材料形成。在实施例中，相同的材料是IV族元素。在实施例中，第一半导体材料是Si1-xGex，并且第二半导体材料是Si1-yGey，其中，x>y。在实施例中，0.3≤x≤0.9并且0.1≤y≤0.5。在实施例中，外延形成第一半导体层和第二半导体层，并且在外延操作期间，增加Ge浓度以形成第一半导体层并且减小Ge浓度以形成第二半导体层。在实施例中，第二半导体层的厚度大于第三半导体层的厚度。
在本发明的实施例中，制造半导体器件的方法包括：形成第一鳍结构和第二鳍结构，其中，在第一鳍结构和第二鳍结构中，第一半导体层和第二半导体层交替堆叠。在第一鳍结构上方形成第一牺牲栅极结构，并且在第二鳍结构上方形成第二牺牲栅极结构。在第二鳍结构和第二牺牲栅极结构上方形成第一保护层。去除未由第一牺牲栅极结构覆盖的第一鳍结构的源极/漏极区域中的第一半导体层，从而形成第一源极/漏极间隔。在第一源极/漏极间隔中形成第一源极/漏极外延层，从而形成第一结构。在第一鳍结构和第一牺牲栅极结构上方形成第二保护层。去除未由第二牺牲栅极结构覆盖的第二鳍结构的源极/漏极区域中的第二半导体层，从而形成第二源极/漏极间隔。去除第二源极/漏极间隔中的第二源极/漏极外延层，从而形成第二结构。去除第一栅极区域中的第一牺牲栅极结构和第一半导体层以形成第一栅极间隔。去除第二栅极区域中的第二牺牲栅极结构和第二半导体层以形成第二栅极间隔。分别在第一和第二栅极间隔中形成第一和第二栅电极结构。第一半导体层包括第一子层和设置在第一子层的相对侧上的第二子层，第一子层由包括第一IV族元素和第二IV族元素的合金形成，并且第二子层由包括第一IV族元素和第二IV族元素的合金形成。第一IV族元素和第二IV族元素在第一子层和在第二子层中的量不同。在实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在实施例中，第一子层的组成是Si1-yGey，其中，0.1≤y≤0.5，并且第二子层的组成是Si1-xGex，其中，0.3≤x≤0.9。
在本发明的实施例中，半导体器件包括：设置在半导体衬底上方的至少一条半导体纳米线，以及包裹环绕至少一条半导体纳米线的栅极结构。源极/漏极结构设置在栅极结构的相对侧上的半导体衬底上方。至少一条半导体纳米线包括由第一半导体材料组成的两个相对的第一层，与第一半导体材料不同的第二半导体材料的第二层，第二层夹在两个相对的第一层之间。在实施例中，第一半导体材料包括第一IV族元素和第二IV族元素，第二半导体材料包括第一IV族元素和第二IV族元素，并且第一IV族元素和第二IV族元素在第一半导体材料和第二半导体材料中的量不同。在实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在实施例中，第一半导体材料是Si1-xGex，第二半导体材料是Si1-yGey，并且x>y。在实施例中，0.3≤x≤0.9，并且0.1≤y≤0.5。在实施例中，第一层的厚度为0.5nm至2nm，并且第二层的厚度为3nm至15nm。在实施例中，源极/漏极结构包裹环绕至少一条纳米线。在实施例中，绝缘侧壁设置在源极/漏极结构和栅极结构之间。在实施例中，栅极结构包括高k介电层和金属栅电极层。
在本发明的实施例中，半导体器件包括：多条半导体线，多条半导体线沿着第一方向布置为堆叠件设置在衬底上方，第一方向基本垂直于衬底的主表面。第一源极/漏极区域与第一半导体线的端部接触。栅极介电层设置在第一半导体线的每个沟道区域上并且包裹环绕第一半导体线的每个沟道区域。栅电极层设置在栅极介电层上并且包裹环绕每个沟道区域。至少一条半导体纳米线包括由第一半导体材料组成的两个相对的第一层，与第一半导体材料不同的第二半导体材料的第二层，第二层夹在两个相对的第一层之间，并且第一层和第二层沿着第一方向布置。在实施例中，第一半导体材料包括第一IV族元素和第二IV族元素，第二半导体材料包括第一IV族元素和第二IV族元素，并且第一IV族元素和第二IV族元素在第一半导体材料和第二半导体材料中的量不同。在实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在实施例中，第一半导体材料是Si1-xGex，第二半导体材料是Si1- yGey，并且x>y。在实施例中，第一层的厚度为0.5nm至2nm，并且第二层的厚度为3nm至15nm。在实施例中，源极/漏极结构包裹环绕每条纳米线。在实施例中，绝缘侧壁包括在源极/漏极区域和栅电极层之间。
在本发明的实施例中，半导体器件包括：第一纳米线结构和第二纳米线结构，其中，第一纳米线结构和第二纳米线结构都包括沿着第一方向延伸并且沿着基本垂直于第一方向的第二方向堆叠的多条纳米线。第一和第二栅电极分别设置在第一和第二纳米线结构上方，其中，第一和第二电极分别包裹环绕第一和第二纳米线的纳米线。第一纳米线由包括第一半导体材料的第一子层和包括第二半导体材料的设置在第一子层的相对侧上的第二子层组成。第二纳米线由第三半导体材料组成，并且第一、第二和第三半导体材料是不同的材料。在实施例中，第一半导体材料是包括第一IV族元素和第二IV族元素的合金，第二半导体材料是包括第一IV族元素和第二IV族元素的合金，第三半导体材料是第一和第二IV族元素中的一种，并且第一IV族元素和第二IV族元素在第一半导体材料和第二半导体材料中的量不同。在实施例中，第一IV族元素是Si并且第二IV族元素是Ge。在实施例中，第一半导体材料的组成是Si1-yGey，其中，0.1≤y≤0.5，并且第二半导体材料的组成是Si1-xGex，其中，0.3≤x≤0.9。
在本发明的实施例中，制造半导体器件的方法包括：形成鳍结构，该鳍结构包括以此顺序设置的第一第一半导体层、第一第二半导体层、第三半导体层、第二第二半导体层和第二第一半导体层。在鳍结构上面形成包括牺牲栅极介电层和牺牲栅电极层的牺牲栅极结构。在牺牲栅极结构的相对侧上的鳍结构上方形成源极和漏极区域。在源极/漏极区域上方形成层间介电层。去除牺牲栅极结构。去除器件的沟道区域中的第一半导体层和第二半导体层，从而形成第三半导体层的纳米线。在沟道区域中形成包裹环绕纳米线的高k栅极介电层和金属栅电极。
根据本发明的一些实施例，提供了一种制造半导体器件的方法，包括：在半导体衬底上方形成具有第一组成的第一半导体层；在所述第一半导体层上方形成具有第二组成的第二半导体层；在所述第二半导体层上方形成具有所述第一组成的另一第一半导体层；在所述另一第一半导体层上方形成具有第三组成的第三半导体层；图案化所述第一半导体层、所述第二半导体层和所述第三半导体层以形成鳍结构；去除所述第三半导体层的部分，从而形成包括所述第二半导体层的纳米线；以及形成围绕所述纳米线的导电材料，其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料。
在上述方法中，通过按顺序重复形成所述第一半导体层、形成所述第二半导体层、形成所述另一第一半导体层以及形成所述第三半导体层来形成所述第一半导体层、所述第二半导体层、所述另一第一半导体层和所述第三半导体层的交替堆叠件。
在上述方法中，还包括：在去除所述第三半导体层的部分之前，在所述鳍结构上方形成牺牲栅极结构。
在上述方法中，还包括：在去除所述第三半导体层的部分之前，去除所述鳍结构的未由所述牺牲栅极结构覆盖的部分，从而形成源极/漏极间隔。
在上述方法中，还包括，在所述源极/漏极间隔中形成源极/漏极区域。
在上述方法中，还包括，当形成所述纳米线时，去除所述半导体衬底的部分。
在上述方法中，所述第三半导体层和所述半导体衬底由相同的材料形成。
在上述方法中，所述相同的材料是硅。
在上述方法中，所述第一半导体材料是Si1-xGex，并且所述第二半导体材料是Si1- yGey，其中，x>y。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：在半导体衬底上方形成鳍结构，其中，第一半导体层A、第二半导体层B和第三半导体层C以重复序列ABAC堆叠，其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料；形成牺牲栅极结构，所述牺牲栅极结构限定所述鳍结构上方的栅极区域；从所述鳍结构的未由所述牺牲栅极结构覆盖的源极/漏极区域去除所述第三半导体层；在所述源极/漏极区域中形成源极/漏极外延层；去除所述牺牲栅极结构；从所述栅极区域去除所述第三半导体层；以及在所述栅极区域中形成栅电极结构，其中，所述栅电极结构包裹环绕所述第一半导体层和所述第二半导体层。
在上述方法中，还包括，当去除所述第三半导体层时，去除所述半导体衬底的部分。
在上述方法中，所述第三半导体层和所述半导体衬底由相同的材料形成。
在上述方法中，所述相同的材料是IV族元素。
在上述方法中，所述第一半导体材料是Si1-xGex，所述第二半导体材料是Si1-yGey，并且所述第三半导体材料是硅，其中，x>y。
在上述方法中，0.3≤x≤0.9并且0.1≤y≤0.5。
在上述方法中，外延形成所述第一半导体层和所述第二半导体层，并且在所述外延操作期间，增加Ge浓度以形成所述第一半导体层并且减小Ge浓度以形成所述第二半导体层。
在上述方法中，所述第二半导体层的厚度大于所述第三半导体层的厚度。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：至少一条半导体纳米线，设置在半导体衬底上方；栅极结构，包裹环绕所述至少一条半导体纳米线；以及源极/漏极结构，设置在所述栅极结构的相对侧上的所述半导体衬底上方，其中，所述至少一条半导体纳米线包括由第一半导体材料组成的两个相对的层，第二半导体材料的层夹在所述两个相对的层之间，所述第二半导体材料与所述第一半导体材料不同。
在上述半导体器件中，所述第一半导体材料包括第一IV族元素和第二IV族元素，并且所述第二半导体材料包括第一IV族元素和第二IV族元素，所述第一IV族元素和所述第二IV族元素在所述第一半导体材料和在所述第二半导体材料中的量不同。
在上述半导体器件中，所述第一IV族元素是Si并且所述第二IV族元素是Ge。
应该理解，不是所有的优势都必需在此处讨论，没有特定的优势对于所有实施例或实例都是需要的，并且其他实施例或实例可以提供不同的优势。

Claims (10)

1.一种制造半导体器件的方法，包括：
在半导体衬底上方形成具有第一组成的第一半导体层；
在所述第一半导体层上方形成具有第二组成的第二半导体层；
在所述第二半导体层上方形成具有所述第一组成的另一第一半导体层；
在所述另一第一半导体层上方形成具有第三组成的第三半导体层；
图案化所述第一半导体层、所述第二半导体层和所述第三半导体层以形成鳍结构；
去除所述第三半导体层的部分，从而形成包括所述第二半导体层的纳米线；以及
形成围绕所述纳米线的导电材料，
其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料。
2.根据权利要求1所述的方法，其中，通过按顺序重复形成所述第一半导体层、形成所述第二半导体层、形成所述另一第一半导体层以及形成所述第三半导体层来形成所述第一半导体层、所述第二半导体层、所述另一第一半导体层和所述第三半导体层的交替堆叠件。
3.根据权利要求1所述的方法，还包括：
在去除所述第三半导体层的部分之前，在所述鳍结构上方形成牺牲栅极结构。
4.根据权利要求3所述的方法，还包括：
在去除所述第三半导体层的部分之前，去除所述鳍结构的未由所述牺牲栅极结构覆盖的部分，从而形成源极/漏极间隔。
5.根据权利要求4所述的方法，还包括，在所述源极/漏极间隔中形成源极/漏极区域。
6.根据权利要求1所述的方法，还包括，当形成所述纳米线时，去除所述半导体衬底的部分。
7.根据权利要求1所述的方法，其中，所述第三半导体层和所述半导体衬底由相同的材料形成。
8.根据权利要求7所述的方法，其中，所述相同的材料是硅。
9.一种制造半导体器件的方法，包括：
在半导体衬底上方形成鳍结构，其中，第一半导体层A、第二半导体层B和第三半导体层C以重复序列ABAC堆叠，
其中，所述第一半导体层、所述第二半导体层和所述第三半导体层包括不同的材料；
形成牺牲栅极结构，所述牺牲栅极结构限定所述鳍结构上方的栅极区域；
从所述鳍结构的未由所述牺牲栅极结构覆盖的源极/漏极区域去除所述第三半导体层；
在所述源极/漏极区域中形成源极/漏极外延层；
去除所述牺牲栅极结构；
从所述栅极区域去除所述第三半导体层；以及
在所述栅极区域中形成栅电极结构，其中，所述栅电极结构包裹环绕所述第一半导体层和所述第二半导体层。
10.一种半导体器件，包括：
至少一条半导体纳米线，设置在半导体衬底上方；
栅极结构，包裹环绕所述至少一条半导体纳米线；以及
源极/漏极结构，设置在所述栅极结构的相对侧上的所述半导体衬底上方，
其中，所述至少一条半导体纳米线包括由第一半导体材料组成的两个相对的层，第二半导体材料的层夹在所述两个相对的层之间，所述第二半导体材料与所述第一半导体材料不同。
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