CN106952956A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106952956A
CN106952956A CN201610949316.4A CN201610949316A CN106952956A CN 106952956 A CN106952956 A CN 106952956A CN 201610949316 A CN201610949316 A CN 201610949316A CN 106952956 A CN106952956 A CN 106952956A
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region
layer
drain
source
channel region
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冯家馨
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • F24F11/00—Control or safety arrangements
    • F24F11/62—Control or safety arrangements characterised by the type of control or by internal processing, e.g. using fuzzy logic, adaptive control or estimation of values
    • F24F11/63—Electronic processing
    • F24F11/65—Electronic processing for selecting an operating mode
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F24—HEATING; RANGES; VENTILATING
    • F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
    • F24F11/00—Control or safety arrangements
    • F24F11/70—Control systems characterised by their outputs; Constructional details thereof
    • F24F11/80—Control systems characterised by their outputs; Constructional details thereof for controlling the temperature of the supplied air
    • F24F11/83—Control systems characterised by their outputs; Constructional details thereof for controlling the temperature of the supplied air by controlling the supply of heat-exchange fluids to heat-exchangers
    • F24F11/85—Control systems characterised by their outputs; Constructional details thereof for controlling the temperature of the supplied air by controlling the supply of heat-exchange fluids to heat-exchangers using variable-flow pumps
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F24—HEATING; RANGES; VENTILATING
    • F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
    • F24F2140/00—Control inputs relating to system states
    • F24F2140/20—Heat-exchange fluid temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

一种半导体器件包括在衬底上方设置的第一沟道区域、在衬底上方设置的且连接至第一沟道区域的第一源极区域和第一漏极区域从而使得第一沟道区域设置在第一源极区域和第一漏极区域之间、在第一沟道区域上且围绕第一沟道区域设置的栅极介电层、在栅极介电层上设置的且围绕第一沟道区域的栅电极层以及第二源极区域和第二漏极区域，第二源极区域和第二漏极区域分别设置在衬底上方且在第一源极区域和第一漏极区域下方。第二源极区域和第二漏极区域与栅极介电层接触。第一源极区域和第一漏极区域的晶格常数不同于第二源极区域和第二漏极区域的晶格常数。本发明实施例涉及具有全环栅结构的半导体器件及其制造工艺。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体集成电路，且更具体地涉及具有全环栅结构的半导体器件及其制造工艺。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如鳍FET(FinFET)和全环栅(GAA)FET的诸如多栅极场效应晶体管(FET)的三维设计的发展。在FinFET中，栅电极邻近具有在其间插入的栅极介电层的沟道区域的三个侧面。由于栅极结构环绕(围绕)在三个表面上的鳍，晶体管基本上具有控制穿过鳍或沟道区域的电流的三个栅极。遗憾地，沟道的第四侧、底部远离栅电极并且因此不受栅极的严密控制。相比之下，在GAA FET中，沟道区域的所有侧表面由栅电极围绕，这允许在沟道区域中更完全消耗且导致短沟道效应更少(由于亚阈值电流摆动(SS)更陡峭和漏极感应势垒降低(DIBL)更小)。
随着晶体管尺寸持续低成比例减小至亚20nm至25nm的技术节点，需要GAA FET的进一步改善。
发明内容
根据本发明的一个实施例，提供了一种半导体器件，包括：第一沟道区域，设置在衬底上方；第一源极区域和第一漏极区域，设置在所述衬底上方且连接至所述第一沟道区域使得所述第一沟道区域设置在所述第一源极区域和所述第一漏极区域之间；栅极介电层，设置在所述第一沟道区域上且围绕所述第一沟道区域；栅电极层，设置在所述栅极介电层上且围绕所述第一沟道区域；以及第二源极区域和第二漏极区域，分别设置在所述衬底上方且设置在所述第一源极区域和所述第一漏极区域下方，其中：所述第二源极区域和所述第二漏极区域与所述栅极介电层接触，以及所述第一源极区域和所述第一漏极区域的晶格常数不同于所述第二源极区域和所述第二漏极区域的晶格常数。
根据本发明的另一实施例，还提供了一种半导体器件，包括p沟道场效应晶体管和n沟道场效应晶体管，其中：所述p沟道场效应晶体管和所述n沟道场效应晶体管的每个均包括：设置在衬底上方的鳍结构；部分地覆盖所述鳍结构的栅极结构；以及形成在所述鳍结构上方的未被所述栅极结构覆盖的源极和漏极结构，所述p沟道场效应晶体管和所述n沟道场效应晶体管的每个的所述栅极结构均包括：设置在所述衬底上方的第一沟道区域；设置在所述第一沟道区域上且围绕所述第一沟道区域的栅极介电层；以及设置在所述栅极介电层上且围绕所述第一沟道区域的栅电极层，以及在所述p沟道场效应晶体管中：所述源极和漏极结构包括第一源极和漏极层和具有与所述第一源极和漏极层的晶格常数不同的晶格常数的第二源极和漏极层，所述第一源极和漏极层连接至所述第一沟道区域，所述第一源极和漏极层具有与所述第一沟道区域的晶格常数不同的晶格常数，以及所述第二源极和漏极层的侧面与所述栅极介电层接触。
根据本发明的又一实施例，还提供了一种用于制造半导体器件的方法，包括：在衬底上方在垂直方向上形成被第二半导体层夹住的第一半导体层；将所述第一半导体层和所述第二半导体层图案化为鳍结构使得所述鳍结构包括由所述第二半导体层制成的牺牲层和由所述第一半导体层制成的沟道区域；在所述鳍结构上方形成牺牲栅极结构使得所述牺牲栅极结构覆盖所述鳍结构的部分而所述鳍结构的剩余部分仍然暴露；去除所述鳍结构的未由所述牺牲栅极结构覆盖的所述剩余部分；形成源极/漏极区域；去除所述牺牲栅极结构；在去除所述牺牲栅极结构之后去除所述鳍结构中的所述牺牲层以暴露所述沟道区域；在暴露的所述沟道区域周围形成栅极介电层和栅电极层，其中：形成所述源极/漏极区域包括：去除所述第一半导体层从而使得暴露所述第二半导体层的至少一个；以及在暴露的所述第二半导体层上和周围形成第一源极/漏极层，所述第一源极/漏极层连接至所述沟道区域，所述第二半导体层的在所述源极/漏极区域中的侧面与所述栅极介电层接触，以及所述第一源极/漏极层的晶格常数不同于所述第二半导体层的晶格常数，且所述第一源极/漏极层的晶格常数不同于所述沟道区域的晶格常数。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图17B示出了根据本发明的一个实施例的用于制造GAA FET器件的示例性顺序工艺。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。另外，术语“由...制成”可以意为“包括”或者“由...组成”。
图1至图17B示出了根据本发明的一个实施例的用于制造GAA FET器件的示例性顺序工艺。应该理解，可以在由图1至图17B示出的工艺之前、期间和/或之后提供附加操作，并且对于方法的额外的实施例，可以替代或消除以下所描述的一些操作。操作/工艺的顺序可交换。
用于形成GAA FET的普遍制造流程在美国专利申请第14/675160号中描述，其全部内容结合于此作为参考。美国专利申请第14/675160号中描述的用于形成GAA FET的普遍制造流程包括：对衬底实施抗穿通注入；在衬底上方形成硅锗层和半导体堆叠件；图案化硅锗层和半导体堆叠件；氧化；形成STI区和使STI区凹进；形成伪栅极堆叠件；形成源极/漏极区；形成ILD；去除伪栅极堆叠件；去除氧化硅锗和剩余的硅锗；硅条的氧化；从核心区去除氧化硅环；形成栅极电介质；形成栅电极。
如图1所示，在衬底10中形成用于n沟道FET(n沟道区域)的p阱11和用于p沟道FET(p沟道区域)的n阱12。在一个实施例中，衬底10包括至少位于衬底10表面部分上的单晶半导体层。衬底10可以包括单晶半导体材料，诸如但不限制于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在本实施例中，衬底10由Si制成。
在一些实施例中，衬底10包括位于其表面区域中的一个或多个缓冲层。缓冲层可以用作逐渐从衬底的晶格常数改变为源极/漏极区域的晶格常数。缓冲层可以形成于外延生长单晶半导体材料，诸如但不限制于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在具体实施例中，衬底10包括在硅衬底10上外延生长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从用于最底部缓冲层的30％的锗增加至用于最顶部缓冲层的70％的锗。
如图2所示，在衬底上方形成堆叠的半导体层。堆叠的半导体层包括为牺牲半导体层的第一半导体层30和第二半导体层35。第一半导体层30随后形成在FET的沟道区域内且第二半导体层35最终被去除。第一半导体层30和第二半导体层35是由具有不同晶格常数的材料制成的，且可以包括诸如但不限制于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP的一层或多层。
在一些实施例中，第一半导体层30和第二半导体层35是由Si、Si的化合物、SiGe、Ge或Ge的化合物制成的。在一个实施例中，第一半导体层30是Si1-xGex(其中，x大于约0.3)或Ge以及第二半导体层35是Si或Si1-xGex(其中，x小于约0.4)，并且第二半导体层35的Ge浓度小于第一半导体层30的Ge浓度。在另一实施例中，第二半导体层35是Si1-xGex，(其中，x大于约0.3)或Ge以及第一半导体层30是Si或Si1-xGex(其中，x小于约0.4)，并且第二半导体层35的Ge浓度大于第一半导体层30的Ge浓度。在其它实施例中，第一半导体层30是由Si1-xGex制成的(其中，x在从约0.3至约0.8的范围内)，以及第二半导体层35是由Si1-xGex制成的(其中，x在从约0.1至约0.4的范围内)。在其它实施例中，第二半导体层35可以掺杂有硼。
在图2中，设置两层第一半导体层30和两层第二半导体层35。然而，层的数量不限制于两个，且可以小至1(每层)和大于2，并且在一些实施例中，形成第一半导体层和第二半导体层中的每个的3至6层。通过调整第二半导体层的数量，可以调整GAA FET器件的驱动电流。
在衬底10上方外延地形成第一半导体层30和第二半导体层35。在一些实施例中，第一半导体层30的厚度等于或大于第二半导体层35的厚度，并且在从约5nm至约50nm的范围内，或在从约10nm至约30nm的范围内。第二半导体层35的厚度在从约5nm至约30nm的范围内，并且可以在从约10nm至约20nm的范围内。第一半导体层30的厚度可以彼此相同或可以变化。
在一些实施例中，底部第二半导体层35B(最接近于衬底10的层)厚于剩余的第二半导体层。在一些实施例中，底部第二半导体层35B的厚度在从约10nm至约50nm的范围内，并且在其他实施例中，该厚度在从约20nm至约40nm的范围内。
接下来，如图3A和3B所示，使用包括光刻和蚀刻的图案化操作图案化第一和第二半导体层30、35的堆叠的层，从而沿着Y方向在鳍结构33内形成堆叠的层。图3B示出了平面图和图3A对应于图3B的线X1-X1。还蚀刻衬底10的部分(p阱和n阱)从而鳍结构的底部包括衬底10的部分。在蚀刻中，可以使用包括氧化硅和/或氮化硅的这样的光刻胶图案或硬掩模图案的掩模图案。
在一些实施例中，鳍结构的沿X方向的宽度W1在从约20nm至约40nm的范围内，并且该宽度在从约25nm至约30nm的范围内。宽度W1基本上限定GAA FET的沟道长度。鳍结构的沿Z方向的高度H1在从约100nm至约200nm的范围内。
如图4所示，在形成鳍结构之后，在衬底上方形成包括一层或多层绝缘材料的绝缘层19从而完全地嵌入鳍结构33。用于绝缘层19的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂硅酸盐玻璃(FSG)或低K介电材料。在形成绝缘层19之后可以实施退火操作。然后，实施诸如化学机械抛光(CMP)方法和/或回蚀刻方法的平坦化操作从而鳍结构的上表面从绝缘材料层暴露。
然后，如图5所示，凹进绝缘层19以形成隔离层20(或所谓的“浅沟槽隔离”(STI))。在一个实施例中，如图5所示，隔离层20的上表面位于底部第二半导体层35B的底部处。在其它实施例中，隔离层20的上表面位于底部第二半导体层35B的上表面和下表面之间。鳍结构从隔离层20的上表面沿Z方向的高度H2在从约80nm至约120nm的范围内。
图6A至图6D示出了在形成牺牲栅极结构之后的结构。图6D是平面图，图6A是沿图6D的线Y1-Y1的截面图，图6B是沿图6D的线X2-X2的截面图，且图6C是沿图6D的线X3-X3的截面图。
牺牲栅极结构包括牺牲栅电极40和牺牲栅极介电层45。在将为沟道区域的鳍结构上方形成牺牲栅极结构。牺牲栅极结构限定GAA FET的沟道区域。
通过在鳍结构和隔离层20上方第一毯式沉积牺牲栅极介电层形成牺牲栅极结构。牺牲栅极介电层包括氧化硅、氮化硅或氮氧化硅的一层或多层。在一些实施例中，牺牲栅极介电层的厚度在从约1nm至约5nm的范围内。然后，在牺牲栅极介电层上和鳍结构上方毯式沉积牺牲栅电极层从而鳍结构完全嵌入在牺牲栅电极层中。牺牲栅电极层包括诸如多晶硅或非晶硅的硅。在一些实施例中，牺牲栅电极层的厚度在从约100nm至约200nm的范围内。在一些实施例中，牺牲栅电极层经受平坦化操作。使用包括低压CVD(LPCVD)和等离子体增强CVD(PECVD)的化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或其它合适的工艺沉积牺牲栅极介电层和牺牲栅电极层。
接下来，实施图案化操作以形成牺牲栅电极40和牺牲栅极介电层45。在牺牲半导体层35的去除期间牺牲栅极结构用于随后地保护鳍结构的沟道区域。如图6A和图6B所示，通过图案化牺牲栅极结构，在牺牲栅极结构的相对侧上部分地暴露第一半导体层和第二半导体层的堆叠的层。在牺牲栅电极40的图案化和形成期间，牺牲栅极介电层用作蚀刻停止层，从而防止鳍受到破坏。使用干和/或湿蚀刻工艺从鳍结构的顶部和侧壁去除牺牲栅极介电层。
如图7A所示，在形成牺牲栅极结构之后，在牺牲栅电极40的顶部上方形成保护帽47。图7A是对应于图6D中的线Y1-Y1的截面图，以及图7B是对应于图6D的线X2-X2的截面图。保护帽47是选择结构，且在一些实施例中，不形成保护帽47。
此外，如图8A和图8B所示，在牺牲栅极结构的相对侧壁上形成侧壁间隔件层140。图8A是对应于图6D中的线Y1-Y1的截面图，以及图8B是对应于图6D的线X2-X2的截面图。
可以使用CVD或其他合适的工艺来形成侧壁间隔件层140。在一个实施例中，诸如但不限制于包括SiN、SiON、SiOCN或SiCN以及它们的组合的基于氮化硅的材料的共形介电间隔件层是在所有结构上方沉积的第一毯。以共形地方式沉积介电间隔件层使其在两个垂直表面(诸如侧壁)和水平面(诸如牺牲栅极结构的顶部)上形成至基本上相同的厚度。在一些实施例中，将介电间隔件层沉积至在从约2nm至约10nm的范围内的厚度。接下来，使用例如反应离子蚀刻(RIE)在介电间隔件层上实施各向异性蚀刻。在各项异性蚀刻工艺期间，绝大多数介电间隔件层从水平表面去除，在诸如牺牲栅极结构的侧壁和暴露的鳍的侧壁的垂直表面上留下介电间隔件层。接下来，实施各项同性蚀刻以从暴露的鳍结构的侧壁去除剩余的介电间隔件层，在牺牲栅极结构的相对侧壁上留下侧壁间隔件层140。在本实施例中，各项同性蚀刻是湿蚀刻工艺。
如图9B所示，然后，去除在n阱12(即，p沟道区域)上方形成的侧壁间隔件层140。图9A是对应于图6D中的线Y1-Y1的截面图，以及图9B是对应于图6D的线X2-X2的截面图。
可以通过干蚀刻和/或湿蚀刻去除侧壁间隔件层140。在蚀刻工艺期间，在p阱11(即，n沟道FET区域)上方形成的鳍结构由例如光刻胶层覆盖。此外，在牺牲栅极结构40上设置的侧壁间隔件层140受到保护帽47的保护免受蚀刻的影响。
在如图9B所示的一些实施例中，在隔离层20的表面附近保留侧壁间隔件层140的小部件(small piece)142。在其它实施例中，从n阱12(即，p沟道FET区域)上方的鳍结构完全地去除侧壁间隔件层140。
在从用于p沟道FET的鳍结构去除侧壁间隔件层140之后，从未被栅极结构覆盖的p沟道FET的鳍结构去除第一半导体层30。图10A是对应于图6D中的线Y1-Y1的截面图，以及图10B是对应于图6D的线X2-X2的截面图。
可以使用蚀刻剂去除第一半导体层30，该蚀刻剂可以选择性地蚀刻第一半导体层30而不蚀刻第二半导体层35。
当第一半导体层30是Ge或基于Ge的化合物且第二半导体层35是Si或SiGe时，可以使用诸如但不限制于氢氧化铵(NH4OH)、氢氧化四甲铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第一半导体层30。
当第一半导体层30是Si或基于Si的化合物且第二半导体层35是Ge或SiGe时，可以使用诸如但不限制于氢氧化铵(NH4OH)、氢氧化四甲铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除第一半导体层30。
如图10A所示，该操作不去除栅极结构下方的第一半导体层30。
然后，如图11A和图11B所示，在p沟道区域中的第二半导体层35上和周围形成p沟道FET的第一源极/漏极(S/D)层210。图11A是对应于图6D中的线Y1-Y1的截面图，以及图11B是对应于图6D的线X2-X2的截面图。用于第一S/D层210的材料可以是Si、Ge、SiGe、GeSn、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP的一个或多个。
在本实施例中，第一S/D层210包括Si1-xGex，其中x等于或大于0.3，并且在一些实施例中，x是在从约0.3至约0.8的范围内。在本发明中Si1-xGex可以简单地称为SiGe。
在形成p沟道S/D结构之后，如图12A和图12B所示，去除位于p阱11上方的用于n沟道FET的鳍结构(包括第一半导体层30和第二半导体层35)。图12A是对应于图6D中的线Y1-Y1的截面图，以及图12B是对应于图6D的线X2-X2的截面图。因此，形成由侧壁间隔件层140限定的间隔145。
然后，如图13A和图13B所示，在间隔145中形成第二S/D层215。图13A是对应于图6D中的线Y1-Y1的截面图，以及图13B是对应于图6D的线X2-X2的截面图。用于第一S/D层210的材料可以是Si、Ge、SiGe、GeSn、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP的一个或多个。在本实施例中，第二S/D层215包括Si1-xGex，其中x等于或大于0.4，并且在一些实施例中，x是大于约0.7至约1.0。
如图14A和图14B所示，在形成n沟道FET的S/D结构之后，在整个结构上方形成层间介电层(ILD)50并且然后通过CMP操作平坦化层间介电层50的上部从而暴露牺牲栅电极层40。图14A是对应于图6D中的线Y1-Y1的截面图，以及图14B是对应于图6D的线X2-X2的截面图。
ILD层50的材料可包括诸如SiCOH和SiOC的含有Si、O、C和/或H的化合物。诸如聚合物的有机材料可用于ILD层50。
如图15A和图15B去除牺牲栅电极40和牺牲栅极介电层45，从而暴露鳍结构。图15A是对应于图6D中的线Y1-Y1的截面图，以及图15B是对应于图6D的线X2-X2的截面图。
在去除牺牲栅极结构期间，ILD层50保护第一S/D结构210和第二S/D结构215。可以使用等离子体干蚀刻和/或湿蚀刻去除牺牲栅极结构。当牺牲栅电极40是多晶硅且ILD层50是氧化硅时，诸如TMAH溶液的湿蚀刻剂可以用于选择性地去除牺牲栅电极40。其后，使用等离子体干蚀刻和/或湿蚀刻去除牺牲栅极介电层45。通过去除牺牲栅极结构，暴露第一半导体层30和第二半导体层35的侧面。
如图16A所示，去除位于暴露的鳍结构中的第一半导体层30之间的第二半导体层35以形成间隔150，从而形成引线状或条状沟道区域110。图16A是对应于图6D中的线Y1-Y1的截面图，以及图16B是对应于图6D的线X2-X2的截面图。
可以使用蚀刻剂去除第二半导体层35，该蚀刻剂可以选择性地蚀刻牺牲半导体层35而不蚀刻第一半导体层30。
当第一半导体层30是Ge或基于Ge的化合物且牺牲半导体层35是Si或SiGe时，可以使用诸如但不限制于氢氧化铵(NH4OH)、氢氧化四甲铵(TMAH)、乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液的湿蚀刻剂选择性地去除牺牲半导体层35。
当第一半导体层30是Si或基于Si的化合物且牺牲半导体层35是Ge或SiGe时，可以使用诸如但不限制于羧酸/硝酸/HF水溶液和柠檬酸/硝酸/HF水溶液的湿蚀刻剂选择性地去除牺牲半导体层35。
通过去除第二半导体层35，在第一半导体层30(沟道区域110)之间形成间隔或空隙150。第一半导体层30之间的间隔或空隙150的厚度在大约5nm至约30nm的范围内。
剩余的第一半导体层30形成沟道区域110的垂直阵列，垂直阵列的每个连接至p沟道区域中的第一S/D层210和n沟道区域中的第二S/D层215的对应的一个。应该注意，用于沟道区域110的材料具有的晶格常数不同于用于第一S/D层210和215的材料的晶格常数。在一些实施例中，沟道区域110的厚度在从约5nm至约50nm的范围内，并且在其他实施例中，该厚度在从约5nm至约30nm的范围内。
如图17A所示，在形成间隔150之后，在每个沟道区域110周围形成栅极介电层120，且在栅极介电层120上形成栅电极层130。图17A是对应于图6D中的线Y1-Y1的截面图，以及图17B是对应于图6D的线X2-X2的截面图。
在特定的实施例中，栅极介电层120包括一层或多层介电材料，诸如氧化硅、氮化硅或高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。
可以通过CVD、ALD或任何其他合适的方法形成栅极介电层120。在一个实施例中，使用诸如ALD的高共形沉积工艺形成栅极介电层120从而确保形成在每个沟道区域110周围均具有均匀厚度的栅极介电层。在一个实施例中，栅极介电层120的厚度在从大约1nm至大约6nm的范围内。还在ILD层50的表面上方形成栅极介电层120(未示出)。
在栅极介电层120上形成栅电极层130以围绕每个沟道区域110。
栅电极130包括导电材料(诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或它们的组合)的一层或多层。
栅电极层130可以通过CVD、ALD、电镀或其他合适的方法来形成。还在ILD层50的上表面上方沉积栅电极层。如图17A所示，然后使用例如CMP平坦化在ILD层50上方形成的栅极介电层和栅电极层，直到暴露ILD层50的顶面。
在本发明的特定实施例中，一个或多个功函调整层(未示出)插入在栅极介电层120与栅电极130之间。功函调整层由导电材料制成，诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或者这些材料的两种或多种的多层。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调整层，而对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。功函调整层可以通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺来形成。另外，可以使用不同的金属层分别地形成用于n沟道FET和p沟道FET的功函调整层。
通过形成栅电极层130，由栅电极层130的材料完全地填充间隔150。在一些实施例中，不完全地填充间隔150，从而形成空隙或狭缝。
在以上实施例中，在垂直方向上的用于一个FET的沟道区域110(30)的数量是二。然而，沟道区域的数量可以是三或更多。在这样的情况下，在垂直方向上还增加第二半导体层35的数量。
在以上的实施例中，首先形成p沟道FET的S/D结构，并且然后形成用于n沟道FET的那些S/D结构。在其它实施例中，首先形成用于n沟道FET的S/D结构，并且然后形成用于p沟道FET的那些S/D结构。
参照图17A和图17B，在衬底10上方设置GAA FET器件。p沟道GAA FET包括栅极结构(120和130)、沟道区域110和源极/漏极区域210，以及n沟道GAA FET包括栅极结构(120和130)、沟道区域110和源极/漏极区域215。
在源极区域和漏极区域之间设置在X方向上延伸的沟道区域110。在Y方向上延伸的栅极结构包括栅极介电层120和栅电极层130。在每个沟道区域110上以及环绕每个沟道区域110的侧面(除了在沟道区域100的在X方向上的端处)形成栅极介电层120，其中，沟道区域110连接至源极和漏极区域210或215。栅电极层130形成在栅极介电层120上并且完全地围绕每个沟道区域110。栅极结构还包括在栅极介电层120上设置的侧壁间隔件层140。在栅极结构下方，离散地设置由栅极介电层120和栅电极层130围绕的沟道区域110。
p沟道FET的源极/漏极(S/D)区域包括在Z方向上交替堆叠的第一S/D层210和第二S/D层35(由第二半导体层制成)。第一S/D层210分别连接至沟道区域110，且第二S/D层35的侧面(在X方向上的横向端)与栅极介电层接触且不与沟道区域110接触。
如图17A所示，每个沟道区域110在垂直方向上(Z方向)的位置与每个第一S/D层210的位置基本上相同。在垂直方向上邻近的沟道区域110之间的由栅电极层130和栅极介电层120填充的间隔位于与第二S/D层35基本上相同的高度处。
在一些实施例中，沟道区域110包括掺杂的或未掺杂的Si或基于Si的化合物，并且第一S/D层210包括具有或没有诸如硼(B)的额外的掺杂剂的Ge或Si1-xGex，其中，Si的含量小于在沟道区域110中Si的含量。当不掺杂沟道区域110时，可以最小化电荷载流子的散射且可以增加沟道区域110中载流子迁移率。在一个实施例中，沟道区域110是由Si制成的。第二S/D层35还可以包括Si1-xGex，其中，Ge的数量小于第一S/D层210的数量。在一个实施例中，第一S/D层210包括Si1-xGex(其中，x在从约0.3至约0.8的范围内)，和第二S/D层35包括Si1-yGey(其中，y在从约0.1至约0.4的范围内),且y<x。
在其它实施例中，沟道区域110包括掺杂的或未掺杂的锗(Ge)或基于Ge的化合物，并且第一S/D层210包括具有或没有诸如硼(B)的额外的掺杂剂的Si或Si1-xGex，其中，Ge的含量小于在沟道区域110中Ge的含量。
应当理解，GAA FET经历另外的CMOS工艺以形成诸如接触件/通孔、互连金属层、介电层、钝化层等的各种部件。
本文描述的各个实施例或实例提供若干优于现有技术的优点。例如，在本发明中，通过在源极/漏极区域中使用堆叠的结构，与源极/漏极区域是由Si1-xGex的单层制成的情况相比，使连接至沟道区域的源极和漏极中的Ge含量更高是有可能的。此外，意识到在一个层中的Ge的含量更均匀，这可以给沟道区域提供更高的应力，并且因此改善了器件性能。
应该理解，本文不必讨论所有优点，没有特定优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同优点。
根据本发明的一个方面，一种半导体器件包括：在衬底上方设置的第一沟道区域；第一源极区域和第一漏极区域，设置在衬底上方且连接至第一沟道区域的从而使得第一沟道区域设置在第一源极区域和第一漏极区域之间；设置在第一沟道区域上且围绕第一沟道区域的栅极介电层；设置在栅极介电层上且围绕第一沟道区域的栅电极层；以及第二源极区域和第二漏极区域，分别设置在衬底上方以及第一源极区域和第一漏极区域下方。第二源极区域和第二漏极区域与栅极介电层接触。第一源极区域和第一漏极区域的晶格常数不同于第二源极区域和第二漏极区域的晶格常数。
根据本发明的另一方面，一种半导体器件包括p沟道FET和n沟道FET。p沟道FET和n沟道FET的每个均包括在衬底上方设置的鳍结构、部分地覆盖鳍结构的栅极结构以及在鳍结构上方形成的未由栅极结构覆盖的源极和漏极(S/D)结构。p沟道FET和n沟道FET的每个的栅极结构均包括在衬底上方设置的第一沟道区域、设置在第一沟道区域上且围绕第一沟道区域的栅极介电层以及设置在栅极介电层上且围绕第一沟道区域的栅电极层。在p沟道FET中，S/D结构包括第一S/D层和具有与第一S/D的晶格常数不同的晶格常数的第二S/D层，第一S/D层连接至第一沟道区域，第一S/D层具有与第一沟道区域的晶格常数不同的晶格常数，以及第二S/D层的侧面与栅极介电层接触。
根据本发明的另一方面，一种用于制造半导体器件的方法包括以下操作。在衬底上方形成在垂直方向上被第二半导体层夹住的第一半导体层。将第一半导体层和第二半导体层图案化为鳍结构从而使得鳍结构包括由第二半导体层制成的牺牲层和由第一半导体层制成的沟道区域。在鳍结构上方形成牺牲栅极结构从而使得牺牲栅极结构覆盖鳍结构的部分而仍然暴露鳍结构的剩余部分。去除鳍结构的未由牺牲栅极结构覆盖的剩余部分。形成源极/漏极区域。去除牺牲栅极结构。在去除牺牲栅极结构之后去除鳍结构中的牺牲层从而暴露沟道区域。在暴露的沟道区域周围形成栅极介电层和栅电极层。形成源极/漏极(S/D)区域包括以下操作：去除第一半导体层从而暴露第二半导体层的至少一个；以及在暴露的第二半导体层上和周围形成第一S/D层。第一S/D层连接至沟道区域，第二半导体层的在S/D区域中的侧面与栅极介电层接触，且第一S/D层的晶格常数不同于第二半导体层的晶格常数和不同于沟道区域的晶格常数。
根据本发明的一个实施例，提供了一种半导体器件，包括：第一沟道区域，设置在衬底上方；第一源极区域和第一漏极区域，设置在所述衬底上方且连接至所述第一沟道区域使得所述第一沟道区域设置在所述第一源极区域和所述第一漏极区域之间；栅极介电层，设置在所述第一沟道区域上且围绕所述第一沟道区域；栅电极层，设置在所述栅极介电层上且围绕所述第一沟道区域；以及第二源极区域和第二漏极区域，分别设置在所述衬底上方且设置在所述第一源极区域和所述第一漏极区域下方，其中：所述第二源极区域和所述第二漏极区域与所述栅极介电层接触，以及所述第一源极区域和所述第一漏极区域的晶格常数不同于所述第二源极区域和所述第二漏极区域的晶格常数。
在上述半导体器件中，在垂直于所述衬底的表面的垂直方向上在所述第一沟道区域和所述衬底之间且在平行于所述衬底的所述表面的水平方向上在所述第二源极区域和所述第二漏极区域之间提供间隔，以及利用所述栅极介电层和所述栅电极层填充所述间隔。
在上述半导体器件中，其中：所述第一沟道区域由Si或基于Si的化合物制成，以及所述第一源极区域和所述第一漏极区域由Ge或SiGe制成。
在上述半导体器件中，所述第二源极区域和所述第二漏极区域由SiGe制成，以及所述第二源极区域和所述第二漏极区域的Ge含量小于所述第一源极区域和所述第一漏极区域的Ge含量。
在上述半导体器件中，还包括：第二沟道区域，设置所述第一沟道区域上方，具有由所述栅极介电层和所述栅电极层填充的间隔，所述第二沟道区域由所述栅极介电层和所述栅电极层围绕；设置在所述第一源极区域上方的第三源极区域以及设置在所述第一漏极区域上方的第三漏极区域；第四源极区域，设置在所述第三源极区域上方且连接至所述第二沟道区域；以及第四漏极区域，设置在所述第三源极区域上方且连接至所述第二沟道区域使得所述第二沟道区域设置在所述第四源极区域和所述第四漏极区域之间，其中，所述第三源极区域和所述第三漏极区域的晶格常数不同于所述第四源极区域和所述第四漏极区域的晶格常数。
在上述半导体器件中，所述第一沟道区域和所述第二沟道区域由Si或基于Si的化合物制成，以及所述第一源极区域和所述第四源极区域以及所述第一漏极区域和所述第四漏极区域由Ge或SiGe制成。
在上述半导体器件中，所述第二源极区域和所述第三源极区域以及所述第二漏极区域和所述第三漏极区域由SiGe制成，以及所述第二源极区域和所述第三源极区域以及所述第二漏极区域和所述第三漏极区域的Ge含量小于所述第一源极区域和所述第四源极区域以及所述第一漏极区域和所述第四漏极区域的Ge含量。
根据本发明的另一实施例，还提供了一种半导体器件，包括p沟道场效应晶体管和n沟道场效应晶体管，其中：所述p沟道场效应晶体管和所述n沟道场效应晶体管的每个均包括：设置在衬底上方的鳍结构；部分地覆盖所述鳍结构的栅极结构；以及形成在所述鳍结构上方的未被所述栅极结构覆盖的源极和漏极结构，所述p沟道场效应晶体管和所述n沟道场效应晶体管的每个的所述栅极结构均包括：设置在所述衬底上方的第一沟道区域；设置在所述第一沟道区域上且围绕所述第一沟道区域的栅极介电层；以及设置在所述栅极介电层上且围绕所述第一沟道区域的栅电极层，以及在所述p沟道场效应晶体管中：所述源极和漏极结构包括第一源极和漏极层和具有与所述第一源极和漏极层的晶格常数不同的晶格常数的第二源极和漏极层，所述第一源极和漏极层连接至所述第一沟道区域，所述第一源极和漏极层具有与所述第一沟道区域的晶格常数不同的晶格常数，以及所述第二源极和漏极层的侧面与所述栅极介电层接触。
在上述半导体器件中，所述第一沟道区域由Si或基于Si的化合物制成，以及所述第一源极和漏极层由Ge或SiGe制成。
在上述半导体器件中，所述第二源极和漏极层由SiGe制成，以及所述第一源极和漏极层的Ge含量大于所述第二源极和漏极层的Ge含量。
在上述半导体器件中，在垂直方向上提供多个所述第一沟道区域和对应的多个所述第一源极和漏极层。
在上述半导体器件中，在所述n沟道场效应晶体管中：所述源极和漏极层结构包括第三源极和漏极层，所述第三源极和漏极层连接至所述第一沟道区域，所述第三源极和漏极层具有与所述第一沟道区域的晶格常数不同的晶格常数，以及所述第三源极和漏极层的侧面与所述栅极介电层接触。
在上述半导体器件中，在所述n沟道场效应晶体管中，所述源极和漏极结构不包括层状结构。
根据本发明的又一实施例，还提供了一种用于制造半导体器件的方法，包括：在衬底上方在垂直方向上形成被第二半导体层夹住的第一半导体层；将所述第一半导体层和所述第二半导体层图案化为鳍结构使得所述鳍结构包括由所述第二半导体层制成的牺牲层和由所述第一半导体层制成的沟道区域；在所述鳍结构上方形成牺牲栅极结构使得所述牺牲栅极结构覆盖所述鳍结构的部分而所述鳍结构的剩余部分仍然暴露；去除所述鳍结构的未由所述牺牲栅极结构覆盖的所述剩余部分；形成源极/漏极区域；去除所述牺牲栅极结构；在去除所述牺牲栅极结构之后去除所述鳍结构中的所述牺牲层以暴露所述沟道区域；在暴露的所述沟道区域周围形成栅极介电层和栅电极层，其中：形成所述源极/漏极区域包括：去除所述第一半导体层从而使得暴露所述第二半导体层的至少一个；以及在暴露的所述第二半导体层上和周围形成第一源极/漏极层，所述第一源极/漏极层连接至所述沟道区域，所述第二半导体层的在所述源极/漏极区域中的侧面与所述栅极介电层接触，以及所述第一源极/漏极层的晶格常数不同于所述第二半导体层的晶格常数，且所述第一源极/漏极层的晶格常数不同于所述沟道区域的晶格常数。
在上述方法中，通过湿蚀刻分别去除位于所述鳍结构中的所述牺牲层和在形成所述源极/漏极区域中的所述第一半导体层。
在上述方法中，在所述衬底上方交替地形成多个所述第一半导体层和多个所述第二半导体层，
在所述鳍结构中，交替地堆叠多个所述牺牲层和多个所述沟道区域。
在上述方法中，所述沟道区域由Si或基于Si的化合物制成，以及所述第一源极/漏极层由Ge或SiGe制成。
在上述方法中，根据权利要求17所述的方法，其中：所述第二半导体层由SiGe制成，以及所述第一源极/漏极层的Ge含量大于所述第二半导体层的Ge含量。
在上述方法中，在通过图案化所述第一半导体层和所述第二半导体层形成所述鳍结构中，形成多个所述鳍结构以布置在平行于所述衬底的表面的水平方向上，以及
在形成所述牺牲栅极结构中，所述牺牲栅极结构覆盖多个所述鳍结构的每个的部分。
在上述方法中，在形成所述源极/漏极区域中，形成多个所述源极/漏极区域，多个所述源极/漏极区域的每个均包括所述第一源极/漏极层和所述第二半导体层。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种半导体器件，包括：
第一沟道区域，设置在衬底上方；
第一源极区域和第一漏极区域，设置在所述衬底上方且连接至所述第一沟道区域使得所述第一沟道区域设置在所述第一源极区域和所述第一漏极区域之间；
栅极介电层，设置在所述第一沟道区域上且围绕所述第一沟道区域；
栅电极层，设置在所述栅极介电层上且围绕所述第一沟道区域；以及
第二源极区域和第二漏极区域，分别设置在所述衬底上方且设置在所述第一源极区域和所述第一漏极区域下方，其中：
所述第二源极区域和所述第二漏极区域与所述栅极介电层接触，以及
所述第一源极区域和所述第一漏极区域的晶格常数不同于所述第二源极区域和所述第二漏极区域的晶格常数。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112701161A (zh) * 2019-10-23 2021-04-23 台湾积体电路制造股份有限公司 存储器器件及其形成方法
CN113497155A (zh) * 2020-06-23 2021-10-12 台湾积体电路制造股份有限公司 晶体管及其形成方法

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9941118B2 (en) * 2016-08-22 2018-04-10 International Business Machines Corporation Dense vertical nanosheet
FR3060838B1 (fr) * 2016-12-15 2019-05-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un dispositif semi-conducteur a canal contraint en compression
EP3340308B1 (en) * 2016-12-22 2022-09-07 IMEC vzw Method for forming transistors on a substrate
CN107726682A (zh) * 2017-10-12 2018-02-23 青岛海尔空调电子有限公司 热泵机组防冷冻控制方法
US10720494B2 (en) * 2018-01-22 2020-07-21 Globalfoundries Inc. Field-effect transistors with airgaps
CN108317687A (zh) * 2018-02-05 2018-07-24 珠海格力电器股份有限公司 防冻节能控制方法、装置和空调机组
DE102019115523B4 (de) * 2018-07-31 2022-05-25 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zur herstellung einer halbleitervorrichtung
CN110873479A (zh) * 2018-08-29 2020-03-10 江苏美力格环境科技有限公司 一种改进型家用多功能空气源热泵系统
US11387362B2 (en) * 2018-11-30 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
DE102019115490B4 (de) 2018-11-30 2022-10-20 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleiter-bauelement und verfahren zu dessen herstellung
CN110131933B (zh) * 2019-04-15 2021-04-20 广东芬尼能源技术有限公司 一种适用于热泵机组的待机防冻控制方法及装置
CN109990519B (zh) * 2019-04-17 2020-12-22 南京天加环境科技有限公司 一种空气源热泵防冻控制方法
US11888034B2 (en) 2019-06-07 2024-01-30 Intel Corporation Transistors with metal chalcogenide channel materials
US11171243B2 (en) * 2019-06-27 2021-11-09 Intel Corporation Transistor structures with a metal oxide contact buffer
US11777029B2 (en) 2019-06-27 2023-10-03 Intel Corporation Vertical transistors for ultra-dense logic and memory applications
CN110425747B (zh) * 2019-08-01 2021-04-09 广东志高暖通设备股份有限公司 一种适用于变频热泵热水器的变频水泵控制方法
CN110553345A (zh) * 2019-09-12 2019-12-10 珠海格力电器股份有限公司 机组自动防冻的方法及空调系统
CN111207485B (zh) * 2020-01-09 2021-07-13 珠海格力电器股份有限公司 一种防冻结控制方法、装置、存储介质及水多联系统
US11653492B2 (en) * 2020-02-10 2023-05-16 Taiwan Semiconductor Manufacturing Limited Memory devices and methods of manufacturing thereof
KR102576497B1 (ko) * 2020-05-29 2023-09-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 가변 수의 채널 층을 가진 반도체 디바이스 및 그 제조 방법
CN112902400A (zh) * 2020-12-30 2021-06-04 珠海拓芯科技有限公司 空调水系统防冻控制方法、装置及空调器
CN112728978A (zh) * 2020-12-31 2021-04-30 浙江中广电器股份有限公司 一种具有板式换热器的空调系统及其防冻控制方法
US20230031490A1 (en) * 2021-07-30 2023-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Strained nanosheets on silicon-on-insulator substrate
CN115247891A (zh) * 2022-06-28 2022-10-28 浙江中广电器集团股份有限公司 一种热泵热水机防冻的控制方法
CN115183405A (zh) * 2022-07-08 2022-10-14 青岛海尔空调电子有限公司 用于空气源热泵机组防冻的方法及装置、空气源热泵机组、存储介质

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2831838B2 (ja) * 1990-11-06 1998-12-02 株式会社東芝 空気調和機
CN2400764Y (zh) * 1999-12-30 2000-10-11 张晓军 空调防冻装置
JP4186492B2 (ja) * 2002-03-29 2008-11-26 ダイキン工業株式会社 空気調和装置
JP4796329B2 (ja) * 2004-05-25 2011-10-19 三星電子株式会社 マルチ−ブリッジチャンネル型ｍｏｓトランジスタの製造方法
CN1979063B (zh) * 2005-12-02 2010-05-12 深圳麦克维尔空调有限公司 一种空调防冻方法
JP2007258485A (ja) 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
EP1895545B1 (en) * 2006-08-31 2014-04-23 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
JP5646300B2 (ja) * 2010-11-29 2014-12-24 三洋電機株式会社 冷凍装置
US8796788B2 (en) * 2011-01-19 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with strained source/drain structures
CN104126228B (zh) 2011-12-23 2016-12-07 英特尔公司 非平面栅极全包围器件及其制造方法
US9012284B2 (en) * 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
CN202947359U (zh) * 2012-11-16 2013-05-22 泰豪科技股份有限公司 全热回收水冷螺杆式冷水机组
US20140151638A1 (en) 2012-12-03 2014-06-05 International Business Machines Corporation Hybrid nanomesh structures
KR20140106270A (ko) * 2013-02-26 2014-09-03 삼성전자주식회사 집적 회로 장치 및 그 제조 방법
US8969149B2 (en) * 2013-05-14 2015-03-03 International Business Machines Corporation Stacked semiconductor nanowires with tunnel spacers
KR102089682B1 (ko) 2013-07-15 2020-03-16 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
CN104422076B (zh) * 2013-08-21 2017-06-20 珠海格力电器股份有限公司 空调器制冷机组及其防冻控制方法
KR102083494B1 (ko) * 2013-10-02 2020-03-02 삼성전자 주식회사 나노와이어 트랜지스터를 포함하는 반도체 소자
US9224833B2 (en) * 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company Limited Method of forming a vertical device
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
CN104534622B (zh) * 2014-12-19 2017-06-06 珠海格力电器股份有限公司 空调防冻控制方法和装置
CN104676993B (zh) * 2015-02-13 2017-11-14 广东芬尼克兹节能设备有限公司 一种待机防冻控制方法
CN104776658A (zh) * 2015-04-09 2015-07-15 珠海格力电器股份有限公司 冷热水机组防冻控制方法、防冻控制装置及冷热水机组
US9437502B1 (en) * 2015-06-12 2016-09-06 International Business Machines Corporation Method to form stacked germanium nanowires and stacked III-V nanowires
US9613871B2 (en) * 2015-07-16 2017-04-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US9773708B1 (en) * 2016-08-24 2017-09-26 Globalfoundries Inc. Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI
US9960254B1 (en) * 2017-02-06 2018-05-01 International Business Machines Corporation Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
US10373912B2 (en) * 2018-01-05 2019-08-06 International Business Machines Corporation Replacement metal gate processes for vertical transport field-effect transistor
US10629499B2 (en) * 2018-06-13 2020-04-21 International Business Machines Corporation Method and structure for forming a vertical field-effect transistor using a replacement metal gate process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112701161A (zh) * 2019-10-23 2021-04-23 台湾积体电路制造股份有限公司 存储器器件及其形成方法
CN112701161B (zh) * 2019-10-23 2024-04-09 台湾积体电路制造股份有限公司 存储器器件及其形成方法
CN113497155A (zh) * 2020-06-23 2021-10-12 台湾积体电路制造股份有限公司 晶体管及其形成方法

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