CN108122772A - 制造半导体器件的方法和半导体器件 - Google Patents
制造半导体器件的方法和半导体器件 Download PDFInfo
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- CN108122772A CN108122772A CN201710906158.9A CN201710906158A CN108122772A CN 108122772 A CN108122772 A CN 108122772A CN 201710906158 A CN201710906158 A CN 201710906158A CN 108122772 A CN108122772 A CN 108122772A
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- 238000000034 method Methods 0.000 title claims abstract description 143
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title abstract description 56
- 238000009413 insulation Methods 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims description 53
- 230000005669 field effect Effects 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 5
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 4
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 409
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 41
- 238000005530 etching Methods 0.000 description 22
- 239000000377 silicon dioxide Substances 0.000 description 21
- 238000005229 chemical vapour deposition Methods 0.000 description 20
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 238000000231 atomic layer deposition Methods 0.000 description 15
- 239000007789 gas Substances 0.000 description 15
- 238000005240 physical vapour deposition Methods 0.000 description 15
- 229910052681 coesite Inorganic materials 0.000 description 13
- 229910052906 cristobalite Inorganic materials 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
- 229910052682 stishovite Inorganic materials 0.000 description 13
- 229910052905 tridymite Inorganic materials 0.000 description 13
- 229910021332 silicide Inorganic materials 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 10
- 229910052799 carbon Inorganic materials 0.000 description 9
- 239000004020 conductor Substances 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- -1 SiCN Inorganic materials 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000000717 retained effect Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 229910052726 zirconium Inorganic materials 0.000 description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 229910010038 TiAl Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910005898 GeSn Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910001868 water Inorganic materials 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910004191 HfTi Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910010041 TiAlC Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003245 coal Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910020630 Co Ni Inorganic materials 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 229910002440 Co–Ni Inorganic materials 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical compound ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910017947 MgOx Inorganic materials 0.000 description 1
- 229910015617 MoNx Inorganic materials 0.000 description 1
- 229910017912 NH2OH Inorganic materials 0.000 description 1
- 229910005889 NiSix Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910020175 SiOH Inorganic materials 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910004349 Ti-Al Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910010421 TiNx Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 229910004692 Ti—Al Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 210000005056 cell body Anatomy 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004441 surface measurement Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/28—Surgical forceps
- A61B17/285—Surgical forceps combined with cutting implements
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/28—Surgical forceps
- A61B17/29—Forceps for use in minimally invasive surgery
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/28—Surgical forceps
- A61B17/29—Forceps for use in minimally invasive surgery
- A61B17/295—Forceps for use in minimally invasive surgery combined with cutting implements
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B18/00—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body
- A61B18/04—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating
- A61B18/12—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating by passing a current through the tissue to be heated, e.g. high-frequency current
- A61B18/14—Probes or electrodes therefor
- A61B18/1442—Probes having pivoting end effectors, e.g. forceps
- A61B18/1445—Probes having pivoting end effectors, e.g. forceps at the distal end of a shaft, e.g. forceps or scissors at the end of a rigid rod
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
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- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/28—Surgical forceps
- A61B17/2812—Surgical forceps with a single pivotal connection
- A61B17/282—Jaws
- A61B2017/2825—Inserts of different material in jaws
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/28—Surgical forceps
- A61B17/29—Forceps for use in minimally invasive surgery
- A61B2017/2926—Details of heads or jaws
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B18/00—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body
- A61B2018/00571—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body for achieving a particular surgical effect
- A61B2018/00589—Coagulation
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B18/00—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body
- A61B2018/00571—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body for achieving a particular surgical effect
- A61B2018/0063—Sealing
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B18/00—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body
- A61B18/04—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating
- A61B18/12—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating by passing a current through the tissue to be heated, e.g. high-frequency current
- A61B18/14—Probes or electrodes therefor
- A61B18/1442—Probes having pivoting end effectors, e.g. forceps
- A61B2018/1452—Probes having pivoting end effectors, e.g. forceps including means for cutting
- A61B2018/1455—Probes having pivoting end effectors, e.g. forceps including means for cutting having a moving blade for cutting tissue grasped by the jaws
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B18/00—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body
- A61B18/04—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating
- A61B18/12—Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by heating by passing a current through the tissue to be heated, e.g. high-frequency current
- A61B18/14—Probes or electrodes therefor
- A61B2018/1465—Deformable electrodes
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B90/00—Instruments, implements or accessories specially adapted for surgery or diagnosis and not covered by any of the groups A61B1/00 - A61B50/00, e.g. for luxation treatment or for protecting wound edges
- A61B90/03—Automatic limiting or abutting means, e.g. for safety
- A61B2090/033—Abutting means, stops, e.g. abutting on tissue or skin
- A61B2090/034—Abutting means, stops, e.g. abutting on tissue or skin abutting on parts of the device itself
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
在形成FinFET的方法中,在FinFET结构的源极/漏极结构和隔离绝缘层上方形成第一牺牲层。使第一牺牲层凹进,使得在隔离绝缘层上形成第一牺牲层的剩余层并且暴露源极/漏极结构的上部。在剩余层和暴露的源极/漏极结构上形成第二牺牲层。图案化第二牺牲层和剩余层,从而形成开口。在开口中形成介电层。在形成介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在源极/漏极结构上方形成接触开口。在接触开口中形成导电层。本发明实施例涉及制造半导体器件的方法和半导体器件。
Description
技术领域
本发明实施例涉及制造半导体集成电路的方法,并且更具体地,涉及制造包括鳍式场效应晶体管(FinFET)的半导体器件的方法和半导体器件。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点,来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展和具有高k(介电常数)材料的金属栅极结构的使用。通常通过使用栅极置换技术制造金属栅极结构,并且通过使用外延生长方法形成源极和漏极。
发明内容
根据本发明的一些实施例,提供了一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:在鳍式场效应晶体管结构的源极/漏极结构和隔离绝缘层上方形成第一牺牲层;使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述源极/漏极结构的上部暴露;在所述剩余层和暴露的源极/漏极结构上形成第二牺牲层;图案化所述第二牺牲层和所述剩余层,从而形成开口;在所述开口中形成介电层;在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述源极/漏极结构上方形成接触开口;以及在所述接触开口中形成导电层。
根据本发明的另一些实施例,还提供了一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:在第一鳍式场效应晶体管结构的第一源极/漏极结构、第二鳍式场效应晶体管结构的第二源极/漏极结构和隔离绝缘层上方形成第一牺牲层,所述第一源极/漏极结构设置为邻近所述第二源极/漏极结构;使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述第一源极/漏极结构和所述第二源极/漏极结构的上部暴露;在所述剩余层以及暴露的第一源极/漏极结构和暴露的第二源极/漏极结构上形成第二牺牲层;图案化所述第二牺牲层和所述剩余层,从而在所述第一源极/漏极结构和所述第二源极/漏极结构之间形成开口;在所述开口中形成介电层;在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述第一源极/漏极结构上方形成第一接触开口并且在所述第二源极/漏极结构上方形成第二接触开口;以及在所述第一接触开口中形成第一导电层并且在所述第二接触开口中形成第二导电层。
根据本发明的又一些实施例,还提供了一种包括鳍式场效应晶体管(FinFET)的半导体器件,包括:第一鳍式场效应晶体管,包括在第一方向上延伸的第一鳍结构、第一源极/漏极结构以及与所述第一源极/漏极结构接触的第一源极/漏极接触件;第二鳍式场效应晶体管,设置为邻近所述第一鳍式场效应晶体管并且包括在所述第一方向上延伸的第二鳍结构、第二源极/漏极结构以及与所述第二源极/漏极结构接触的第二源极/漏极接触件;以及介电层,将所述第一源极/漏极结构和所述第二源极/漏极结构分隔开,其中,所述介电层由硅基绝缘材料制成,并且在所述介电层与所述第一源极/漏极接触件和所述第二源极/漏极接触件中的一个之间的界面处或附近包含Ge。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A至图1C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图2A至图2C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图3A至图3C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图4A至图4C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图5A至图5C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图6A至图6C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图7A至图7C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图8A至图8C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图9A至图9C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图10A至图10C示出了根据本发明的实施例的半导体器件制造工艺中的各个阶段的一个。
图11A至图11C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图12A至图12C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图13A至图13C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图14A至图14C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图15A至图15C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图16A至图16C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图17A至图17C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图18A至图18C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图19A至图19C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图20A至图20C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图21A至图21C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个阶段的一个。
图22A和图22B示出了根据本发明的一些实施例的半导体器件的视图。
图23A和图23B示出了根据本发明的一些实施例的半导体器件的视图。
图24A至图24C示出了根据本发明的一些实施例的半导体器件的视图。
图25A至图25C示出了根据本发明的一些实施例的半导体器件的视图。
具体实施方式
应该理解,以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,元件的尺寸不限于公开的范围或值,但是可能依赖于工艺条件和/或器件所需的性能。此外,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清晰的目的,各个部件可以以不同比例任意地绘制。在随后的附图中,为了简化,可以省略一些层/部件。
此外,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。此外,术语“由…制成”可能意味着“包括”或“由…组成”。此外,在随后的制造工艺中,在描述的操作中/之间可以存在一个或多个额外的操作,并且操作的顺序可以改变。
公开的实施例涉及形成用于鳍式场效应晶体管(FinFET)的源极/漏极(S/D)结构的方法、图案化用于S/D结构上方的接触件的开口的方法。诸如本文公开的那些实施例通常不仅适用于FinFET,而且也适用于双栅极晶体管、环绕栅极晶体管、欧米茄-栅极晶体管或全环栅晶体管、二维FET和/或纳米线晶体管或使用源极/漏极外延生长工艺的任何合适的器件。
图1A至图10C示出了根据本发明的一些实施例的半导体器件制造工艺中的各个工艺。贯穿各个视图和示例性实施例,相同的参考标号用于指定相同的元件。在图1A至图9C中,“A”图(例如,图1A、图2A等)示出了立体图,“B”图(例如,图1B、图2B等)示出了沿着对应于图1A中示出的线Y1-Y1的Y方向的截面图,并且“C”图(例如,图1C、图2C等)示出了沿着对应于图1A中示出的线X1-X1的X方向的截面图。应该理解,可以在图1A至图10C所示的工艺之前、期间和之后提供额外的操作,并且对于方法的额外实施例,可以替换或消除以下描述的一些操作。操作/工艺的顺序可以互换。
首先参照图1A至图1C,图1A至图1C示出了实施形成FinFET结构的各个制造操作之后的结构。如图1A至图1C所示,源极/漏极(S/D)结构120和121以及金属栅极130与栅极介电层131一起形成在衬底101上方。在一些实施例中,S/D结构120用于p沟道FET并且S/D结构121用于n沟道FET(即,不同的导电类型)。在其他实施例中,S/D结构120、121均用于p沟道FET或用于n沟道FET(即,相同的导电类型)。可以通过以下制造操作形成这种结构。
在图1A至图1C中,示出了具有一个或多个鳍结构的衬底101,其中,示出了两个鳍结构102。应该理解,为了说明的目的,示出了两个鳍结构,但是其他实施例可以包括任何数量的鳍结构。在一些实施例中,一个或多个伪鳍结构形成为邻近于用于有源FinFET的鳍结构。鳍结构102在X方向上延伸并且从衬底在Z方向上突出,而栅极130在Y方向上延伸。
衬底101可以包括依赖于设计需求(例如,p型衬底或n型衬底)的各个掺杂区域。在一些实施例中,掺杂区域可以掺杂有p型或n型掺杂剂。例如,掺杂区域可以掺杂有诸如硼或BF2的p型掺杂剂;诸如磷或砷的n型掺杂剂;和/或它们的组合。掺杂区域可以配置为用于n型FinFET或可以可选地配置为用于p型FinFET。
在一些实施例中,衬底101可以由合适的元素半导体,诸如硅、金刚石或锗;合适的合金或化合物半导体,诸如IV族化合物半导体(硅锗(SiGe)、碳化硅(SiC)、碳化硅锗(SiGeC)、GeSn、SiSn、SiGeSn)、III-V族化合物半导体(例如,砷化镓、砷化镓铟(GaInAs)、砷化铟、磷化铟、锑化铟、磷砷化镓或磷化镓铟)等制成。此外,衬底101可以包括外延层(epi层),该外延层可以是应变的以用于性能增强,和/或该衬底101可以包括绝缘体上硅(SOI)结构。
可以使用例如图案化工艺形成沟槽来形成鳍结构102,从而使得在邻近的鳍结构102之间形成沟槽。如下面更细的讨论,鳍结构102将用于形成FinFET。
诸如浅沟槽隔离(STI)105的隔离区域设置在衬底101上方的沟槽中。在一些实施例中,在形成隔离绝缘层105之前,在衬底101上方和在鳍结构102的底部103的侧壁上方形成一个或多个衬垫层。在一些实施例中,衬垫层包括在衬底101上和鳍结构102的底部103的侧壁上形成的第一鳍衬垫层106,以及在第一鳍衬垫层106上形成的第二鳍衬垫层108。在一些实施例中,衬垫层的每个均具有介于约1nm和约20nm之间的厚度。
在一些实施例中,第一鳍衬垫层106包括氧化硅并且具有介于约0.5nm和约5nm之间的厚度,并且第二鳍衬垫层108包括氮化硅并且具有介于约0.5nm和约5nm之间的厚度。可以通过诸如物理汽相沉积(PVD)、化学汽相沉积(CVD)或原子层沉积(ALD)的一种或多种工艺来沉积衬垫层,但是可以利用任何可接受的工艺。
隔离绝缘层105可以由合适的介电材料制成,介电材料诸如氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、聚合物(诸如聚酰亚胺)、它们的组合等。在一些实施例中,通过诸如CVD、可流动CVD(FCVD)或旋涂玻璃工艺形成隔离绝缘层105,但是可以利用任何可接受的工艺。随后,使用例如蚀刻工艺、化学机械抛光(CMP)等去除在鳍结构102的顶面上方延伸的隔离绝缘层105的部分以及位于鳍结构102的顶面上方的衬垫层的部分。
在一些实施例中,如图1A至图1C所示,使隔离绝缘层105和衬垫层凹进以暴露鳍结构102的上部104。在一些实施例中,使用单个蚀刻工艺或多个蚀刻工艺使隔离绝缘层105和衬垫层凹进。在隔离绝缘层105由氧化硅制成的一些实施例中,蚀刻工艺可以是例如干蚀刻、化学蚀刻或湿清洗工艺。例如,化学蚀刻可以采用诸如稀释的氢氟(dHF)酸的含氟化学物。在一些实施例中,在鳍形成工艺之后,鳍高度H鳍为约30nm或更高,诸如约50nm或更高。在一个实施例中,鳍高度介于约40nm和约80nm之间。应该理解,鳍高度可以通过随后的处理修改。可以使用其他材料、工艺和尺寸。
在形成鳍结构102之后,在暴露的鳍结构102上方形成包括伪栅极介电层和伪栅电极的伪栅极结构。伪栅极介电层和伪栅电极将随后用于限定并且形成源极/漏极区域。在一些实施例中,通过沉积并且图案化在暴露的鳍结构102上方形成的伪介电层和位于伪介电层上方的伪电极层来形成伪栅极介电层和伪栅电极。可以通过热氧化、CVD、溅射或用于形成伪介电层的本领域中已知和使用的任何其他方法来形成伪介电层。在一些实施例中,伪介电层可以由一种或多种合适的介电材料制成,诸如氧化硅、氮化硅、SiCN、SiON和SiN、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、聚合物(诸如聚酰亚胺)等或它们的组合。在一个实施例中,使用SiO2。
随后,在伪介电层上方形成伪电极层。在一些实施例中,伪电极层是导电材料并且可以选自包括非晶硅、多晶硅、非晶锗、多晶锗、非晶硅-锗、多晶硅-锗、金属氮化物、金属硅化物、金属氧化物和金属的组。可以通过PVD、CVD、溅射沉积或用于沉积导电材料的本领域中已知和使用的其他技术来沉积伪电极层。可以使用导电和非导电的其他材料。在一个实施例中,使用多晶Si。
可以在伪电极层上方形成掩模图案以帮助图案化。该掩模图案可以由SiO2、SiCN、SiON、Al2O3、SiN或其他合适的材料的一层或多层制成。通过使用掩模图案作为蚀刻掩模,将伪电极层图案化成伪栅电极。在一些实施例中,也图案化伪介电层以限定伪栅极介电层。
随后,沿着伪栅极结构的侧壁形成侧壁间隔件134。可以通过沉积和各向异性蚀刻沉积在伪栅极结构、鳍结构102和隔离绝缘层105上方的绝缘层来形成侧壁间隔件134。在一些实施例中,侧壁间隔件134由氮化硅形成,并且可以具有单层结构。在可选实施例中,侧壁间隔件134可以具有包括多个层的复合结构。例如,侧壁间隔件134可以包括氧化硅层和位于氧化硅层上方的氮化硅层。也可以使用诸如SiO2、SiCN、SiON、SiN、SiOCN、其他低k材料或它们的组合的其他材料。在一些实施例中,侧壁间隔件134的厚度在从约5nm至约40nm的范围内。
在形成伪栅极结构和侧壁间隔件之后,沿着伪栅极结构的相对侧在鳍结构102的暴露部分104上形成源极/漏极(S/D)结构120和121。可以在暴露的鳍结构104的侧面和顶面上外延形成S/D结构120和121。在一些实施例中,可以使鳍结构104凹进并且在凹进的鳍的暴露的部分上外延形成S/D结构。源极/漏极区域中外延生长材料的使用允许源极/漏极区域对FinFET的沟道施加应力。当S/D结构120和121用于不同导电类型的FET时,在形成S/D结构120时,用于S/D结构121的鳍结构由例如SiN制成的保护层覆盖,并且之后形成S/D结构121,同时形成的S/D结构120由保护层覆盖。
对于n型FinFET和p型FinFET,用于S/D结构120和121的材料可以是变化的,从而使得一种类型的材料用于n型FinFET以对沟道区域施加拉伸应力,并且另一类型的材料用于p型FinFET以施加压缩应力。例如,SiP或SiC可以用于形成n型FinFET,并且SiGe或Ge可以用于形成p型FinFET。可以使用其他材料。在一些实施例中,S/D结构120和/或121包括具有不同组成和/或不同掺杂剂浓度的两个或多个外延层。
S/D结构120和/或121可以通过注入工艺以注入适当的掺杂剂或随着材料的生长原位掺杂来掺杂。例如,对于沟道可以是Si或Si1-xGex的p沟道FET,掺杂的外延膜可以是硼掺杂的Si1-yGey,其中,y等于或大于x以诱导沟道中的纵向压缩应变以用于空穴迁移率增强。对于沟道可以是Si的n沟道FET,掺杂的外延膜可以是例如磷掺杂的硅(Si:P)或磷掺杂的硅碳(Si1-zCz:P)。在沟道是诸如InmGa1-mAs的化合物半导体的情况下,掺杂的外延膜可以是例如InnGa1-nAs,其中,n小于或等于m。
如图1A和图1B所示,在一些实施例中,S/D结构120和/或121在Y方向上的截面具有基本六边形形状,并且在其他实施例中,S/D结构120和/或121的截面具有菱形形状、柱形形状或条形形状。在一些实施例中,S/D结构在Y方向上的宽度WSD在从约25nm至约100nm的范围内。
在形成S/D结构120和121之后,用作衬垫层或接触蚀刻停止层(CESL)的第一绝缘层122沉积为覆盖S/D结构120和121并且位于伪栅极结构的侧壁间隔件134上。第一绝缘层122用作随后形成的介电材料的图案化期间的蚀刻停止件。在一些实施例中,第一绝缘层122包括SiO2、SiCN、SiON、SiN和其他合适的介电材料。在一个实施例中,使用SiN。第一绝缘层122可以由包括上述材料的组合的多个层制成。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积第一绝缘层122,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。在一些实施例中,第一绝缘层122具有介于约0.5nm和约10nm之间的厚度。在其他实施例中,可以使用其他厚度。
在形成第一绝缘层122之后,在第一绝缘层122上方形成第一牺牲层115。在一些实施例中,第一牺牲层包括诸如SiO2、SiCN、SiON、SiOC、SiOH、SiN的硅基介电材料或其他合适的介电材料的一层或多层。在一些实施例中,通过诸如CVD、PVD、ALD、FCVD或旋涂玻璃工艺的膜形成工艺来形成第一牺牲层115,但是可以利用任何可接受的工艺。随后,使用例如蚀刻工艺、CMP等去除第一绝缘层122的部分以暴露伪栅电极的上表面。
随后,去除伪栅电极和伪栅极介电层。去除工艺可以包括一种或多种蚀刻工艺。例如,在一些实施例中,去除工艺包括使用干蚀刻或者湿蚀刻的选择性蚀刻。当使用干蚀刻时,工艺气体可以包括CF4、CHF3、NF3、SF6、Br2、HBr、Cl2或它们的组合。可以可选地使用诸如N2、O2或Ar的稀释气体。当使用湿蚀刻时,蚀刻溶液(蚀刻剂)可以包括NH4OH:H2O2:H2O(APM)、NH2OH、KOH、HNO3:NH4F:H2O等。可以使用诸如稀释的HF酸的湿蚀刻工艺去除伪栅极介电层。可以使用其他工艺和材料。
在去除伪栅极结构之后,在鳍结构104的沟道区域上方形成栅极介电层131。在一些实施例中,栅极介电层131包括一个或多个高k介电层(例如,具有大于3.9的介电常数)。例如,一个或多个栅极介电层可以包括Hf、Al、Zr的金属氧化物或Hf、Al、Zr的硅酸盐、它们的组合和它们的多层的一层或多层。其他合适的材料包括La、Mg、Ba、Ti、Pb、Zr的金属氧化物形式、金属合金氧化物形式和它们的组合形式。示例性材料包括MgOx、BaTixOy、BaSrxTiyOz、PbTixOy、PbZrxTiyOz、SiCN、SiON、SiN、Al2O3、La2O3、Ta2O3、Y2O3、HfO2、ZrO2、HfSiON、YGexOy、YSixOy和LaAlO3等。栅极介电层131的形成方法包括分子束沉积(MBD)、ALD、PVD等。在一些实施例中,栅极介电层131具有约0.5nm至约5nm的厚度。在一些实施例中,也在侧壁间隔件134的侧边上形成栅极介电层131。
在一些实施例中,在形成栅极介电层131之前,在沟道区域104上方形成界面层(未示出),并且在界面层上方形成栅极介电层131。界面层有助于缓冲随后形成的高k介电层与下面的半导体材料。在一些实施例中,界面层是可以通过化学反应形成的化学氧化硅。例如,可以使用去离子水+臭氧(DIO3)、NH4OH+H2O2+H2O(APM)或其他方法形成化学氧化硅。其他实施例利用用于界面层的不同材料或工艺。在实施例中,界面层具有约0.2nm至约1nm的厚度。
在形成栅极介电层131之后,在栅极介电层131上方形成栅电极130。栅电极130可以是选自W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr的组的金属。在一些实施例中,栅电极130包括选自TiN、WN、TaN和Ru的组的金属。可以使用诸如Ti-Al、Ru-Ta、Ru-Zr、Pt-Ti、Co-Ni和Ni-Ta的金属合金和/或可以使用诸如WNx、TiNx、MoNx、TaNx和TaSixNy的金属氮化物。在一些实施例中,栅电极130具有在约5nm至约10nm的范围内的厚度。可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的工艺形成栅电极130。可以实施诸如CMP的平坦化工艺以去除过量的材料。
在本发明的特定实施例中,栅电极130包括设置在栅极介电层131上的一个或多个功函调整层(未示出)。功函调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两种或多种的多层的导电材料制成。对于n沟道FinFET,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi的一种或多种用作功函调整层,并且对于p沟道FinFET,TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种用作功函调整层。
之后,使栅电极130、栅极介电层131和功函调整层凹进,并且在凹进的栅电极130上形成栅极覆盖层132。在一些实施例中,当栅电极130主要由W制成时,可以在24℃至150℃的温度范围以及在低于1托的压力下,使用例如使用Cl2/O2/BCl3的干蚀刻工艺使栅电极凹进。
在使栅电极130凹进之后,在凹槽中形成栅极覆盖层132以在随后的工艺期间保护栅电极130。在一些实施例中,栅极覆盖层132包括SiO2、SiCN、SiON、SiN、Al2O3、La2O3、SiN、它们的组合等,但是可以使用其他合适的介电膜。可以使用例如CVD、PVD、旋涂等形成栅极覆盖层132。可以使用其他合适的工艺步骤。可以实施诸如CMP的平坦化工艺以去除过量的材料。
图2A至图2C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
如图2A至图2C所示,从S/D结构120和121的两侧区域至少部分地去除第一牺牲层115,以形成开口116。在一些实施例中,去除全部的第一牺牲层115。可以通过诸如干蚀刻和/或湿蚀刻的合适的蚀刻操作去除第一牺牲层115。蚀刻操作基本停止在第一绝缘层122处。在一些实施例中,第一绝缘层122具有介于约0.5nm和约10nm之间的厚度。
图3A至图3C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在形成开口116之后,在开口116中形成第二牺牲层140。第二牺牲层140由相对于第一绝缘层122和/或隔离绝缘层105的材料具有更高(例如,5或更多)蚀刻选择性的材料制成。在一些实施例中,第二牺牲层140由可以是晶体、多晶或非晶并且可以是掺杂或非掺杂的诸如Si、SiGe、SiC、Ge、SiGeC和GeSn的IV族元素或化合物材料的一层或多层制成。在其他实施例中,第二牺牲层140由SiOC、SiC、SiON、SiCN、SiOCN、SiN和/或SiO2的一种或多种硅基介电层制成。可以使用诸如氧化铝、碳氧化铝和氮氧化铝的铝基介电材料。也可以使用SOC(旋涂碳)。在特定实施例中,第二牺牲层140由包括,但不限于,GaAs、GaN、InGaAs、InAs、InP、InSb、InAsSb、AlN和/或AlGaN的III-V族化合物半导体的一层或多层制成。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积第二牺牲层140,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。在一个实施例中,非晶或多晶Si用作第二牺牲层140。在其他实施例中,非晶或多晶Si1-xGex(其中,x等于或小于0.4)用作第二牺牲层140。
可以实施诸如回蚀刻工艺或CMP的平坦化操作以平坦化第二牺牲层140的上表面。通过平坦化操作,暴露栅极覆盖层132的上表面。在一些实施例中,在平坦化操作之后,从第一绝缘层122的表面测量的第二牺牲层的高度H牺牲在从约100nm至约350nm的范围内。
图4A至图4C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
通过使用湿蚀刻和/或干蚀刻使第二牺牲层140凹进,使得第二牺牲层的薄层141保留在第一绝缘层122(在隔离绝缘层105上形成)上。在一些实施例中,减薄的第二牺牲层141的厚度在从约1nm至约20nm的范围内。通过这种凹进操作,基本暴露覆盖S/D结构120和121的第一绝缘层122的部分。
图5A至图5C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在使第二牺牲层140凹进之后,形成第三牺牲层160。第三牺牲层160由相对于第一绝缘层122和/或隔离绝缘层105的材料具有更高(例如,5或更多)蚀刻选择性的材料制成。在一些实施例中,第三牺牲层160由与第一牺牲层和第二牺牲层的不同的材料制成。在一些实施例中,第三牺牲层160由可以是晶体、多晶或非晶并且可以是掺杂或非掺杂的诸如Si、SiGe、SiC、Ge、SiGeC和GeSn的IV族材料的一层或多层制成。在其他实施例中,第三牺牲层160由SiOC、SiC、SiON、SiCN、SiOCN、SiN和/或SiO2的一种或多种硅基介电层制成。可以使用诸如氧化铝、碳氧化铝和氮氧化铝的铝基介电材料。也可以使用SOC(旋涂碳)。在特定实施例中,第三牺牲层160由包括,但不限于,GaAs、GaN、InGaAs、InAs、InP、InSb、InAsSb、AlN和/或AlGaN的III-V族化合物半导体的一层或多层制成。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积第三牺牲层160,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。可以实施诸如回蚀刻工艺或CMP的平坦化操作以平坦化第三牺牲层160的上表面。通过平坦化操作,暴露栅极覆盖层132的上表面。在一个实施例中,非晶或多晶Ge用作第三牺牲层160。在其他实施例中,Si1-yGey(其中,y等于或大于0.6)用作第三牺牲层160。
在一个实施例中,非晶或多晶Ge用作第三牺牲层160。Ge/SiN蚀刻选择性比SiO2/SiN的蚀刻选择性大10倍以上。例如,Ge/SiN蚀刻选择性为约100(湿蚀刻),而SiO2/SiN蚀刻选择性为约3至4。因此,去除Ge第三牺牲层而不会引起对其他层的损坏是可能的。
当第二牺牲层140由Si制成时,Ge第三牺牲层160可以自减薄的第二牺牲层141选择性地形成在减薄的第二牺牲层141上。在特定实施例中,第二牺牲层140由非晶Ge或多晶Ge制成并且第三牺牲层160由非晶Si或多晶Si制成。
在特定实施例中,代替凹进(回蚀刻)第二牺牲层140以形成减薄的第二牺牲层141,通过使用CVD或ALD或其他合适的膜形成方法在第一绝缘层122上直接形成非晶或多晶Si的薄层(约1nm至约20nm)。之后,在薄第二牺牲层上形成第三牺牲层160(例如,非晶或多晶Ge)。
图6A至图6C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在形成第三牺牲层160之后,在第三牺牲层160上方形成掩模图案,并且通过使用掩模图案作为蚀刻掩模,图案化第三牺牲层160、减薄的第二牺牲层141和第一绝缘层122,从而在S/D结构120和121之间形成开口162。图6A至图6C示出了去除掩模层之后的结构。
可以通过使用光蚀刻操作图案化合适的掩模材料的层来形成掩模图案。蚀刻操作可以包括使用不同等离子体气体的多个蚀刻工艺。在一些实施例中,掩模图案在第三牺牲层160和栅极覆盖层132上方的X方向上延伸。掩模图案由诸如SiO2、SiN和/或SiON和/或TiN的介电材料的一层或多层制成。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积用于掩模图案的材料,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。
当Ge基材料(例如,Ge或SiGe)用作第三牺牲层160时,可以通过使用例如包括碳氟化合物的气体或包括卤素的气体的等离子体干蚀刻来实施蚀刻。在蚀刻期间,可以在介于20℃至约200℃之间的温度下加热衬底。当Si基材料(例如,多晶Si或非晶Si)用作第二牺牲层140时,可以通过使用例如包括HBr的气体或包括Cl2或SF6的气体的等离子体干蚀刻来实施蚀刻。当SOC(旋涂碳)用作第二牺牲层140时,可以通过使用例如包括N2和H2的气体或包括SO2和O2的气体的等离子体干蚀刻来实施蚀刻。当通过FCVD形成的氧化Si基材料用作第二牺牲层和/或第三牺牲层时,可以通过使用例如包括碳氟化合物和/或氟的气体的等离子体干蚀刻来实施蚀刻。在一些实施例中,第一绝缘层122没有被完全蚀刻并且保留在隔离绝缘层105上。
在一些实施例中,在Y方向上的开口宽度Wsp在从约5nm至约40nm的范围内,并且在其他实施例中,在从约10nm至约40nm的范围内。宽度Wsp可以是依赖于半导体器件的设计规则和/或类型的其他值。
应该注意,如图6A和图6C所示,在第三牺牲层160、减薄的第二牺牲层141的图案化期间基本没有蚀刻栅极覆盖层132。换句话说,用于栅极覆盖层132的材料相对于第二牺牲层和第三牺牲层具有高的蚀刻选择性(例如,5或更多)。
图7A至图7C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,在图案化的第三牺牲层和图案化的第二牺牲层以及第一绝缘层上方形成第二绝缘层146。如图7A和图7C所示,第二绝缘层146也形成在侧壁间隔件134和栅极覆盖层132上。
在一些实施例中,第二绝缘层146包括SiO2、SiCN、SiON、SiCN、SiOCN和SiN,但是可以使用其他合适的介电材料。在一个实施例中,使用诸如SiN的氮化硅基材料。第二绝缘层146可以由包括上述材料的组合的多个层制成。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积第二绝缘层146,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。在一些实施例中,第二绝缘层146具有介于约1nm和约10nm之间的厚度。在其他实施例中,使用其他厚度。
图8A至图8C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在形成第二绝缘层146之后,第一层间介电(ILD)层145形成为填充开口162并且位于第三牺牲层160上方。
ILD层145可以包括单层或多层。在一些实施例中,ILD层145包括SiO2、SiCN、SiOC、SiON、SiOCN、SiN或低k材料,但是可以使用其他合适的介电膜。可以通过CVD、PECVD或ALD、FCVD或旋涂玻璃工艺形成ILD层145。可以实施诸如CMP工艺的平坦化工艺以去除过量的材料。在一些实施例中,通过平坦化工艺,暴露第三牺牲层160(和覆盖绝缘层132)的上表面。
图9A至图9C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,去除第三牺牲层160,从而形成接触开口148和149以暴露由第一绝缘层122覆盖的S/D结构120、121。去除第三牺牲层160的蚀刻操作可以是各向同性或各向异性的。此外,去除第一绝缘层122,从而暴露S/D结构120、121。
当Ge基材料(例如,Ge或SiGe)用作第三牺牲层160时,可以通过使用例如臭氧的等离子体干蚀刻或使用含NH4OH和H2O2的溶液或者含HCl和H2O2的溶液的湿蚀刻来实施蚀刻。可以使用合适的蚀刻操作去除剩余的第一绝缘层122。
当Si基材料(例如,多晶Si或非晶Si)用作第二牺牲层140时,可以通过使用包括Cl2和NF3的气体或包括F2的气体的等离子体干蚀刻或使用NH4OH和/或四甲基氢氧化铵(TMAH)的湿蚀刻来实施蚀刻。当SOC(旋涂碳)用作第二牺牲层140时,可以使用例如包括N2和H2的气体或包括SO2和O2的气体的等离子体干蚀刻来实施蚀刻。当通过FCVD形成的氧化Si基材料用作第二牺牲层和/或第三牺牲层时,可以通过使用例如HF或缓冲的HF(BHF)来实施蚀刻。
在一些实施例中,开口148、149沿着Y方向的宽度WCH在从约10nm至约100nm的范围内。
图10A至图10C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在去除第二牺牲层和第三牺牲层和去除形成在S/D结构120、121上的第一绝缘层122之后,在接触开口148、149中填充导电材料,从而形成S/D接触件150。
在一些实施例中,在暴露的S/D结构120、121上形成硅化物层。金属硅化物形成工艺可以在S/D结构的侧部上形成金属硅化物。金属硅化物形成工艺包括在S/D结构上沉积金属膜、热处理以在S/D结构的界面或表面处形成金属硅化物以及通过蚀刻工艺去除过量未反应的金属。金属硅化物包括TiSix、NiSix、CoSix、NiCoSix和TaSix,但是可以使用其他合适的硅化物材料。在一些实施例中,硅化物层具有介于约0.5nm和约10nm之间的厚度。在其他实施例中,在制造操作的这个阶段没有形成硅化物层,并且例如可以在形成第一绝缘层122之前的更早的制造阶段形成硅化物层。在一些实施例中,通过合适的蚀刻操作去除未形成在S/D外延层上的金属膜和未被消耗以形成硅化物层的金属膜。在其他实施例中,没有去除金属膜并且保留金属膜。
S/D接触件150可以包括单层或多层结构。例如,在一些实施例中,接触件150包括位于接触开口148、149中的接触衬垫层(诸如扩散阻挡层、粘合层等),以及在接触衬垫层上方形成的接触体。接触衬垫层可以包括通过ALD、CVD等形成的Ti、TiN、Ta、TaN等。可以通过沉积诸如Ni、Ta、TaN、W、Co、Ti、TiN、Al、Cu、Au、它们的合金、它们的组合等的一层或多层的导电材料形成接触体,但是也可以使用其他合适的金属。可以实施诸如CMP的平坦化工艺以从ILD层145的表面去除过量的材料。
在一些实施例中,在形成S/D接触件150之后,从鳍结构104的顶部测量的包括栅极覆盖层132的栅极结构的高度Hg在从约20nm至100nm的范围内并且从鳍结构104的顶部测量的金属栅极130的高度Hmg在从约10nm至约60nm的范围内。
在形成接触件150之后,实施进一步的CMOS工艺以形成诸如额外的层间介电层、接触件/通孔、互连金属层和钝化层等的各个部件。
图11A至图21C示出了根据本发明的其他实施例的半导体器件制造工艺中的各个工艺。在图11A至图21C中,“A”图(例如,图11A、图12A等)示出了立体图,“B”图(例如,图11B、图12B等)示出了沿着对应于图11A和图12A中示出的线Y1-Y1的Y方向的截面图,并且“C”图(例如,图11C、图12C等)示出了沿着对应于图11A和图12A中示出的线X1-X1的X方向的截面图。应该理解,可以在图11A至图21C所示的工艺之前、期间和之后提供额外的操作,并且对于方法的额外实施例,可以替换或消除以下描述的一些操作。操作/工艺的顺序可以互换。在一些实施例中可以采用与参照图1A至图10C描述的上述实施例相同或类似的材料、配置、尺寸和/或工艺,并且可以省略它们详细的说明。
图11A至图11C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
图11A至图11C所示结构与图2A至图2C所示的结构基本类似,除了还未形成栅极结构并且设置伪栅电极230、伪栅极介电层231和栅极掩模层232,代替栅电极130、栅极介电层131和栅极覆盖层132之外。制造伪栅极结构的操作如上所述。
图12A至图12C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
与图3A至图3C类似,在开口116中形成第二牺牲层140。
图13A至图13C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
与图4A至图4C类似,使第二牺牲层140凹进以形成减薄的第二牺牲层141,从而形成开口144。
图14A至图14C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
与图5A至图5C类似,在开口144中形成第三牺牲层160。
15A至图15C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,将第三牺牲层160部分地凹进至Z方向上的伪栅电极230的中间部分的水平,从而形成开口164。可以通过回蚀刻工艺和/或湿蚀刻使第三牺牲层160凹进。在一些实施例中,凹进的第三牺牲层160的剩余的厚度Hsc在从约40nm至约200nm的范围内。
图16A至图16C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
用绝缘材料填充开口164,从而形成掩模层220。在一些实施例中,掩模层220由SiOC、SiC、SiON、SiCN、SiOCN、SiN和/或SiO2的一层或多层制成。在一个实施例中,使用SiN。可以通过诸如PVD、CVD或ALD的一种或多种工艺沉积掩模层220,但是可以利用任何可接受的工艺。可以使用其他材料和/或工艺。可以实施诸如回蚀刻工艺或CMP的平坦化操作来平坦化掩模层的上表面和栅极掩模层232。通过平坦化操作,暴露伪栅电极层230的上表面。
图17A至图17C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,去除伪栅电极230和伪栅极介电层231,从而形成开口235。参照以上图1A至图1C来说明去除操作。
图18A至图18C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
在去除伪栅极结构之后,在鳍结构104的沟道区域上方形成栅极介电层131,并且在栅极介电层131上形成用于栅电极130的导电层。栅极形成操作为以上参照图1A至图1C所说明的。
可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的工艺形成栅电极130。可以实施诸如CMP的平坦化操作以去除过量的材料。在平坦化操作之后,暴露掩模层220。
图19A至图19C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,使栅电极层凹进,从而形成栅电极130和栅极覆盖开口237。
图20A至图20C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
之后,在栅极覆盖开口237中和掩模层220上方形成绝缘层132。在一些实施例中,用于栅极覆盖层132的绝缘层包括SiO2、SiCN、SiON、SiN、Al2O3、La2O3、它们的组合等,但是可以使用其他合适的介电膜。可以使用例如CVD、PVD、旋涂等形成用于栅极覆盖层132的绝缘层。可以使用其他合适的工艺步骤。
图21A至图21C示出了根据本发明的一些实施例的用于制造FinFET器件的各个阶段的一个的视图。
随后,可以实施诸如CMP的平坦化工艺以去除过量的材料,从而形成栅极覆盖层132。
图21A至图21C的结构与图5A至图5C的结构基本相同。随后,实施与图6A至图10C说明的相同的操作。
图22A至图23B示出了根据本发明的一些实施例的半导体器件的视图。
在本发明的一些实施例中,在形成外延层以形成S/D结构120、122之前,对应于S/D区域的鳍104的上部由覆盖层(由例如SiN制成)覆盖,并且之后从鳍104去除覆盖层以及之后形成外延层。在这种情况下,覆盖层109保留在鳍104的底部处。在未由覆盖层109覆盖的鳍104上形成用于S/D结构120、122的外延层。
当使第二牺牲层140凹进时,使第二牺牲层140凹进至用于S/D结构120、122的外延层的水平。换句话说,减薄的第二牺牲层141具有使得减薄的牺牲层的上表面与S/D结构120、122接触或与S/D结构120、122的底部齐平的厚度。
当形成开口148和149(见图9A至图9C)时,没有蚀刻减薄的第二牺牲层141或仅部分地蚀刻减薄的第二牺牲层141。因此,如图23A所示,第二牺牲层141保留在S/D接触件150下方。
图24A至图24C示出了根据本发明的一些实施例的半导体器件的视图。
图24A与图23B基本相同,其中,减薄的第二牺牲层141保留在S/D结构120、122的底部或高于S/D结构120、122的底部。在一些实施例中,减薄的第二牺牲层141的厚度Tge在从约0nm至约45nm的范围内。减薄的第二牺牲层可以等于或高于或低于S/D结构120、122的底部。
如图24B所示,减薄的第二牺牲层141保留在S/D结构120、122的底部之下。在一些实施例中,减薄的第二牺牲层141的厚度Tge在从约0nm至约45nm的范围内。减薄的第二牺牲层可以等于或高于或低于S/D结构120、122的底部。在其他实施例中,如图24C所示,没有保留减薄的第二牺牲层141。
此外,在一些实施例中,由于第三牺牲层蚀刻的蚀刻性质,开口162具有上部宽度大于底部宽度的锥形形状。因此,开口148和149具有上部宽度小于下部宽度的反锥形形状(如图22B所示),并且之后S/D接触件150也具有反锥形形状(如图23B所示)。
图25A至图25C示出了根据本发明的一些实施例的半导体器件的视图。图25B是对应于图25A的线X2-X2的截面图,并且图25C是对应于图25A的线X1-X1的截面图。
在一些实施例中,在开口162(见图6A至图6C)的形成期间,稍微蚀刻栅极覆盖层132的上部。因此,如图25B所示,位于S/D结构120和121之间的ILD层145的上部沿着X方向具有漏斗形状,该漏斗形状具有比主体区域更宽的顶部。
在一些实施例中,在开口148和149(见图9A至图9C)的形成期间,稍微蚀刻栅极覆盖层132和侧壁间隔件134的上部。因此,如图25C所示,S/D接触件150的上部沿着X方向具有漏斗形状,该漏斗形状具有比主体区域更宽的顶部。
在一些实施例中,Ge用作第三牺牲层160。因此,Ge元素扩散至第二绝缘层146和/或ILD层145,并且可以在绝缘层146和/或ILD层145中或上发现Ge元素(或GeO(氧化锗)的形式)。
应该理解,不是所有的优势都必须在此处讨论,没有特定的优势对所有实施例或实例都是需要的,并且其他实施例或实例可以提供不同的优势。
例如,在本发明中,由于使用相对于绝缘层(例如,氧化硅基材料、氮化硅基材料)具有更高蚀刻选择性的材料(例如,Ge)作为第二牺牲层和第三牺牲层,因此可以更精确地控制S/D结构和S/D接触结构的大小。通过这些制造方法,材料可以容易地填充侧壁间隔件之间的间隔以形成无空隙膜。此外,侧壁间隔件之间的全部间隔可以全部用于S/D接触件并且对接触区域产生较小的损坏。由于S/D接触件的区域更宽,因此可以通过对氧化硅和/或氮化硅更高的选择性蚀刻形成环绕接触件以获得接触区域。通过上述结构和方法,可以避免S/D外延层受到损坏并且形成环绕的接触结构。
根据本发明的方面,在形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法中,在FinFET结构的源极/漏极结构和隔离绝缘层上方形成第一牺牲层。使第一牺牲层凹进,使得在隔离绝缘层上形成第一牺牲层的剩余层并且暴露源极/漏极结构的上部。在剩余层和暴露的源极/漏极结构上形成第二牺牲层。图案化第二牺牲层和剩余层,从而形成开口。在开口中形成介电层。在形成介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在源极/漏极结构上方形成接触开口。在接触开口中形成导电层。
根据本发明的另一方面,在形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法中,在第一FinFET结构的第一源极/漏极结构、第二FinFET结构的第二源极/漏极结构和隔离绝缘层上方形成第一牺牲层。第一源极/漏极结构设置为邻近于第二源极/漏极结构。使第一牺牲层凹进,使得在隔离绝缘层上形成第一牺牲层的剩余层并且暴露第一源极/漏极结构和第二源极/漏极结构的上部。在剩余层以及暴露的第一源极/漏极结构和暴露的第二源极/漏极结构上形成第二牺牲层。图案化第二牺牲层和剩余层,从而在第一源极/漏极结构和第二源极/漏极结构之间形成开口。在开口中形成介电层。在形成介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在第一源极/漏极结构上方形成第一接触开口并且在第二源极/漏极结构上方形成第二接触开口。在第一接触开口中形成第一导电层并且在第二接触开口中形成第二导电层。
根据本发明的另一方面,包括鳍式场效应晶体管(FinFET)的半导体器件包括第一FinFET和第二FinFET以及介电层。第一FinFET包括在第一方向上延伸的第一鳍结构、第一源极/漏极结构以及与第一源极/漏极结构接触的第一源极/漏极接触件。第二FinFET设置为邻近于第一FinFET并且包括在第一方向上延伸的第二鳍结构、第二源极/漏极结构以及与第二源极/漏极结构接触的第二源极/漏极接触件。介电层将第一源极/漏极结构和第二源极/漏极结构分隔开。介电层由硅基绝缘材料制成,并且在介电层与第一源极/漏极接触件和第二源极/漏极接触件的一个之间的界面处或附近包含Ge。
根据本发明的一些实施例,提供了一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:在鳍式场效应晶体管结构的源极/漏极结构和隔离绝缘层上方形成第一牺牲层;使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述源极/漏极结构的上部暴露;在所述剩余层和暴露的源极/漏极结构上形成第二牺牲层;图案化所述第二牺牲层和所述剩余层,从而形成开口;在所述开口中形成介电层;在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述源极/漏极结构上方形成接触开口;以及在所述接触开口中形成导电层。
在上述方法中,在形成所述第一牺牲层之前,在所述源极/漏极结构和所述隔离绝缘层上方形成第一绝缘层,在使所述第一牺牲层凹进之后,暴露覆盖所述源极/漏极结构的上部的所述第一绝缘层,以及当形成所述接触开口时,也去除所述第一绝缘层。
在上述方法中,所述第一牺牲层由Si1-xGex制成,其中,0≤x≤0.4。
在上述方法中,所述第二牺牲层由Si1-yGey制成,其中,0.6≤y≤1。
在上述方法中,还包括,在图案化所述第二牺牲层之后以及在形成所述介电层之前:在所述开口中以及图案化的所述第二牺牲层上方形成第二绝缘层。
在上述方法中,所述第二牺牲层由与所述隔离绝缘层、所述第一绝缘层和所述第二绝缘层不同的材料制成。
在上述方法中,所述源极/漏极结构包括鳍结构以及在所述鳍结构的两个相对侧面和顶部上形成的一个或多个外延层。
在上述方法中,还包括,在形成所述第一牺牲层之前,形成所述鳍式场效应晶体管的金属栅极结构。
在上述方法中,还包括,在形成所述接触开口之后并且在形成所述导电层之前:在所述源极/漏极结构上方形成硅化物层。
在上述方法中,所述源极/漏极结构包括嵌入在所述隔离绝缘层内的鳍结构以及在所述鳍结构的顶部上形成的一个或多个外延层。
根据本发明的另一些实施例,还提供了一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:在第一鳍式场效应晶体管结构的第一源极/漏极结构、第二鳍式场效应晶体管结构的第二源极/漏极结构和隔离绝缘层上方形成第一牺牲层,所述第一源极/漏极结构设置为邻近所述第二源极/漏极结构;使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述第一源极/漏极结构和所述第二源极/漏极结构的上部暴露;在所述剩余层以及暴露的第一源极/漏极结构和暴露的第二源极/漏极结构上形成第二牺牲层;图案化所述第二牺牲层和所述剩余层,从而在所述第一源极/漏极结构和所述第二源极/漏极结构之间形成开口;在所述开口中形成介电层;在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述第一源极/漏极结构上方形成第一接触开口并且在所述第二源极/漏极结构上方形成第二接触开口;以及在所述第一接触开口中形成第一导电层并且在所述第二接触开口中形成第二导电层。
在上述方法中,还包括,在形成所述第二牺牲层之后并且在形成掩模图案之前:在所述第一鳍式场效应晶体管结构和所述第二鳍式场效应晶体管结构的至少一个上方形成金属栅极结构。
在上述方法中,形成所述金属栅极结构包括:在所述第二牺牲层上方形成硬掩模层;去除伪栅极结构,从而形成栅极间隔;在所述栅极间隔中形成所述金属栅极结构;以及在所述金属栅极结构上方形成栅极覆盖层。
在上述方法中,在形成所述第一牺牲层之前,在所述第一源极/漏极结构和所述第二源极/漏极结构以及所述隔离绝缘层上方形成第一绝缘层,在使所述第一牺牲层凹进之后,暴露覆盖所述第一源极/漏极结构和所述第二源极/漏极结构的上部的所述第一绝缘层,以及当形成所述第一接触开口和所述第二接触开口时,也去除所述第一绝缘层。
在上述方法中,所述第一牺牲层由Si1-xGex制成,其中,0≤x≤0.4。
在上述方法中,所述第二牺牲层由Si1-yGey制成,其中,0.6≤y≤1。
在上述方法中,还包括,在图案化所述第二牺牲层之后并且在形成所述介电层之前:在所述开口中以及图案化的所述第二牺牲层上方形成第二绝缘层。
在上述方法中,所述第一源极/漏极结构和所述第二源极/漏极结构均包括鳍结构以及在所述鳍结构的两个相对侧面和顶部上形成的一个或多个外延层。
在上述方法中,还包括,在形成所述第一接触开口和所述第二接触开口之后并且在形成所述第一导电层和所述第二导电层之前:在所述第一源极/漏极结构和所述第二源极/漏极结构上方形成硅化物层。
根据本发明的又一些实施例,还提供了一种包括鳍式场效应晶体管(FinFET)的半导体器件,包括:第一鳍式场效应晶体管,包括在第一方向上延伸的第一鳍结构、第一源极/漏极结构以及与所述第一源极/漏极结构接触的第一源极/漏极接触件;第二鳍式场效应晶体管,设置为邻近所述第一鳍式场效应晶体管并且包括在所述第一方向上延伸的第二鳍结构、第二源极/漏极结构以及与所述第二源极/漏极结构接触的第二源极/漏极接触件;以及介电层,将所述第一源极/漏极结构和所述第二源极/漏极结构分隔开,其中,所述介电层由硅基绝缘材料制成,并且在所述介电层与所述第一源极/漏极接触件和所述第二源极/漏极接触件中的一个之间的界面处或附近包含Ge。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:
在鳍式场效应晶体管结构的源极/漏极结构和隔离绝缘层上方形成第一牺牲层;
使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述源极/漏极结构的上部暴露;
在所述剩余层和暴露的源极/漏极结构上形成第二牺牲层;
图案化所述第二牺牲层和所述剩余层,从而形成开口;
在所述开口中形成介电层;
在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述源极/漏极结构上方形成接触开口;以及
在所述接触开口中形成导电层。
2.根据权利要求1所述的方法,其中:
在形成所述第一牺牲层之前,在所述源极/漏极结构和所述隔离绝缘层上方形成第一绝缘层,
在使所述第一牺牲层凹进之后,暴露覆盖所述源极/漏极结构的上部的所述第一绝缘层,以及
当形成所述接触开口时,也去除所述第一绝缘层。
3.根据权利要求1所述的方法,其中,所述第一牺牲层由Si1-xGex制成,其中,0≤x≤0.4。
4.根据权利要求1所述的方法,其中,所述第二牺牲层由Si1-yGey制成,其中,0.6≤y≤1。
5.根据权利要求1所述的方法,还包括,在图案化所述第二牺牲层之后以及在形成所述介电层之前:
在所述开口中以及图案化的所述第二牺牲层上方形成第二绝缘层。
6.根据权利要求5所述的方法,其中,所述第二牺牲层由与所述隔离绝缘层、所述第一绝缘层和所述第二绝缘层不同的材料制成。
7.根据权利要求1所述的方法,其中,所述源极/漏极结构包括鳍结构以及在所述鳍结构的两个相对侧面和顶部上形成的一个或多个外延层。
8.根据权利要求1所述的方法,还包括,在形成所述第一牺牲层之前,形成所述鳍式场效应晶体管的金属栅极结构。
9.一种形成包括鳍式场效应晶体管(FinFET)的半导体器件的方法,所述方法包括:
在第一鳍式场效应晶体管结构的第一源极/漏极结构、第二鳍式场效应晶体管结构的第二源极/漏极结构和隔离绝缘层上方形成第一牺牲层,所述第一源极/漏极结构设置为邻近所述第二源极/漏极结构;
使所述第一牺牲层凹进,使得所述第一牺牲层的剩余层形成在所述隔离绝缘层上并且所述第一源极/漏极结构和所述第二源极/漏极结构的上部暴露;
在所述剩余层以及暴露的第一源极/漏极结构和暴露的第二源极/漏极结构上形成第二牺牲层;
图案化所述第二牺牲层和所述剩余层,从而在所述第一源极/漏极结构和所述第二源极/漏极结构之间形成开口;
在所述开口中形成介电层;
在形成所述介电层之后,去除图案化的第一牺牲层和图案化的第二牺牲层以在所述第一源极/漏极结构上方形成第一接触开口并且在所述第二源极/漏极结构上方形成第二接触开口;以及
在所述第一接触开口中形成第一导电层并且在所述第二接触开口中形成第二导电层。
10.一种包括鳍式场效应晶体管(FinFET)的半导体器件,包括:
第一鳍式场效应晶体管,包括在第一方向上延伸的第一鳍结构、第一源极/漏极结构以及与所述第一源极/漏极结构接触的第一源极/漏极接触件;
第二鳍式场效应晶体管,设置为邻近所述第一鳍式场效应晶体管并且包括在所述第一方向上延伸的第二鳍结构、第二源极/漏极结构以及与所述第二源极/漏极结构接触的第二源极/漏极接触件;以及
介电层,将所述第一源极/漏极结构和所述第二源极/漏极结构分隔开,
其中,所述介电层由硅基绝缘材料制成,并且在所述介电层与所述第一源极/漏极接触件和所述第二源极/漏极接触件中的一个之间的界面处或附近包含Ge。
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US10008497B2 (en) | 2018-06-26 |
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US20180151565A1 (en) | 2018-05-31 |
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US20180263684A1 (en) | 2018-09-20 |
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US11695006B2 (en) | 2023-07-04 |
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US11007005B2 (en) | 2021-05-18 |
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