CN111199886A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN111199886A
CN111199886A CN201911055398.8A CN201911055398A CN111199886A CN 111199886 A CN111199886 A CN 111199886A CN 201911055398 A CN201911055398 A CN 201911055398A CN 111199886 A CN111199886 A CN 111199886A
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layer
semiconductor
sacrificial
forming
gate
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CN111199886B (zh
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马库斯·约翰内斯·亨里克斯·凡·达尔
荷尔本·朵尔伯斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件包括电源开关电路和逻辑电路。半导体器件包括第一介电层和形成在第一介电层上的薄膜晶体管(TFT)。TFT包括半导体纳米片，包裹半导体纳米片的沟道区域的栅极介电层，以及形成在栅极介电层上的栅电极层。半导体纳米片由氧化物半导体材料制成。本发明的实施例还涉及制造半导体器件的方法。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体器件及其制造方法。
背景技术
随着半导体器件的尺寸变小，标准单元的单元高度也变小。单元高度通常被定义为两条电源线VDD和VSS之间的周期性距离(间距)，并且通常由鳍结构和/或金属线的数量和间距确定。单元高度也称为轨道高度。典型的轨道高度是7.5T、6.5T或5.5T，其中T是在标准单元上运行的金属线的最小间距。当前需要缩小至4.5T或4T，以进一步减小半导体器件的尺寸。
发明内容
本发明的实施例提供了一种制造半导体器件的方法，包括：形成包括交替堆叠的半导体层和牺牲层的堆叠件结构；在所述堆叠件结构上方形成牺牲栅极结构；在所述牺牲栅极结构上方形成介电层；去除所述牺牲栅极结构，从而形成栅极间隔；去除所述栅极间隔中的所述牺牲层，从而释放所述半导体层；以及形成包裹所述半导体层的栅极结构，其中，所述半导体层由氧化物半导体材料制成。
本发明的另一实施例提供了一种制造半导体器件的方法，包括：在第一介电层上方形成包括交替堆叠的半导体层和牺牲层的鳍结构；在所述鳍结构上方形成牺牲栅极结构；在所述牺牲栅极结构的相对侧面上形成栅极侧壁间隔件；在所述牺牲栅极结构和所述鳍结构上方形成第二介电层；去除所述牺牲栅极结构，从而形成栅极间隔；去除所述栅极间隔中的所述牺牲层，从而释放所述半导体层的沟道区域；形成包裹所述半导体层的所述沟道区域的栅极结构；形成第三介电层；在所述第三介电层和所述第二介电层中形成接触开口；去除所述接触开口中的所述牺牲层，从而释放所述半导体层的源极/漏极区域；以及形成包裹所述半导体层的所述源极/漏极区域的源极/漏极接触件，其中，所述半导体层由氧化物半导体材料制成。
本发明的又一实施例提供了一种包括电源开关电路和逻辑电路的半导体器件，该电源开关电路包括：第一介电层；薄膜晶体管(TFT)，形成在所述第一介电层上，其中：所述薄膜晶体管包括：垂直布置的半导体纳米片；栅极介电层，包裹每个所述半导体纳米片的沟道区域；栅电极层，形成在所述栅极介电层上，其中，所述半导体纳米片由氧化物半导体材料制成。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明实施例的半导体器件的电路图。
图2示出了根据本发明实施例的半导体器件的截面图。
图3示出了根据本发明实施例的半导体器件的截面图。
图4示出了根据本发明实施例的半导体器件的截面图。
图5示出了根据本发明实施例的半导体器件的截面图。
图6A和图6B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图6A是等轴视图，并且图6B是平面图。
图7A和图7B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图7A是等轴视图，并且图7B是平面图。
图8A和图8B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图8A是等轴视图，并且图8B是平面图。
图9A和图9B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图9A是等轴视图，并且图9B是平面图。
图10A和图10B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图10A是等轴视图，图10B是平面图。
图11A和图11B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图11A是等轴视图，并且图11B是平面图。
图12A和图12B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图12A是等轴视图，并且图12B是平面图。
图13A和图13B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图13A是等轴视图，并且图13B是平面图。
图14A和图14B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图14A是等轴视图，并且图14B是平面图。
图15A和图15B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图15A是等轴视图，并且图15B是平面图。
图16A和图16B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图16A是等轴视图，并且图16B是平面图。
图17A和图17B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图17A是等轴视图，并且图17B是平面图。
图18A和图18B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图18A是等轴视图，并且图18B是平面图。
图19A和图19B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图19A是等轴视图，并且图19B是平面图。
图20A和图20B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图20A是等轴视图，并且图20B是平面图。
图21A和图21B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图21A是等轴视图，并且图21B是平面图。
图22A和图22B是根据本发明的实施例的制造半导体器件的顺序工艺的示意图。图22A是等轴视图，并且图22B是平面图。
图23示出了根据本发明实施例的半导体FET器件的截面图。
具体实施例
应当理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限于所公开的范围或值，而是可以取决于工艺条件和/或装置的期望特性。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚起见，可以以不同比例任意绘制各种部件。在附图中，为了简化，可以省略一些层/部件。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等间隔相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，间隔相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的间隔相对描述符可以同样地作出相应的解释。另外，术语“由…制成”可以表示“包含”或“由…组成”。此外，在随后的制造工艺中，在所描述的操作期间/之间可能存在一个或多个附加操作，并且操作顺序可以改变。在以下实施例中，术语“上部”，“在…上方”和/或“上方”是沿着与前表面和后表面的距离增加的方向定义的。如在实施例中说明的材料、配置、尺寸、工艺和/或操作可以在其它实施例中采用，并且可以省略其详细描述。
对于用于高速操作的半导体器件和/或用于移动终端的半导体器件，诸如集成电路(IC)的半导体器件中的功耗的最小化是关键问题。已经提出了各种降低功耗的技术，但是由于用于控制功率的附加电路，许多附加电路需要更大的芯片面积。一种这样的技术包括在主电源线(VDD和/或VSS)和虚拟电源线之间提供虚拟电源线(VVDD和/或VVSS)以及头部开关和/或脚部开关。虚拟电源线可以称为局部电源线，而主电源线可以称为全局电源线。应该注意，VDD通常处于比VSS更高的电势(电压)，并且在一些实施例中，VSS耦合至地(0V)。通过断开(打开)与半导体器件中的非有源功能电路耦合的头部/脚部开关，来降低功耗。
图1示出了根据本发明实施例的半导体器件的电路图。如图1所示，p型MOS FET用作头部开关，n型MOS FET用作脚部开关，以切断向局部VVDD的电源，该局部VVDD进一步向包括一个或多个标准单元STDC的模块供电，每个标准单元包括功能电路(例如，CMOS反相器)。在一些实施例中，不使用脚部开关，并且标准单元直接耦合至VSS。在一些实施例中，如图1所示，第一主电源线VDD耦合至VDD生成电路(Vdd源)，该VDD生成电路生成诸如0.5V、0.8V、1.0V、1.2V、1.8V、2.4V、3.3V或5.0V的电压。在一些实施例中，第二主电源线VSS耦合至VSS生成电路(Vss源)，该VSS生成电路生成低于VDD或地的电压。如图1所示，局部电源线VVDD被分成多条局部电源线作为单元块，每个局部电源线连接一个或多个标准单元STDC。因此，可以逐块地控制至标准单元的电源。此外，在一些实施例中，标准单元STDC包括内部电源线(总线)INT，并且局部电源线VVDD通过或不通过开关耦合至内部电源线。
在本发明的实施例中，在半导体器件中，将电源开关电路(头部和/或脚部开关)从前段制程(FEOL)电路电平移动至后段制程(BEOL)电路电平，以减小器件的尺寸，如图2所示。FEOL电路电平包括形成在半导体衬底上的MOS晶体管。MOS晶体管包括平面场效应晶体管(FET)、鳍式FET和/或全环栅(GAA)FET。在一些实施例中，FEOL电路电平还包括局部互连。BEOL电路电平包括金属布线结构，该金属布线结构包括一个或多个介电层、嵌入在介电层中的金属布线和通孔。将电源开关电路从FEOL电路电平移动至BEOL电路电平中的布线层可以使器件面积减少约10％。将电源开关电路放置在BEOL电路电平中需要使用的通孔更少，从而为逻辑块腾出了更多的布线空间，从而增加了逻辑块中的器件密度。使用非晶态半导体的TFT适合于后段制程工艺，因为非晶态半导体通常可以在例如低于450℃的低温下形成。
在一些实施例中，电源开关电路包括如图2所示的薄膜晶体管(TFT)，因为TFT的制造操作通常不需要高温来形成，例如外延半导体沟道，并且适合于BEOL电路电平。如图2所示，电源开关电路被置于例如M1-M2电平、M4-M5电平或M8-M9电平。
在本发明的一些实施例中，TFT的沟道区域包括氧化物半导体，诸如非晶铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。
电源开关电路的晶体管通常需要低的导通电阻Ron＝Vds/Id。例如，IGZO提供了极低的截止电流Ioff(低泄漏电流)，并且IGZO TFT具有较大的Ion/Ioff比。但是，由于非晶态IGZO(a-IGZO)具有较低的电子迁移率
Figure BDA0002256408380000061
所以由a-IGZO制成的单层平面TFT不足以满足电源开关电路所需的Ron值。
为了补偿该特性，在一些实施例中，增加沟道宽度Weff以提供低的Ron＞Reh＝Lg/(Weff迁移率Cox(Vg-Vt))，因为Cox通常由于栅极电流限制无法增加，并且Vg-Vt由电源电压设置。在本发明的实施例中，提供了多个堆叠的纳米片全环栅氧化物半导体器件结构和相应的工艺流程，以增加每覆盖区的有效宽度以减小Ron而不会损害Ion/Ioff比。使用如IGZO的氧化物半导体的益处包括低漏电流、合理的电子迁移率和高可靠性。
根据本发明的实施例，图3是横跨半导体器件的氧化物半导体纳米片的示意性截面图(X-Z平面)，图4是横跨半导体器件的栅电极的示意性截面图(Y-Z平面)。
在一些实施例中，半导体器件是如图3和图4所示的全环栅(GAA)FET。在一些实施例中，氧化物半导体纳米片25在Y方向(源极至漏极方向)上延伸并且沿着Z方向(垂直方向)堆叠。尽管在图3和图4中示出了四个氧化物半导体纳米片25，但是取决于所需电流，氧化物半导体纳米片25的数量可以少至2并且可以多达20。在一些实施例中，氧化物半导体纳米片的数量为从4至10。在一些实施例中，氧化物半导体纳米片25的宽度W1在从约10nm至约50nm的范围内，并且在其它实施例中，在从约15nm至约30nm的范围内，这取决于所需的电流和/或制造工艺条件。在一些实施例中，氧化物半导体纳米片25的厚度T1在从约5nm至约30nm的范围内，并且在其它实施例中，在从约10nm至约20nm的范围内，这取决于所需的电流和/或制造工艺条件。在一些实施例中，W1＞T1。在一些实施例中，高宽比W1/T1在从约1.2至约10的范围内，并且在其它实施例中在从约2至约5的范围内。在一些实施例中，相邻氧化物半导体纳米片25之间的间隔S1在从约5nm至约30nm的范围内，并且在其它实施例中，在从约10nm至约20nm的范围内，这取决于所需的电流和/或制造工艺条件。在一些实施例中，S1≥T1，在其它实施例中，S1＜T1。如果间隔S1太窄，则将难以均匀地形成要包裹氧化物半导体纳米片25的层(例如，栅极介电层和栅电极层)。
栅极介电层82包裹每个氧化物半导体纳米片25。在一些实施例中，栅极介电层是高k介电材料，诸如氮化硅、HfO2、La2O3、ZrO2、BaO、TiO2、Ta2O5、SrO、Y2O3、HfSiO4、ZrSiO4、Al2O3、MgO、CaO、其它合适的高k介电材料和/或它们的组合。在一些实施例中，栅极介电层82的厚度在从约2nm至约20nm的范围内。栅极介电层82可以由CVD、ALD或任何合适的方法形成。在实施例中，使用诸如ALD的高度共形沉积工艺来形成栅极介电层，以确保在每个氧化物半导体纳米片周围形成具有均匀厚度的栅极介电层。
在栅极介电层82上形成金属栅电极80，以包裹每个氧化物半导体纳米片25。在一些实施例中，金属栅电极80包括多个导电层。在一些实施例中，金属栅电极80包括一个或多个功函调整层84和体金属栅电极层86。功函调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层的导电材料制成，或这些材料的两种或多种的多层。功函调整层可以通过ALD、PVD、CVD、电子束蒸发或其它合适的工艺形成。此外，功函调整层84可以针对可以使用不同金属层的nFET和pFET分别形成。体栅电极层形成为围绕每个氧化物半导体纳米片(沟道区域)。体栅电极层包括一个或多个导电材料层，导电材料诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合。可以通过CVD、ALD、电镀或其它合适的方法来形成体栅电极层。
如图3所示，包括栅极介电层82和金属栅电极80的栅极结构设置在栅极侧壁间隔件48之间，并且如图3所示，还设置层间介电(ILD)层50。
在一些实施例中，内部间隔件21设置在栅电极层84和源极/漏极接触件70之间，如图4所示。内部间隔件21是牺牲层20的剩余部分，如下所述。
氧化物半导体纳米片25还具有如图4所示的源极/漏极区域。源极/漏极接触件70形成为与每个氧化物半导体纳米片25的源极/漏极区域接触并且包裹源极/漏极区域。在一些实施例中，源极/漏极接触件70具有多层结构。在如图4所示的一些实施例中，源极/漏极接触件70包括衬垫层或阻挡层72和体接触件层74。在一些实施例中，衬垫层72由Ti、TiN、Ta和TaN中的一种或多种制成，并且体接触件层74由W、Cu、Ti、Ag、Al、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr中的一种或多种制成。
在一些实施例中，氧化物半导体纳米片25穿过源极/漏极接触件70并且到达ILD层50，如图4所示。在其它实施例中，氧化物半导体纳米片25的端部位于源极/漏极接触件70中。
图5是根据本发明的另一实施例的横跨半导体器件的栅电极的示意性截面图(Y-Z平面)。
在该实施例中，氧化物半导体纳米片25不穿透或不穿过源极/漏极接触件70。如图5所示，源极/漏极接触件70覆盖氧化物半导体纳米片25的端面。
图6A至图20B示出了根据本发明实施例的用于制造半导体器件的顺序操作。应该理解，对于该方法的其它实施例，可以在图6A至图20B所示的工艺之前、期间和之后提供附加的操作，并且可以替换或消除以下描述的一些操作。操作/工艺的顺序可以互换。“A”图显示等轴视图，并且“B”图显示平面图(俯视图)。
图6A和图6B是根据本发明的实施例的半导体器件的顺序制造操作的阶段的一个的示意图。如图6A所示，提供衬底5。在一些实施例中，衬底5至少在其表面部分上包括单晶半导体层。衬底5可以包括单晶半导体材料，诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在某些实施例中，衬底5由晶体Si、SiGe或Ge制成。在一些实施例中，衬底5可在其表面区域中包括一个或多个缓冲层(未示出)。缓冲层可以用于从衬底的晶格常数逐渐改变为源极/漏极区域的晶格常数。缓冲层可以由外延生长的单晶半导体材料形成，单晶半导体材料诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在特定实施例中，衬底5包括外延生长在硅衬底5上的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从最底部的缓冲层的30％原子的锗增加至最顶部的缓冲层的70％原子的锗。
此外，如图6A所示，在衬底5上方形成一个或多个第一层间介电(ILD)层10。在一些实施例中，诸如晶体管(例如，场效应晶体管)、存储器(例如，动态随机存取存储器(DRAM)、静态RAM、磁MRAM、和/或相变RAM)的一个或多个电子器件形成在衬底5上，并且一个或多个第一层间介电层10覆盖电子器件。
在一些实施例中，在ILD层10中嵌入一个或多个金属布线结构。用于第一ILD层10的介电材料包括氧化硅、氮化硅、氮氧化硅(SiON)、SiCN、掺氟硅酸盐玻璃(FSG)或低K介电材料，通过LPCVD(低压化学汽相沉积)、等离子CVD或可流动CVD或任何其它合适的膜形成方法形成的膜。可以在形成第一ILD层10之后实施退火操作。在一些实施例中，实施诸如化学机械抛光(CMP)方法和/或回蚀方法的平坦化操作以平坦化第一ILD层10的表面。
图7A和图7B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。在一些实施例中，在ILD层10上方交替地形成半导体层25和牺牲层20。
在一些实施例中，半导体层25由氧化物半导体材料制成，诸如非晶铟镓锌氧化物(IGZO)、C轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在一些实施例中，使用非晶IGZO。半导体层25通过CVD、原子层沉积(ALD)、包括溅射的物理汽相沉积或任何其它合适的成膜方法来形成。在一些实施例中，通过在从约50℃至600℃范围内的温度下的CVD形成半导体层25。在其它实施例中，半导体层25通过原子层沉积(ALD)在从约25℃至400℃范围内的温度下形成。在一些实施例中，通过包括在从约25℃至400℃的温度范围内的溅射的物理汽相沉积来形成半导体层25。
在一些实施例中，牺牲层20由与半导体层25不同的材料制成，使得牺牲层20在随后的工艺中相对于半导体层25被选择性地去除。在一些实施例中，牺牲层25由一个或多个绝缘材料层制成，绝缘材料诸如氧化硅、氮化硅、氮氧化硅、SiOC、氧化铝、氧化铪或任何其它合适的绝缘材料。在一些实施例中，牺牲层25由一个或多个半导体材料层制成，半导体材料诸如Si、SiGe和Ge。在一些实施例中，半导体层是非晶或多晶的。在其它实施例中，牺牲层25由一个或多个金属材料层制成，金属材料诸如包括TiN和TaN的金属氮化物。
在一些实施例中，半导体层25的厚度在从约5nm至约30nm的范围内，并且在其它实施例中在从约10nm至约20nm的范围内。在一些实施例中，牺牲层20的厚度在从约5nm至约30nm的范围内，并且在其它实施例中在从约10nm至约20nm的范围内。在一些实施例中，半导体层25的厚度等于牺牲层20的厚度，并且在其它实施例中，半导体层25的厚度大于或小于牺牲层20的厚度。
尽管示出了四个半导体层25和五个牺牲层20，但是在一些实施例中，每个形成多达20层。在一些实施例中，半导体层和牺牲层的每个的层的数量在从4至10层的范围内。在一些实施例中，牺牲层20直接形成在第一ILD层10上，并且交替堆叠的最上层是牺牲层20。在其它实施例中，交替堆叠件的最上层是半导体层25。
图8A和图8B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。在一些实施例中，半导体层25和牺牲层20的交替堆叠件被图案化为鳍结构22。
鳍结构22可以通过任何合适的方法来图案化。例如，可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺来图案化该结构。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，从而允许创建具有例如间距小于使用单个直接光刻工艺可获得的间距的图案。例如，在实施例中，在衬底上方形成牺牲层(芯轴图案)，并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层(芯轴图案)，然后可以使用剩余的间隔件来图案化鳍结构22。
尽管在图8B中示出了五个鳍结构22，但是用于一个TFT的鳍结构的数量不限于五个。在一些实施例中，取决于驱动电流要求，每个TFT的鳍结构的数量在从1至10的范围内，而在其它实施例中在从2至5的范围内。鳍结构25的宽度在一些实施例中在从约10nm至约50nm的范围内，并且在其它实施例中在从约15nm至约30nm的范围内。
图9A和图9B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。在一些实施例中，如图9A所示，在鳍结构22和ILD层20上方形成牺牲栅极介电层42。在一些实施例中，牺牲栅极介电层42由绝缘材料制成，诸如氧化硅、氮化硅、氮氧化硅、SiOC、氧化铝、氧化铪或任何其它合适的绝缘材料。在其它实施例中，不形成牺牲栅极介电层。
图10A和图10B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。然后，如图10A和图10B所示，形成用于栅极替换技术的牺牲栅极结构40。在一些实施例中，牺牲栅极结构包括牺牲栅电极层44和硬掩模层46。在一些实施例中，牺牲栅电极层44是多晶或非晶Si、SiGe或Ge。牺牲栅电极层44通过化学汽相沉积(CVD)或任何其它合适的成膜方法形成，并且硬掩模层46形成在牺牲栅电极层44上方。在一些实施例中，硬掩模层46由基于氮化硅的材料制成，诸如氮化硅、SiON或SiCN，或者由基于氧化硅的材料制成，诸如氧化硅。在形成硬掩模层46之后，通过使用一种或多种光刻和蚀刻操作，图案化硬掩模层46。然后，通过使用图案化的硬掩模层46作为蚀刻掩模，图案化沉积的牺牲栅电极层44。在一些实施例中，形成一个或多个用于抑制工艺变化和/或改善图案保真度的伪栅极结构，以围绕用于功能晶体管的牺牲栅极结构。
图11A和图11B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。随后，如图11A和图11B所示，在牺牲栅极结构40的侧面上形成栅极侧壁间隔件48。通过使用CVD或其它合适的方法共形地形成用于第一侧壁间隔件的绝缘材料的覆盖层。覆盖层以共形的方式沉积，使得其形成为在牺牲栅极结构40的垂直表面(诸如侧壁)、水平表面和顶部上具有基本相等的厚度。在一些实施例中，覆盖层被沉积至从约2nm至约30nm范围内的厚度。在一实施例中，覆盖层的绝缘材料不同于牺牲栅极结构的材料，并且由基于氮化硅的材料制成，诸如氮化硅、SiON、SiOCN或SiCN以及它们的组合。在一些实施例中，覆盖层由氮化硅制成。侧壁间隔件通过各向异性蚀刻形成在牺牲栅极结构的相对侧面上。在一些实施例中，栅极侧壁间隔件48形成在硬掩模层46的相对侧面上。在一些实施例中，侧壁间隔件形成在鳍结构22的侧面上。
图12A和图12B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。然后，如图12A和图12B所示，去除牺牲栅极介电层42，并且暴露鳍结构22。如图12A所示，牺牲栅极介电层42保留在牺牲栅极结构40和栅极侧壁间隔件48下方。
图13A和图13B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。然后，如图13A和图13B所示，在牺牲栅极结构40和鳍结构22上方形成第二ILD层50。用于第二ILD层50的材料包括包含Si、O、C和/或H的化合物，诸如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于第二ILD层50。在一些实施例中，第二ILD层50由与第一ILD层10相同的材料制成。在形成第二ILD层50之后，如图13A和图13B所示，实施诸如CMP的平坦化操作，使得牺牲栅电极层44的顶部暴露。
图14A和图14B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。随后，如图14A和图14B所示，去除牺牲栅电极层44和牺牲栅极介电层42，从而形成栅极间隔52。可以使用等离子体干蚀刻和/或湿蚀刻来去除牺牲栅电极层44。在一些实施例中，当牺牲栅电极层44由多晶或非晶硅制成时，氢氧化四甲铵溶液(TMAH)用作湿蚀刻剂。牺牲栅极介电层42也通过合适的湿/干蚀刻去除。
此外，如图14A和图14B所示，也去除了栅极间隔52下方的牺牲层20。当牺牲层20和牺牲栅极介电层42由相同或相似的材料制成时，牺牲栅极介电层42的去除操作(例如，湿蚀刻)也去除了牺牲层20。当牺牲层20和牺牲栅极介电层42由彼此不同的材料制成时，实施两个或更多个蚀刻操作以顺序去除牺牲栅极介电层42和牺牲层20。通过去除牺牲层20，半导体层25的沟道区域在栅极间隔52中释放为半导体纳米片。
图15A和图15B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。然后，如图15A和图15B所示，在栅极间隔52中形成栅极介电层82和栅电极层80。在一些实施例中，栅极介电层82包括一个或多个介电材料层，诸如氧化硅、氮化硅或高k介电材料、其它合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料、和/或它们的组合。在一些实施例中，栅极介电层82包括形成在沟道区域和介电材料之间的界面层。可以通过CVD、ALD或任何合适的方法来形成栅极介电层82。在实施例中，使用诸如ALD的高度共形沉积工艺来形成栅极介电层82，以确保在每个沟道区域周围形成具有均匀厚度的栅极介电层。栅极介电层82的厚度在一些实施例中在从约1nm至约20nm的范围内，并且在其它实施例中在从约2nm至约10nm的范围内。
在一些实施例中，金属栅电极层80包括一个或多个功函调整层84和体金属栅电极层86。功函调整层由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层的导电材料制成，或这些材料的两种或多种的多层制成。功函调整层可以通过ALD、PVD、CVD、电子束蒸发或其它合适的工艺形成。此外，功函调整层84可以相对于nFET和pFET分别形成，其可以使用不同的金属层。体栅电极层形成为围绕每个氧化物半导体纳米片(沟道区域)。体栅电极层包括一个或多个导电材料层，导电材料诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合。可以通过CVD、ALD、电镀或其它合适的方法来形成体栅电极层。栅极介电层82和栅电极层80的金属也沉积在第二ILD层50的上表面上方。然后，通过使用例如CMP来平坦化形成在第二ILD层50上方的栅电极层80的材料，直至露出第二ILD层50的顶面，如图15A和图15B所示。在一些实施例中，在平坦化操作之后，使金属栅电极层凹进并且在凹进的栅电极层上方形成覆盖绝缘层(未示出)。覆盖绝缘层包括一个或多个基于氮化硅的材料层，诸如氮化硅。可以通过沉积绝缘材料然后进行平坦化操作来形成覆盖绝缘层。
图16A和图16B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。此外，如图16A和图16B所示，在第二ILD层50上方形成第三ILD层60，并且在第三ILD层和第二ILD层中形成用于源极/漏极接触的接触孔65。用于第三ILD层60的材料包括包含Si、O、C和/或H的化合物，诸如氧化硅、SiCOH和SiOC。诸如聚合物的有机材料可以用于第三ILD层60。在一些实施例中，第三ILD层60由与第二ILD层和/或第一ILD层10相同的材料制成。在一些实施例中，第三ILD层60用作用于蚀刻第二ILD层的硬掩模层。
图17A和图17B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。在形成接触孔65之后，去除接触孔65下方的牺牲层20，从而释放半导体层20的源极/漏极区域，如图17A所示。
在一些实施例中，部分牺牲层20保留为内部间隔件21。在一些实施例中，当牺牲层20保留为内部间隔件21时，牺牲层20由绝缘材料制成。在其它实施例中，牺牲层20被完全去除。
图18A至图20B是根据本发明的实施例的制造半导体器件的顺序步骤的示意图。图18A示出了沿源极至漏极方向(Y方向)截取的截面，图19A示出了沿着栅电极的栅极延伸方向(X方向)截取的截面，并且图20A是沿源极/漏极接触件的X方向截取的截面图。
如图18A至图20B所示，在接触孔65中形成源极/漏极接触件70。在接触孔内和接触孔上方形成一个或多个导电材料层，然后实施诸如CMP操作的平坦化操作以形成导电接触件70。在一些实施例中，源极/漏极接触件70包括如图4所示的衬垫或阻挡层72和体接触件层74。在一些实施例中，衬垫层72由Ti、TiN、Ta和TaN中的一种或多种制成，并且体接触件层74由W、Cu、Ti、Ag、Al、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr中的一种或多种制成。如图20A所示，至少衬垫层72包裹半导体层(纳米片)25的源极/漏极区域。在其它实施例中，体接触件层74也包裹源极/漏极区域。
应该理解，TFT经过进一步的工艺以形成各个部件，诸如接触件/通孔、互连金属层、介电层、钝化层等。
图21A至图22B示出了根据本发明的另一实施例的用于制造半导体器件的顺序操作。应该理解，对于该方法的其它实施例，可以在图21A至图22B所示的过程之前、期间和之后提供附加的工艺，并且可以替换或消除以下描述的一些操作。图21A至图22B所示的制造操作对应于图5所示的TFT结构。
在形成用于源极/漏极接触的接触孔65之后，如图21A和图21B所示，去除接触孔65中的半导体层25和牺牲层20。然后，类似于图20A和图20B，形成源极/漏极接触件70，如图22A和图22B所示。
图23示出了根据本发明实施例的半导体器件的截面图。如图23所示，在衬底上方形成有下层器件100。下层器件100包括一个或多个鳍式场效应晶体管(FinFET)、全环栅FET(GAA FET)、平面FET、垂直FET或任何其它电子器件。图23还示出了设置在下层器件100上方的上层器件200。在一些实施例中，一个或多个ILD层、金属布线层和/或通孔接触件设置在下层器件100和上层器件200之间。在一些实施例中，上层器件200包括通过本发明的以上实施例制造的一个或多个TFT。
在本实施例中，由于通过使用诸如IGZO的氧化物半导体形成了用于将电源从主电源(VDD或VSS)切换至局部电源(VVDD或VVSS)的电源切换电路和电源布线。因此，可以在BEOL电路电平提供电源开关电路。
应该理解，不是所有的优势都有必要在此处讨论，没有特定的优势对所有实施例都是需要的，并且其它是实施例可以提供不同的优势。
根据本发明的方面，在制造半导体器件的方法中，形成包括半导体层和牺牲层交替堆叠的堆叠件结构，在堆叠件结构上方形成牺牲栅极结构，在牺牲栅极结构上方形成介电层，牺牲栅极结构被去除，从而形成栅极间隔，在栅极间隔中去除牺牲层，从而释放出半导体层，形成包裹半导体层的栅极结构。半导体层由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，牺牲层包括选自由绝缘材料，非晶或多晶半导体材料和金属氮化物材料组成的组中的一种。在以上和/或以下的一个或多个实施例中，堆叠件结构形成在绝缘材料层上。在以上和/或以下的一个或多个实施例中，绝缘材料层覆盖形成在半导体衬底上方的晶体管。在以上和/或以下的一个或多个实施例中，通过在绝缘材料层上交替地形成半导体层和牺牲层，并且将半导体层和牺牲层图案化为一个或多个鳍结构来形成堆叠件结构。
根据本发明的另一方面，在制造半导体器件的方法中，在第一介电层上方形成包括交替堆叠的半导体层和牺牲层的鳍结构，在鳍状结构上方形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成栅极侧壁间隔件，在牺牲栅极结构和鳍结构上方形成第二介电层，去除牺牲栅极结构，从而形成栅极间隔，在栅极间隔中去除牺牲层，从而释放出半导体层的沟道区域，形成包裹半导体层的沟道区域的栅极结构，形成第三介电层，在第三介电层和第二介电层中形成接触开口，在接触开口中去除牺牲层，从而释放出半导体层的源极/漏极区域，并且形成包裹半导体层的源极/漏极区域的源极/漏极接触件。半导体层由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，牺牲层包括选自由氧化硅、氮化硅、氮氧化硅、SiOC、氧化铝、氧化铪组成的组中的一种。在以上和/或以下的一个或多个实施例中，牺牲层包括选自由非晶或多晶Si、SiGe和Ge组成的组中的一种。在以上和/或以下的一个或多个实施例中，牺牲层包括选自由TiN和TaN组成的组中的一种。在以上和/或以下的一个或多个实施例中，第一介电层覆盖形成在半导体衬底上方的晶体管。在以上和/或以下的一个或多个实施例中，在去除接触开口中的牺牲层时，保留部分牺牲层，并且在形成源极/漏极接触件之后，将牺牲层的其余部分设置在源极/漏极接触件和栅极结构之间。
根据本发明的另一方面，在制造半导体器件的方法中，在第一介电层上方形成包括交替堆叠的半导体层和牺牲层的鳍结构，在鳍状结构上方形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成栅极侧壁间隔件，在牺牲栅极结构和鳍结构上方形成第二介电层，牺牲栅极结构被去除，从而形成栅极间隔，在栅极间隔中去除牺牲层，从而释放出半导体层的沟道区域，形成包裹半导体层的沟道区域的栅极结构，形成第三介电层，在第三介电层和第二介电层中形成接触开口，在接触开口中去除牺牲层和半导体层，并且在接触开口中形成源极/漏极接触件。半导体层由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，牺牲层包括选自由氧化硅、氮化硅、氮氧化硅、SiOC、氧化铝、氧化铪组成的组中的一种。在以上和/或以下的一个或多个实施例中，在去除接触开口中的牺牲层时，保留部分牺牲层，并且在形成源极/漏极接触件之后，将牺牲层的其余部分设置在源极/漏极接触件和栅极结构之间。
根据本发明的方面，半导体器件包括电源开关电路和逻辑电路。半导体器件包括第一介电层和形成在第一介电层上的薄膜晶体管(TFT)。TFT包括半导体纳米片、包裹半导体纳米片的沟道区域的栅极介电层，以及形成在栅极介电层上的栅电极层。半导体纳米片由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，半导体纳米片的厚度T1在从5nm至30nm的范围内，并且每个半导体纳米片的沿栅极延伸方向的宽度W1在10nm至50nm的范围内。在以上和/或以下的一个或多个实施例中，比率W1/T1在从1.2至10的范围内。
根据本发明的另一方面，半导体器件包括电源开关电路和逻辑电路。功率开关电路包括第一介电层和形成在第一介电层上的薄膜晶体管(TFT)。TFT包括垂直布置的半导体纳米片、包裹每个半导体纳米片的沟道区域的栅极介电层，以及形成在栅极介电层上的栅电极层。半导体纳米片由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，每个半导体纳米片的厚度T1在从5nm至30nm的范围内，并且每个半导体纳米片的沿栅极延伸方向的宽度W1在从10nm至50nm的范围内。在以上和/或以下的一个或多个实施例中，比率W1/T1在从2至5的范围内。在以上和/或以下的一个或多个实施例中，半导体纳米片的数量在从2至10的范围内。在以上和/或以下的一个或多个实施例中，TFT还包括包裹每个半导体纳米片的源极/漏极区域的源极/漏极接触件。在以上和/或以下的一个或多个实施例中，TFT还包括设置在源极/漏极接触件和栅电极层之间的内部间隔件。在以上和/或以下的一个或多个实施例中，TFT还包括与半导体纳米片的端面接触的源极/漏极接触件。在以上和/或以下的一个或多个实施例中，TFT还包括设置在源极/漏极接触件和栅电极层之间的内部间隔件。
根据本发明的另一方面，半导体器件包括电源开关电路和逻辑电路，并且该半导体器件包括第一介电层和形成在第一介电层上的薄膜晶体管(TFT)。该TFT包括多组半导体纳米片，其中该半导体纳米片垂直地布置在每一个该多个组中，包裹多个半导体纳米片组中的每个半导体纳米片的沟道区域的栅极介电层，栅电极层形成在多个半导体纳米片组上的栅极介电层上方。半导体纳米片由氧化物半导体材料制成。在以上和/或以下的一个或多个实施例中，氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。在以上和/或以下的一个或多个实施例中，每个半导体纳米片的厚度T1在从5nm至30nm的范围内，并且每个半导体纳米片的沿栅极延伸方向的宽度W1在从10nm至50nm的范围内。在以上和/或以下的一个或多个实施例中，半导体纳米片的数量在从2至10的范围内。在以上和/或以下的一个或多个实施例中，多个基团的数量在从2至5的范围内。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，包括：
形成包括交替堆叠的半导体层和牺牲层的堆叠件结构；
在所述堆叠件结构上方形成牺牲栅极结构；
在所述牺牲栅极结构上方形成介电层；
去除所述牺牲栅极结构，从而形成栅极间隔；
去除所述栅极间隔中的所述牺牲层，从而释放所述半导体层；以及
形成包裹所述半导体层的栅极结构，
其中，所述半导体层由氧化物半导体材料制成。
2.根据权利要求1所述的方法，其中，所述氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。
3.根据权利要求1所述的方法，其中，所述氧化物半导体材料包括非晶铟镓锌氧化物(IGZO)。
4.根据权利要求1所述的方法，其中，所述牺牲层包括选自由绝缘材料、非晶或多晶半导体材料以及金属氮化物材料组成的组中的一种。
5.根据权利要求2所述的方法，其中，所述堆叠件结构形成在绝缘材料层上方。
6.根据权利要求5所述的方法，其中，所述绝缘材料层覆盖形成在半导体衬底上方的晶体管。
7.根据权利要求1所述的方法，其中，所述堆叠件结构通过以下方式形成：
在绝缘材料层上交替形成所述半导体层和所述牺牲层；以及
将所述半导体层和所述牺牲层图案化为一个或多个鳍结构。
8.一种制造半导体器件的方法，包括：
在第一介电层上方形成包括交替堆叠的半导体层和牺牲层的鳍结构；
在所述鳍结构上方形成牺牲栅极结构；
在所述牺牲栅极结构的相对侧面上形成栅极侧壁间隔件；
在所述牺牲栅极结构和所述鳍结构上方形成第二介电层；
去除所述牺牲栅极结构，从而形成栅极间隔；
去除所述栅极间隔中的所述牺牲层，从而释放所述半导体层的沟道区域；
形成包裹所述半导体层的所述沟道区域的栅极结构；
形成第三介电层；
在所述第三介电层和所述第二介电层中形成接触开口；
去除所述接触开口中的所述牺牲层，从而释放所述半导体层的源极/漏极区域；以及
形成包裹所述半导体层的所述源极/漏极区域的源极/漏极接触件，
其中，所述半导体层由氧化物半导体材料制成。
9.根据权利要求8所述的方法，其中，所述氧化物半导体材料包括选自由铟镓锌氧化物(IGZO)、c轴取向晶体(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON组成的组中的一种。
10.一种包括电源开关电路和逻辑电路的半导体器件，该电源开关电路包括：
第一介电层；
薄膜晶体管(TFT)，形成在所述第一介电层上，其中：
所述薄膜晶体管包括：
垂直布置的半导体纳米片；
栅极介电层，包裹每个所述半导体纳米片的沟道区域；
栅电极层，形成在所述栅极介电层上，
其中，所述半导体纳米片由氧化物半导体材料制成。
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