TWI787553B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI787553B
TWI787553B TW108139131A TW108139131A TWI787553B TW I787553 B TWI787553 B TW I787553B TW 108139131 A TW108139131 A TW 108139131A TW 108139131 A TW108139131 A TW 108139131A TW I787553 B TWI787553 B TW I787553B
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semiconductor
layer
dielectric layer
sacrificial
gate
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TW108139131A
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TW202025498A (zh
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范達爾 馬庫斯瓊斯亨利庫斯
朵爾伯斯 荷爾本
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件包括功率開關電路和邏輯電路。半導體元件包括第一介電質層和形成在該第一介電質層上的薄膜電晶體。薄膜電晶體包括半導體奈米層片、包裹在該半導體奈米層片的通道區周圍的閘極介電質層,以及形成在該閘極介電質層上的閘電極層。該半導體奈米層片由氧化物半導體材料製成。

Description

半導體元件及其製造方法
本揭示是關於一種半導體元件及其製造方法。
隨著半導體元件的大小變小,標準單元的單元高度也變小。單元高度通常被定義為兩條供電線路VDD和VSS之間的週期性距離(節距),並且通常由鰭結構及/或金屬線的數量和節距確定。單元高度也稱為軌道高度。典型的軌道高度是7.5T、6.5T或5.5T,其中T是在標準單元上運行的金屬線的最小節距。當前需要按比例縮小到4.5T或4T,以進一步減小半導體元件的大小。
根據本揭示的一態樣,在一種製造半導體元件的方法中,形成包括交替堆疊的半導體層和犧牲層的堆疊結構,在堆疊結構上形成犧牲閘極結構,在犧牲閘極結構上形成介電質層,移除犧牲閘極結構,從而形成閘極空間,在閘極空間中移除犧牲層,從而釋放半導體層,形成包裹在半導體層周圍的閘極結構。半導體層由氧化物半導體材料製成。
在一種製造半導體元件的方法中,在第一介電質層上形成包括交替堆疊的半導體層和犧牲層的鰭結構,在鰭結構上形成犧牲閘極結構,在犧牲閘極結構的相對側面上形成閘極側壁間隔物,在犧牲閘極結構和鰭結構上形成第二介電質層,移除犧牲閘極結構,從而形成閘極空間,在閘極空間中移除犧牲層,從而釋放半導體層的通道區,形成包裹在半導體層的通道區周圍的閘極結構,形成第三介電質層,在第三介電質層和第二介電質層中形成接觸開口,在接觸開口中移除犧牲層,從而釋放半導體層的源極/汲極區,並且形成包裹半導體層的該些源極/汲極區的源極/汲極觸點。半導體層由氧化物半導體材料製成。
一種半導體元件包括功率開關電路和邏輯電路。功率開關電路包括第一介電質層和形成在第一介電質層上的薄膜電晶體。薄膜電晶體包括豎直佈置的半導體奈米層片、包裹在半導體奈米層片的通道區周圍的閘極介電質層,以及形成在閘極介電質層上的閘電極層。半導體奈米層片由氧化物半導體材料製成。
5:基板
10:第一ILD層
20:犧牲層
21:內部間隔物
22:鰭結構
25:氧化物半導體奈米層片/半導體層
40:犧牲閘極結構
42:犧牲閘極介電質層
44:犧牲閘電極層
46:硬掩模層
48:閘極側壁間隔物
50:第二ILD層
52:閘極空間
60:第三ILD層
65:接觸孔
70:源極/汲極觸點
72:襯墊層/阻擋層
74:體接觸層
80:金屬閘電極
82:閘極介電質層
84:功函數調節層
86:體金屬閘電極
100:下層元件
200:上層元件
當結合附圖閱讀時,從以下詳細描述可以最好地理解本揭露的各態樣。應注意,根據行業中的標準實踐,各種特徵未按比例繪製。實際上,為了論述的清楚性,可以任意地增大或縮小各種特徵的尺寸。
第1圖圖示根據本揭示的一實施例的半導體元件的電路圖。
第2圖圖示根據本揭示的一實施例的半導體元件的剖視圖。
第3圖圖示根據本揭示的一實施例的半導體元件的剖視圖。
第4圖圖示根據本揭示的一實施例的半導體元件的剖視圖。
第5圖圖示根據本揭示的一實施例的半導體元件的剖視圖。
第6A圖和第6B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第6A圖是立體視圖,並且第6B圖是平面圖。
第7A圖和第7B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第7A圖是立體視圖,並且第7B圖是平面圖。
第8A圖和第8B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第8A圖是立體視圖,並且第8B圖是平面圖。
第9A圖和第9B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第9A圖是立體視圖,並且第9B圖是平面圖。
第10A圖和第10B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第10A圖是立體視圖,並且第10B圖是平面圖。
第11A圖和第11B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第11A圖是立體視圖,並且第11B圖是平面圖。
第12A圖和第12B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第12A圖是立體視圖,並且第12B圖是平面圖。
第13A圖和第13B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第13A圖是立體視圖,並且第13B圖是平面圖。
第14A圖和第14B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第14A圖是立體視圖,並且第14B圖是平面圖。
第15A圖和第15B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第15A圖是立體視圖,並且第15B圖是平面圖。
第16A圖和第16B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第16A圖是立體視圖,並且第16B圖是平面圖。
第17A圖和第17B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第17A圖是立體視圖,並且第17B圖是平面圖。
第18A圖和第18B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第18A圖是立體視圖,並且第18B圖是平面圖。
第19A圖和第19B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第19A圖是立體視圖,並且第19B圖是平面圖。
第20A圖和第20B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第20A圖是立體視圖,並且第20B圖是平面圖。
第21A圖和第21B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第21A圖是立體視圖,並且第21B圖是平面圖。
第22A圖和第22B圖是根據本揭示的一實施例的製造半導體元件的順序過程的示意圖。第22A圖是立體視圖,並且第22B圖是平面圖。
第23圖圖示根據本揭示的一實施例的半導體FET元件的剖視圖。
應當理解,以下揭露內容提供了用於實施本揭示的不同特徵的許多不同實施例或實例。以下描述了部件和佈置的特定實施例或實例以簡化本揭示內容。當然,該些僅僅是實例,而並且意欲為限制性的。例如,元件的尺寸不限於所揭示的範圍或值,而是可取決於元件的處理條件及/或所需特性。 此外,在以下描述中在第二特徵上方或之上形成第一特徵可以包括第一特徵和第二特徵形成為直接接觸的實施例,並且亦可以包括可以形成插置第一特徵與第二特徵的額外特徵,使得第一特徵和第二特徵可以不直接接觸的實施例。為了簡單和清楚起見,可以以不同比例任意繪示各種特徵。在附圖中,為了簡化,可以省略一些層/特徵。
此外,在此可以使用空間相對術語,諸如「下方」、「以下」、「下部」、「上方」、「上部」等來簡化描述,以描述如圖中所示的一個元件或特徵與另一元件或特徵的關係。除了圖中所示的取向之外,空間相對術語旨在包括使用或操作中的裝置/元件的不同取向。裝置可以以其他方式取向(旋轉90度或在其他方向上),並且可以類似地相應解釋在此使用的空間相對描述詞。另外,術語「由...製成」可以表示「包含」或「由......組成」。此外,在以下製造製程中,在所描述的操作之間可以有一或多個額外操作,並且可以改變操作的順序。在以下實施例中,術語「上部」、「在……上方」及/或「在……上面」是沿著與前表面和後表面的距離增加的方向定義的。關於一個實施例描述的材料、配置、尺寸、處理及/或操作可以在其他實施例中採用,並且可以省略關於其的詳細描述。
對於用於高速操作的半導體元件及/或用於行動終端的半導體元件,諸如積體電路(IC)等半導體元件中的功耗最小化是關鍵問題。已經提出了各種用於降低功耗的技術,但是由於用於控制功率的額外電路,其中許多技術需要更大的晶片面積。一種此類技術包括提供虛擬供電線路(VVDD及/或 VVSS),以及在主供電線路(VDD及/或VSS)與該虛擬供電線路之間的頭開關(header switch)及/或腳開關(footer switch)。虛擬供電線路可以稱為本端供電線路,而主供電線路可以稱為全局供電線路。應注意,VDD通常處於比VSS更高的電勢(電壓)下,並且在一些實施例中,VSS耦合到接地(0V)。藉由關斷(斷開)與半導體元件中的非有源功能電路耦合的頭/腳開關,來降低功耗。
第1圖圖示根據本揭示的一實施例的半導體元件的電路圖。如第1圖所示,p型MOS FET用作頭開關並且n型MOS FET用作腳開關,以切斷通向本端VVDD的電力供應,該本端VVDD進一步向包括一或多個標準單元在內的區塊供應電力,每個區塊均包括功能電路(例如,CMOS反相器)。在一些實施例中,不使用腳開關,並且標準單元直接耦合到VSS。在一些實施例中,如第1圖所示,第一主供電線路VDD耦合到VDD生成電路(Vdd源),該VDD生成電路生成諸如0.5V、0.8V、1.0V、1.2V、1.8V、2.4V、3.3V或5.0V的電壓。在一些實施例中,第二主供電線路VSS耦合到VSS生成電路(VSS源),該VSS生成電路生成低於VDD的電壓,或接地。如第1圖所示,本端供電線路VVDD被分成複數個本端供電線路(local power supply lines),一或多個標準單元(standard cell,STDC)連接至各個本端供電線路,以作為單元區塊。因此,可以逐區塊地控制對標準單元的電力供應。此外,在一些實施例中,標準單元包括內部供電線路(匯流排線 路)INT,並且本端供電線路VVDD使用或不使用開關耦合到內部供電線路。
在本揭示的實施例中,在半導體元件中功率開關電路(頭開關及/或腳開關)從前段製程(front end of the line,FEOL)電路級移動到後段製程(back end of the line,BEOL)電路級,以實現元件尺寸的縮減,如第2圖所示。FEOL電路級包括形成在半導體基板上的MOS電晶體。MOS電晶體包括平面場效電晶體(field effect transistors,FET)、鰭式FET及/或環繞式閘極(gate-all-around,GAA)FET。在一些實施例中,FEOL電路級亦包括局部互連件。BEOL電路級包括金屬佈線結構,該金屬佈線結構包括一或多個介電質層、金屬佈線和嵌入在該些介電質層中的通孔。將功率開關電路從FEOL電路級移動到BEOL電路級中的佈線層允許將元件面積減少約10%。將功率開關電路放置在BEOL電路級中需要使用的通孔更少,從而為邏輯區塊騰出了更多的佈線空間,從而增大了邏輯區塊中的元件密度。使用非結晶半導體的TFT適用於後段製程,因為非結晶半導體通常可以在低溫(例如低於450℃)下形成。
在一些實施例中,如第2圖所示,功率開關電路包括薄膜電晶體(TFT),因為TFT的製造操作通常不需要高溫來形成例如磊晶半導體溝道,並且適合於BEOL電路級。如第2圖所示,功率開關電路被置於例如M1-M2級、M4-M5級或M8-M9級中。
在本揭示的一些實施例中,TFT的通道區包括氧化物半導體,諸如非晶銦鎵鋅氧化物(IGZO)、c軸對準的結晶(c-axis aligned crystal,CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。
功率開關電路的電晶體通常需要低導通電阻Ron=Vds/Id。例如,IGZO提供了極低的截止電流Ioff(低洩漏電流),並且IGZO TFT具有大的Ion/Ioff比。然而,由於非結晶IGZO(a-IGZO)具有低電子遷移率(約15cm2Vs),所以由a-IGZO製成的單層平面TFT應不足以滿足功率開關電路所需的Ron值。
為了補償該特性,在一些實施例中增大溝道寬度Weff以提供低Ron>Reh=Lg/(Weff遷移率Cox(Vg-Vt)),因為通常Cox不能由於閘極電流約束而增大並且Vg-Vt由電源電壓設定。在本揭示的實施例中,提供多個堆疊的奈米層片環繞式閘極氧化物半導體元件結構和相應的製程流以增大每佔地面積的有效寬度,以便減小Ron而不損害Ion/Ioff比。使用如IGZO等的氧化物半導體的益處包括低洩漏電流、合理的電子遷移率和高可靠性。
第3圖是在半導體元件的氧化物半導體奈米層片上切開的示意性剖視圖(X-Z平面),並且第4圖是根據本揭示的一實施例在半導體元件的閘電極上切開的示意性剖視圖(Y-Z平面)。
在一些實施例中,半導體元件是如第3圖和第4圖所示的環繞式閘極(GAA)FET。在一些實施例中,氧化物半 導體奈米層片25在Y方向(源極至汲極方向)上延伸並且沿著Z方向(豎直方向)堆疊。儘管在第3圖和第4圖中圖示了四個氧化物半導體奈米層片(oxide semiconductor nano-sheet)25,但是取決於所需電流,氧化物半導體奈米層片25的數量可以少至2個及多個20個。在一些實施方式中,氧化物半導體奈米層片25的數量範圍為4至10個。取決於所需的電流及/或製造製程條件,氧化物半導體奈米層片25的寬度W1在一些實施例中在約10nm至約50nm的範圍內,並且在其他實施例中在約15nm至約30nm的範圍內。取決於所需的電流及/或製造製程條件,氧化物半導體奈米層片25的厚度T1在一些實施例中範圍為約5nm至約30nm,並且在其他實施例中範圍為約10nm至約20nm。在一些實施例中,W1>T1。深寬比W1/T1在一些實施例中範圍為約1.2至約10,並且在其他實施例中範圍為約2至約5。取決於所需的電流及/或製造製程條件,相鄰氧化物半導體奈米層片25之間的間隔S1在一些實施例中範圍為約5nm至約30nm,並且在其他實施例中範圍為約10nm至約20nm。在一些實施例中S1
Figure 108139131-A0305-02-0012-1
T1,並且在其他實施例中S1<T1。如果間隔S1太窄,則將難以均勻地形成要包裹在氧化物半導體奈米層片25周圍的層(例如,閘極介電質層和閘電極層)。
閘極介電質層82包裹在每個氧化物半導體奈米層片25周圍。在一些實施例中,閘極介電質層82是高介電常數介電材料,諸如氮化矽、HfO2、La2O3、ZrO2、BaO、TiO2、Ta2O5、SrO、Y2O3、HfSiO4、ZrSiO4、Al2O3、MgO、CaO、其他合適的高介電常數介電材料,及/或其組合。在一些實施 例中,閘極介電質層82的厚度範圍為約2nm至約20nm。閘極介電質層82可以由化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atom layer deposition,ALD)或任何合適的方法形成。在一個實施例中,使用諸如ALD等高度共形沉積製程來形成閘極介電質層82,以確保在每個氧化物半導體奈米層片25周圍形成具有均勻厚度的閘極介電質層82。
在閘極介電質層82上形成金屬閘電極80,以包裹在每個氧化物半導體奈米層片25周圍。在一些實施例中,金屬閘電極80包括多個導電層。在一些實施例中,金屬閘電極80包括一或多個功函數調節層84和體金屬閘電極86。功函數調節層84由導電材料製成,該導電材料為諸如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC,或多層的該些材料中的兩種或更多種材料。功函數調節層84可藉由ALD、物理氣相沉積(physical vapor deposition,PVD)、CVD、電子束蒸鍍或其他合適的製程來形成。此外,功函數調節層84可以被單獨地形成以用於該nFET和該pFET,該nFET和該pFET可以使用不同的金屬層。體金屬閘電極86形成為圍繞每個氧化物半導體奈米層片25(通道區)。體金屬閘電極86包括一層或多層導電材料,諸如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適的材料,和/或其組合。體金屬閘電極86可以由CVD、ALD、電鍍或其他合適的方法形成。
如第3圖所示,在閘極側壁間隔物48之間設置包括閘極介電質層82和金屬閘電極80的閘極結構,並且如第3圖所示進一步設置了層間介電質(interlayer dielectric,ILD)層50。
在一些實施例中,內部間隔物21設置金屬閘電極80與源極/汲極觸點70之間,如第4圖所示。內部間隔物21是犧牲層20的剩餘部分,如下所述。
氧化物半導體奈米層片25亦具有如第4圖所示的源極/汲極區。源極/汲極觸點70形成為與每個氧化物半導體奈米層片25的源極/汲極區接觸並包裹在該源極/汲極區周圍。在一些實施例中,源極/汲極觸點70具有多層結構。在一些實施例中,源極/汲極觸點70包括襯墊層或阻擋層72以及體接觸層74,如第4圖所示。在一些實施例中,襯墊層72由Ti、TiN、Ta和TaN中的一或多種製成,並且體接觸層74由W、Cu、Ti、Ag、Al、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr中的一或多種製成。
在一些實施例中,氧化物半導體奈米層片25穿過源極/汲極觸點70到達ILD層50,如第4圖所示。在其他實施例中,氧化物半導體奈米層片25的端部定位於源極/汲極觸點70中。
第5圖是根據本揭示的另一實施例的在半導體元件的閘電極上切開的示意性剖視圖(Y-Z平面)。
在該實施例中,氧化物半導體奈米層片25不穿透入或穿過源極/汲極觸點70。如第5圖所示,源極/汲極觸點70覆蓋氧化物半導體奈米層片25的端面。
第6A圖至第20B圖示了根據本揭示的一實施例的用於製造半導體元件的順序操作。應當理解,對於該方法的其他實施例,可以在第6A圖至第20B圖所示的製程之前、期間和之後提供額外的操作,並且下面描述的一些操作可以被替換或者省略。操作/製程的順序可以是可互換的。「A」圖圖示立體視圖,並且「B」圖圖示平面圖(俯視圖)。
第6A圖和第6B圖是根據本揭示的一實施例的半導體元件的順序製造操作的各階段之一的示意圖。如第6A圖所示,提供基板5。在一些實施例中,基板5在至少其表面部分上包括單一結晶半導體層。基板5可包含單一結晶半導體材料,諸如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在某些實施例中,基板5由結晶Si、SiGe或Ge製成。在一些實施例中基板5可在其表面區域中包括一或多個緩衝層(未圖示)。緩衝層可以用來將晶格常數從基板的晶格常數逐漸改變為源極/汲極區的晶格常數。緩衝層可以由磊晶生長的單一結晶半導體材料形成,所述單一結晶半導體材料為諸如但不限於Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP,以及InP。在一特定實施例中,基板5包括在矽基板上磊晶生長的矽鍺(SiGe)緩衝層。SiGe緩衝層 的鍺濃度可以從最底部緩衝層的30原子%的鍺增大到最頂部緩衝層的70原子%的鍺。
此外,如第6A圖所示,在基板5上形成一或多個第一層間介電質(ILD)層10。在一些實施例中,在基板5上形成諸如電晶體(例如,FET)、記憶體(例如,隨機存取記憶體(DRAM)、靜態RAM、磁性MRAM及/或相變RAM)的一或多個電子元件,並且一或多個第一ILD層10覆蓋該些電子元件。
在一些實施例中,在第一ILD層10中嵌入一或多個金屬佈線結構。用於第一ILD層10的介電質材料包括藉由LPCVD(低壓化學氣相沉積)、電漿CVD或可流動CVD或任何其他合適的膜形成方法形成的氧化矽、氮化矽、氧氮化矽(SiON)、SiCN、氟摻雜的矽酸鹽玻璃(FSG)或低介電常數介電材料。可以在形成第一ILD層10之後執行退火操作。在一些實施例中,執行諸如化學機械拋光(CMP)方法及/或回蝕方法等平坦化操作以平坦化第一ILD層10的表面。
第7A圖和第7B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。在一些實施例中,在第一ILD層10上交替地形成半導體層25和犧牲層20。
在一些實施例中,半導體層25由氧化物半導體材料製成,該氧化物半導體材料為諸如非晶銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在一些實施例中,使用非晶IGZO。藉由CVD、原子層沉積(ALD)、包括濺射的物理氣相沉積或任何其他合適的膜形成方法來形成半導體層25。在一些實施例中,藉由CVD 在範圍為約50℃至600℃的溫度下形成半導體層25。在其他實施例中,藉由原子層沉積(ALD)在範圍為約25℃至400℃的溫度下形成半導體層25。在一些實施例中,藉由包括濺射的物理氣相沉積在範圍為約25℃至400℃的溫度下形成半導體層25。
在一些實施例中,犧牲層20由與半導體層25不同的材料製成,使得犧牲層20在隨後的製程中相對於半導體層25被選擇性地移除。在一些實施例中,犧牲層20由一或多層絕緣材料製成,該些絕緣材料為例如氧化矽、氮化矽、氧氮化矽、SiOC、氧化鋁、氧化鉿或任何其他合適的絕緣材料。在一些實施例中,犧牲層20由一或多層半導體材料製成,該些半導體材料為諸如Si、SiGe和Ge。在一些實施例中,半導體層是非晶或多晶的。在其他實施例中,犧牲層20由一或多層金屬材料製成,該金屬材料為諸如包括TiN和TaN的金屬氮化物。
半導體層25的厚度在一些實施例中範圍為約5nm至約30nm,並且在其他實施例中範圍為約10nm至約20nm。犧牲層20的厚度在一些實施例中範圍為約5nm至約30nm,並且在其他實施例中範圍為約10nm至約20nm。在一些實施例中,半導體層25的厚度等於犧牲層20的厚度,並且在其他實施例中,半導體層25的厚度大於或小於犧牲層20的厚度。
儘管圖示了四個半導體層25和五個犧牲層20,但是在一些實施例中,每次形成至多20層。在一些實施例中,半導體層25和犧牲層20的每一者的層數範圍為4至10層。在一些實施例中,犧性層20直接形成在第一ILD層10上,並且交替堆 疊的最上層是犧牲層20。在其他實施例中,替代堆疊的最上層是半導體層25。
第8A圖和第8B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。在一些實施例中,半導體層25和犧牲層20的交替堆疊被圖案化到鰭結構22中。
鰭結構22可以藉由任何合適的方法來圖案化。例如,可以使用一個或多個光刻製程來圖案化該結構,該一個或多個光刻製程包括雙重圖案化或多重圖案化製程。通常,雙重圖案化或多重圖案化製程組合光刻和自對準製程,從而允許創建具有例如比使用單個直接光刻製程可獲得的節距更小的節距的圖案。例如,在一個實施例中,在基板上形成犧牲層(心軸圖案),並使用光刻製程進行圖案化。使用自對準製程在經圖案化的犧牲層旁邊形成間隔物。隨後移除犧牲層(心軸圖案),並且隨後可以使用剩餘的間隔物來圖案化鰭結構22。
儘管在第8B圖中圖示了五個鰭結構22,但是一個TFT的鰭結構22的數量不限於五個。取決於驅動電流要求,在一些實施例中,每個TFT的鰭結構的數量範圍為1至10個,而在其他實施例中範圍為2至5個。鰭結構25的寬度在一些實施例中範圍為約10nm至約50nm,並且在其他實施例中範圍為約15nm至約30nm。
第9A圖和第9B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。在一些實施例中,如第9A圖所示,在鰭結構22和第一ILD層10上形成犧牲閘極介電質層42。在一些實施例中,犧牲閘極介電質層42由絕緣材料製成, 該絕緣材料為諸如氧化矽、氮化矽、氧氮化矽、SiOC、氧化鋁、氧化鉿或任何其他合適的絕緣材料。在其他實施例中,不形成犧牲閘極介電質層。
第10A圖和第10B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,如第10A圖和第10B圖所示,形成用於閘極替代技術的犧牲閘極結構40。在一些實施例中,犧牲閘極結構40包括犧牲閘電極層44和硬掩模層46。在一些實施例中,犧牲閘電極層44是多晶或非晶Si、SiGe或Ge。藉由化學氣相沉積(CVD)或任何其他合適的膜形成方法形成犧牲閘電極層44,並且在犧牲閘電極層44上形成硬掩模層46。在一些實施例中,硬掩模層46由基於氮化矽的材料(諸如氮化矽、SiON或SiCN)製成,或者由基於氧化矽的材料(諸如氧化矽)製成。在形成硬掩模層46之後,藉由使用一或多種光微影和蝕刻操作,對硬掩模層46進行圖案化。隨後,藉由使用圖案化的硬掩模層46作為蝕刻掩模,對沉積的犧牲閘電極層44進行圖案化。在一些實施例中,形成一或多個用於抑制製程變化及/或改善圖案保真度的虛擬閘極結構,以圍繞用於功能電晶體的犧牲閘極結構。
第11A圖和第11B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,如第11A圖和第11B圖所示,在犧牲閘極結構40的側面上形成閘極側壁間隔物48。藉由使用CVD或其他合適的方法而共形地形成用於閘極側壁間隔物48的絕緣材料毯覆層。毯覆層以共形方式沉積,使得其形成為在犧牲閘極結構40的豎直表面(諸如側壁)、水平表 面和頂部上具有基本上相等的厚度。在一些實施例中,將毯覆層沉積至範圍為約2nm至約30nm的厚度。在一個實施例中,毯覆層的絕緣材料不同於犧牲閘極結構40的材料,並且由基於氮化矽的材料製成,該基於氮化矽的材料為諸如氮化矽、SiON、SiOCN或SiCN及其組合。在一些實施例中,毯覆層由氮化矽製成。藉由各向異性蝕刻在犧牲閘極結構的相對側面上形成側壁間隔物。在一些實施例中,在硬掩模層46的相對側面上形成閘極側壁間隔物48。在一些實施例中,在鰭結構22的側面上形成側壁間隔物。
第12A圖和第12B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,移除犧牲閘極介電質層42並暴露鰭結構22,如第12A圖和第12B圖所示。如第12A圖所示,犧牲閘極介電質層42保留在犧牲閘極結構40和閘極側壁間隔物48下方。
第13A圖和第13B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,在犧牲閘極結構40和鰭結構22上形成第二ILD層50,如第13A圖和第13B圖所示。用於第二ILD層50的材料包括包含Si、O、C和/或H的化合物,諸如氧化矽、SiCOH和SiOC。諸如聚合物的有機材料可以用於第二ILD層50。在一些實施例中,第二ILD層50由與第一ILD層10相同的材料製成。在形成第二ILD層50之後,執行諸如CMP等平坦化操作,使得犧牲閘電極層44的頂部被暴露,如第13A圖和第13B圖所示。
第14A圖和第14B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,移除犧牲閘電極層44和犧牲閘極介電質層42,從而形成閘極空間52,如第14A圖和第14B圖所示。可以使用電漿乾式蝕刻和/或濕式蝕刻來移除犧牲閘電極層44。在一些實施例中,當犧牲閘電極層44由多晶或非晶Si製成時,使用四甲基氫氧化銨溶液(TMAH)作為濕式蝕刻劑。亦藉由合適的濕式/乾式蝕刻移除犧牲閘極介電質層42。
此外,如第14A圖和第14B圖所示,犧牲層20也在閘極空間52下方被移除。當犧牲層20和犧牲閘極介電質層42由相同或相似的材料製成時,對犧牲閘極介電質層42的移除操作(例如,濕式蝕刻)亦移除犧牲層20。當犧牲層20和犧牲閘極介電質層42由彼此不同的材料製成時,執行兩次或更多次蝕刻操作以順序地移除犧牲閘極介電質層42和犧牲層20。藉由移除犧牲層20,將半導體層25的通道區域在閘極空間52中作為半導體奈米層片釋放。
第15A圖和第15B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。隨後,如第15A圖和第15B圖所示,在閘極空間52中形成閘極介電質層82和金屬閘電極80。在一些實施例中,閘極介電質層82包括一層或多層介電材料,諸如氧化矽、氮化矽、或高介電常數介電材料、其他合適的介電材料,和/或其組合。高介電常數介電材料的實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合 金、其他合適的高介電常數介電材料,和/或其組合。在一些實施例中,閘極介電質層82包括在通道區與介電質材料之間形成的界面層。閘極介電質層82可以藉由CVD、ALD或任何合適的方法形成。在一個實施例中,使用諸如ALD等高度共形沉積製程來形成閘極介電質層82,以確保在每個通道區周圍形成具有均勻厚度的閘極介電質層。閘極介電質層82的厚度在一些實施例中在約1nm至約20nm的範圍內,並且在其他實施例中在約2nm至約10nm的範圍內。
在一些實施例中,金屬閘電極80包括一或多個功函數調節層84和體金屬閘電極86。功函數調節層84由導電材料製成,該導電材料為諸如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC,或多層的該些材料中的兩種或更多種材料。功函數調節層84可藉由ALD、PVD、CVD、電子束蒸鍍或其他合適的製程來形成。此外,功函數調節層84可以被單獨地形成以用於該nFET和該pFET,該nFET和該pFET可以使用不同的金屬層。體金屬閘電極86形成為圍繞每個氧化物半導體奈米層片(通道區)。體金屬閘電極86包括一層或多層導電材料,諸如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適的材料,和/或其組合。體金屬閘電極86可以藉由CVD、ALD、電鍍或其他合適的方法形成。亦在第二ILD層50的上表面上沉積閘極介電質層82和金屬閘電極80的金屬。隨後藉由使用例如CMP來平坦化形成在第二ILD層50上的金屬閘電極80的材 料,直到第二ILD層50的頂表面被揭露,如第15A圖和第15B圖所示。在一些實施例中,在平坦化操作之後,使金屬閘電極80凹陷並且在該凹陷的金屬閘電極80上形成封蓋絕緣層(未圖示)。封蓋絕緣層包含一或多層基於氮化矽的材料,諸如氮化矽。可以藉由沉積絕緣材料之後進行平坦化操作來形成封蓋絕緣層。
第16A圖和第16B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。此外,在第二ILD層50上形成第三ILD層60,並且在第三ILD層和第二ILD層中形成用於源極/汲極觸點的接觸孔65,如第16A圖和第16B圖所示。用於第三ILD層60的材料包括包含Si、O、C和/或H的化合物,諸如氧化矽、SiCOH和SiOC。諸如聚合物等有機材料可以用於第三ILD層60。在一些實施例中,第三ILD層60由與第二ILD層50及/或第一ILD層10相同的材料製成。在一些實施例中,第三ILD層60用作用於蝕刻第二ILD層50的硬掩模層。
第17A圖和第17B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。在形成接觸孔65之後,在接觸孔65下方移除犧牲層20,從而釋放犧牲層20的源極/汲極區,如第17A圖所示。
在一些實施例中,部分犧牲層20保留作為內部間隔物21。在一些實施例中,當犧牲層20保留作為內部間隔物21時,犧牲層20由絕緣材料製成。在其他實施例中,完全移除犧牲層20。
第18A圖至第20B圖是根據本揭示的一實施例的製造半導體元件的順序步驟的示意圖。第18A圖圖示沿源極至汲極方向(Y方向)截取的橫截面,第19A圖圖示沿閘電極的閘極延伸方向(X方向)截取的橫截面,並且第20A圖圖示了沿著源極/汲極觸點的X方向截取的橫截面。
如第18A圖至第20B圖所示,在接觸孔65中形成源極/汲極觸點70。在接觸孔內和接觸孔上形成一或多層導電材料,隨後執行諸如CMP操作等平坦化操作以形成源極/汲極觸點70。在一些實施例中,源極/汲極觸點70包括襯墊層或阻擋層72和體接觸層74,如第4圖所示。在一些實施例中,襯墊層72由Ti、TiN、Ta和TaN中的一或多種製成,並且體接觸層74由W、Cu、Ti、Ag、Al、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt和Zr中的一或多種製成。如第20A圖所示,至少部分的襯墊層72包裹在半導體層(氧化物半導體奈米層片)25的源極/汲極區周圍。在其他實施例中,體接觸層74亦包裹在源極/汲極區周圍。
應當理解,TFT經歷進一步的處理以形成各種特徵,諸如觸點/通孔、互連金屬層、介電質層、鈍化層等。
第21A圖至第22B圖圖示根據本揭示的另一實施例的用於製造半導體元件的順序操作。應當理解,對於該方法的其他實施例,可以在第21A圖至第22B圖所示的製程之前、期間和之後提供額外的操作,並且下面描述的一些操作可以被替換或者省略。第21A圖至第22B圖所示的製造操作對應於第5圖所示的TFT結構。
在形成用於源極/汲極觸點的接觸孔65之後,半導體層25和犧牲層20皆在接觸孔65中被移除,如第21A圖和第21B圖所示。隨後,類似於第20A圖和第20B圖,如第22A圖和第22B圖所示,形成源極/汲極觸點70。
第23圖圖示根據本揭示的一實施例的半導體元件的剖視圖。如第23圖所示,在基板上形成下層元件100。下層元件100包括一或多個鰭式場效電晶體(FinFET)、環繞式閘極FET、平面FET、豎直FET,或任何其他電子元件。第23圖亦圖示了設置在下層元件100上的上層元件200。在一些實施例中,一或多個ILD層、金屬佈線層及/或通孔觸點設置在下層元件100與上層元件200之間。在一些實施例中,上層元件200包括藉由本揭示的上述實施例製造的一或多個TFT。
在本實施例中,由於功率開關電路用於將電力供應從主電力供應(VDD或VSS)切換成本端電力供應(VVDD或VVSS),所以藉由使用諸如IGZO等氧化物半導體來形成電力供應佈線。因此,可以在BEOL電路級處提供功率開關電路。
應當理解,並非所有優點都必須在本文中論述,所有實施例或實例都不需要特別的優點,並且其他實施例或實例可以提供不同的優點。
根據本揭示的一態樣,在一種製造半導體元件的方法中,形成包括交替堆疊的半導體層和犧牲層的堆疊結構,在該堆疊結構上形成犧牲閘極結構,在該犧牲閘極結構上形成介電質層,移除該犧牲閘極結構,從而形成閘極空間,在該閘極空間中移除該些犧牲層,從而釋放該些半導體層,形成包裹 在該些半導體層周圍的閘極結構。該些半導體層由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括選自由以下項組成的群組:銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,該犧牲層包含選自由以下項組成的群組的一種:絕緣材料、非晶或多晶半導體材料和金屬氮化物材料。在前述及/或以下實施例中的一或多個中,在絕緣材料層上形成堆疊結構。在前述及/或以下實施例中的一或多個中,絕緣材料層覆蓋形成在半導體基板上的電晶體。在前述及/或以下實施例中的一或多個中,藉由以下方式來形成堆疊結構:在絕緣材料層上交替地形成半導體層和犧牲層,以及將該些半導體層和該些犧性層圖案化到一或多個鰭結構中。
根據本揭示的另一態樣,在一種製造半導體元件的方法中,在第一介電質層上形成包括交替堆疊的半導體層和犧牲層的鰭結構,在該鰭結構上形成犧牲閘極結構,在該犧牲閘極結構的相對側面上形成閘極側壁間隔物,在該犧牲閘極結構和該鰭結構上形成第二介電質層,移除該犧牲閘極結構,從而形成閘極空間,在該閘極空間中移除該些犧牲層,從而釋放該些半導體層的通道區,形成包裹在該些半導體層的該些通道區周圍的閘極結構,形成第三介電質層,在該第三介電質層和該第二介電質層中形成接觸開口,在該接觸開口中移除該些犧牲層,從而釋放該些半導體層的源極/汲極區,並且形成包裹 該些半導體層的該些源極/汲極區的源極/汲極觸點。該些半導體層由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括選自由以下項組成的群組:銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,犧牲層包含選自由以下項組成的群組中的一種:如氧化矽、氮化矽、氧氮化矽、SiOC、氧化鋁、氧化鉿。在前述及/或以下實施例中的一或多個中,犧牲層包括選自由以下項組成的群組中的一種:非晶或多晶Si、SiGe和Ge。在前述及/或以下實施例中的一或多個中,犧牲層包括選自由以下項組成的群組中的一種:TiN和TaN。在前述及/或以下實施例中的一或多個中,第一介電質層覆蓋形成在半導體基板上的電晶體。在前述及/或以下實施例中的一或多個中,在移除接觸開口中的犧牲層時,保留犧牲層的部分,並且在形成源極/汲極觸點之後,將該些犧牲層的剩餘部分設置在源極/汲極觸點與閘極結構之間。
根據本揭示的另一方面,在一種製造半導體元件的方法中,在第一介電質層上形成包括交替堆疊的半導體層和犧牲層的鰭結構,在該鰭結構上形成犧牲閘極結構,在該犧牲閘極結構的相對側面上形成閘極側壁間隔物,在該犧牲閘極結構和該鰭結構上形成第二介電質層,移除該犧牲閘極結構,從而形成閘極空間,在該閘極空間中移除犧牲層,從而釋放該些半導體層的通道區,形成包裹在該些半導體層的該些通道區周 圍的閘極結構,形成第三介電質層,在該第三介電質層和該第二介電質層中形成接觸開口,在該接觸開口中移除該些犧牲層和該些半導體層,並且在該接觸開口中形成源極/汲極觸點。該些半導體層由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括選自由以下項組成的群組中的一種:銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,犧牲層包含選自由以下項組成的群組中的一種:如氧化矽、氮化矽、氧氮化矽、SiOC、氧化鋁、氧化鉿。在前述及/或以下實施例中的一或多個中,在移除接觸開口中的犧牲層時,保留犧牲層的部分,並且在形成源極/汲極觸點之後,將該些犧牲層的剩餘部分設置在源極/汲極觸點與閘極結構之間。
根據本揭示的一個態樣,一種半導體元件包括功率開關電路和邏輯電路。功率開關電路包括第一介電質層和形成在該第一介電質層上的薄膜電晶體。薄膜電晶體包括豎直佈置的半導體奈米層片、包裹在該半導體奈米層片的通道區周圍的閘極介電質層,以及形成在該閘極介電質層上的閘電極層。該半導體奈米層片由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括選自由以下項組成的群組中的一種:銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在前述 及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,半導體奈米層片的厚度T1的範圍為5nm至30nm,並且沿著閘極延伸方向每個半導體奈米層片的寬度W1的範圍為10nm至50nm。在前述及/或以下實施例中的一或多個中,比率W1/T1的範圍為1.2至10。
根據本揭示的另一方面,一種半導體元件包括功率開關電路和邏輯電路。功率開關電路包括第一介電質層和形成在該第一介電質層上的薄膜電晶體(TFT)。TFT包括豎直佈置的半導體奈米層片,包裹在每個半導體奈米層片的通道區周圍的閘極介電質層,以及形成在該閘極介電質層上的閘電極層。該半導體奈米層片由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括選自由以下項組成的群組中的一種:銦鎵鋅氧化物(IGZO)、c軸對準的結晶(CAAC)-IGZO、ZnO、In2O3、Ga2O3和ZnON。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,每個半導體奈米層片的厚度T1的範圍為5nm至30nm,並且沿著閘極延伸方向每個半導體奈米層片的寬度W1的範圍為10nm至50nm。在前述及/或以下實施例中的一或多個中,比率W1/T1的範圍為2至5。在前述及/或以下實施例中的一或多個中,半導體奈米層片的數量範圍為2至10個。在前述及/或以下實施例中的一或多個中,TFT進一步包括包裹在每個半導體奈米層片的源極/汲極區周圍的源極/汲極觸點。在 前述及/或以下實施例中的一或多個中,TFT進一步包括設置在源極/汲極觸點與閘電極層之間的內部間隔物。在前述及/或以下實施例中的一或多個中,TFT亦包括與半導體奈米層片的端面接觸的源極/汲極觸點。在前述及/或以下實施例中的一或多個中,TFT進一步包括設置在源極/汲極觸點與閘電極層之間的內部間隔物。
根據本揭示的另一態樣,一種半導體元件包括功率開關電路和邏輯電路,並且該半導體元件包括第一介電質層和形成在該第一介電質層上的薄膜電晶體(TFT)。TFT包括複數個群組的半導體奈米層片,其中半導體奈米層片豎直佈置在該複數個群組的每一群組中,閘極介電質層包裹在該複數個群組的半導體奈米層片的每個半導體奈米層片的通道區周圍,並且閘電極層形成在該複數個群組的半導體奈米層片上方的閘極介電質層上。該半導體奈米層片由氧化物半導體材料製成。在前述及/或以下實施例中的一或多個中,該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。在前述及/或以下實施例中的一或多個中,每個半導體奈米層片的厚度T1的範圍為5nm至30nm,並且沿著閘極延伸方向每個半導體奈米層片的寬度W1的範圍為10nm至50nm。在前述及/或以下實施例中的一或多個中,半導體奈米層片的數量範圍為2至10個。在前述及/或以下實施例中的一或多個中,該複數個群組的數量範圍為2至5個。
先前概述了若干實施例或實例的特徵,使得本領域技藝人士可以更好地理解本揭露的各態樣。本領域技藝人士 應當理解,他們可以容易地使用本揭露作為設計或修改其他製程和結構的基礎,以實現與本文介紹的實施例或實例相同的目的及/或實現與本文介紹的實施例相同的優點。本領域技藝人士亦應當認識到,此類等同構造不脫離本揭露的精神和範疇,並且在不脫離本揭露的精神和範疇的情況下,他們可以在本文中進行各種改變、替換和變更。
10:第一ILD層
21:內部間隔物
25:氧化物半導體奈米層片
48:閘極側壁間隔物
50:第二ILD層
70:源極/汲極觸點
72:襯墊層/阻擋層
74:體接觸層
82:閘極介電質層
84:功函數調節層
86:體金屬閘電極

Claims (10)

  1. 一種製造半導體元件的方法,包括以下步驟:形成包括交替堆疊的複數個半導體層和複數個犧牲層的一堆疊結構;在該堆疊結構上形成一犧牲閘極結構;在該犧牲閘極結構和該堆疊結構上形成一第一介電質層,其中該第一介電質層圍繞該堆疊結構;執行一平坦化操作以暴露該犧牲閘極結構的一頂部;移除該犧牲閘極結構,從而形成一閘極空間;在該閘極空間中移除一部分的該些犧牲層,從而釋放該些半導體層,並留下另一部分的該些犧牲層;形成包裹在該些半導體層周圍的一閘極結構,在該第一介電質層上形成一第二介電質層;在該第二介電質層和該第一介電質層中形成兩個接觸開口,其中該些接觸開口分別位於該閘極結構的兩側;在形成該些接觸開口後,在該些接觸開口中移除另一部分的該些犧牲層,從而釋放該些半導體層的複數個源極/汲極區;以及形成包裹在該些半導體層的該些源極/汲極區周圍的一源極/汲極觸點,其中該些半導體層由一氧化物半導體材料製成。
  2. 如請求項1所述之方法,其中該氧化物半導體材料選自於由銦鎵鋅氧化物(IGZO)、c軸對準的結晶 IGZO(c-axis aligned crystal IGZO,CAAC IGZO)、ZnO、In2O3、Ga2O3和ZnON所組成的群組。
  3. 如請求項1所述之方法,其中該氧化物半導體材料包括非晶銦鎵鋅氧化物(IGZO)。
  4. 一種製造半導體元件的方法,包括以下步驟:在一第一介電質層上形成包括交替堆疊的複數個半導體層和複數個犧牲層的一鰭結構;在該鰭結構上形成一犧牲閘極結構;在該犧牲閘極結構的相對側面上形成複數個閘極側壁間隔物;在該犧牲閘極結構和該鰭結構上形成一第二介電質層,其中該第二介電質層圍繞該鰭結構;執行一平坦化操作以暴露該犧牲閘極結構的一頂部;移除該犧牲閘極結構,從而形成一閘極空間;在該閘極空間中移除一部分的該些犧牲層,從而釋放該些半導體層的通道區,並留下另一部分的該些犧牲層;形成包裹在該些半導體層的該些通道區周圍的一閘極結構;在該第二介電質層上形成一第三介電質層;在該第三介電質層和該第二介電質層中形成兩個接觸開口,其中該些接觸開口分別位於該閘極結構的兩側; 在形成該些接觸開口後,在該些接觸開口中移除另一部分的該些犧牲層,從而釋放該些半導體層的複數個源極/汲極區;以及形成包裹在該些半導體層的該些源極/汲極區周圍的一源極/汲極觸點,其中該些半導體層由一氧化物半導體材料製成。
  5. 如請求項4所述之方法,其中該些犧牲層選自於由氧化矽、氮化矽、氧氮化矽、SiOC、氧化鋁、氧化鉿所組成的群組。
  6. 如請求項4所述之方法,其中該些犧牲層選自於由非晶矽或多晶矽、矽鍺和鍺所組成的群組。
  7. 如請求項4所述之方法,其中該些犧牲層選自於由TiN和TaN所組成的群組。
  8. 一種包括一功率開關電路和一邏輯電路的半導體元件,該功率開關電路包括:一第一介電質層;一第一薄膜電晶體,該第一薄膜電晶體形成在該第一介電質層上,其中:該第一薄膜電晶體包括:豎直佈置的複數個第一半導體奈米層片; 一第一閘極介電質層,該第一閘極介電質層包裹在該些第一半導體奈米層片的每一者的一第一通道區周圍;一第一閘電極層,該第一閘電極層形成在該第一閘極介電質層上,一第二薄膜電晶體,該第二薄膜電晶體形成在該第一薄膜電晶體上,其中:該第二薄膜電晶體包括:豎直佈置的複數個第二半導體奈米層片;一第二閘極介電質層,該第二閘極介電質層包裹在該些第二半導體奈米層片的每一者的一第二通道區周圍;一第二閘電極層,該第二閘電極層形成在該第二閘極介電質層上,其中該些第一半導體奈米層片和該些第二半導體奈米層片由一氧化物半導體材料製成,該第一薄膜電晶體和該第二薄膜電晶體位於一後段製程電路級中,且該第二薄膜電晶體之尺寸大於該第一薄膜電晶體之尺寸。
  9. 如請求項8所述之半導體元件,其中:該些第一半導體奈米層片的每一者的一厚度T1範圍為5nm至30nm,以及沿著一閘極延伸方向,該些第一半導體奈米層片的每一者的一寬度W1範圍為10nm至50nm。
  10. 如請求項9所述之半導體元件,其中W1/T1之比率的範圍為2至5。
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