TWI725539B - 半導體裝置和製造半導體裝置的方法 - Google Patents

半導體裝置和製造半導體裝置的方法 Download PDF

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TWI725539B
TWI725539B TW108132309A TW108132309A TWI725539B TW I725539 B TWI725539 B TW I725539B TW 108132309 A TW108132309 A TW 108132309A TW 108132309 A TW108132309 A TW 108132309A TW I725539 B TWI725539 B TW I725539B
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layer
semiconductor
gate
semiconductor layer
forming
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TW108132309A
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TW202032724A (zh
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喬治凡利亞尼提斯
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台灣積體電路製造股份有限公司
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Abstract

在一種製造半導體裝置之方法中，在基板之上形成單晶氧化物層。在形成單晶氧化物層之後，形成用以限定活性區域之隔離結構。在活性區域中於單晶氧化物層之上形成閘極結構。形成源極/汲極結構。

Description

半導體裝置和製造半導體裝置的方法
本揭示是關於一種半導體裝置和一種製造半導體裝置的方法。
經常實施傳統的互補金屬氧化物半導體(complementary metal-oxide-semiconductor；CMOS)技術以在單個積體電路(integrated-circuit；IC)晶片上之大致同一層級處製造大量半導體元件，諸如，金屬氧化物半導體場效應電晶體(metal-oxide-semiconductor field effect transistor；MOSFET)及雙極接面電晶體(bipolar junction transistor；BJT)。在先進IC晶片中，將電晶體設置在多個層上。
根據本揭示案之一態樣，在一種製造半導體裝置之方法中，在設置於基板之上的介電層上形成半導體層；在半導體層上形成種晶層；將種晶層圖案化成經圖案 化之種晶層；以及使用經圖案化之種晶層作為結晶之種晶來對半導體層執行結晶操作，藉此形成已結晶之半導體層。
根據本揭示案之一態樣，在一種製造半導體裝置之方法中，在設置於基板之上的介電層上形成非晶或多晶的半導體層；在半導體層上形成種晶層；將種晶層圖案化成多個經圖案化之種晶層；以及使用這些經圖案化之種晶層作為結晶之種晶來對半導體層執行結晶操作，藉此在介電層之上形成多個單晶半導體層。
根據本揭示案之一態樣，一種半導體裝置包括：電子裝置、一或多個介電層及多個薄膜電晶體。電子裝置被設置在基板上。一或多個介電層被設置在電子裝置之上。這些薄膜電晶體被設置在一或多個介電層中之一最上層上。這些薄膜電晶體中之每一者包括：通道、閘極介電層、閘電極層、多個側壁間隔物，以及源極及汲極。通道形成為設置在最上層上之一半導體層之一部分。閘極介電層被設置在通道之上。閘電極層被設置在閘極介電層之上。這些側壁間隔物被設置在閘電極層之相對側面上。通道為單晶。晶界存在於這些薄膜電晶體中之一者的半導體層與鄰近這些薄膜電晶體中之者的這些薄膜電晶體中之另一者的半導體層之間。
10:基板
20:介電層
30:半導體層
35:已結晶部分
37:晶界
40:種晶層
45:經圖案化之種晶層
47:閘極空間
50:側壁間隔物
60:源極/汲極區域
65:第一層間介電質(ILD)層
70:閘極介電層
75:閘電極
80:第二ILD
85:導電接觸件
90:虛設閘極層
95:經圖案化之虛設閘極層
100:下層元件
200:上層元件
W1:寬度
本揭示案當結合附圖閱讀時將自以下詳細描述中最佳地理解。應強調，根據工業上之標準實務，各種特 徵並未按比例繪製且僅用於說明目的。事實上，為了論述清楚，可任意地增大或減小各種特徵之尺寸。
圖1繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖2繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖3繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖4繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖5繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖6繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖7繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖8繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖9繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖10繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖11繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖12繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖13A及圖13B繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段中之一者。
圖14繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖15繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖16繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖17繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖18繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖19繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖20繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖21繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖22繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖23繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖24繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖25繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖26繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖27繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖28繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖29繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖30繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖31繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖32繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖33繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖34繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖35繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖36A繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖36B繪示根據本揭示案之另一實施例的製造半導體FET裝置之各個階段中之一者。
圖37繪示根據本揭示案之實施例之半導體FET裝置的橫截面圖。
應理解，以下揭示內容提供了用於實施本發明之不同特徵的許多不同實施例或實例。以下描述元件及佈置之特定實施例或實例以簡化本揭示案。當然，此些僅為實例，且並不意欲為限制性的。舉例而言，元件之尺寸並不限於所揭示之範圍或值，而可視製程條件及/或裝置之所需性質而定。此外，在如下描述中之第一特徵在第二特徵之上或在第二特徵上的形成可包括其中第一特徵與第二特徵形成為直接接觸之實施例，且亦可包括其中額外特徵可形成為插入第一特徵與第二特徵之間而使得第一特徵與第二特徵可不直接接觸的實施例。為了簡化及清楚起見，可以不同比例任意地繪製各種特徵。
另外，為了便於描述起見，可在本文中使用諸如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」之空間相對術語及其類似術語，以描述如諸圖中所繪示之一個元件或特徵與另一(其他)元件或特徵的關係。除了諸圖中所描繪之定向以外，該等空間相對術語 意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或以其他定向)，且可同樣相應地解釋本文中所使用之空間相對描述詞。另外，術語「由……製成」可意謂「包括」抑或「由……組成」。在本揭示案中，詞語「A、B及C中之一者」意謂「A、B及/或C」(A、B、C、A與B、A與C、B與C，或者A、B及C)，且並不意謂來自A之一個元件、來自B之一個元件以及來自C之一個元件，除非另有描述。
對於後端工序(back-end of line)中之電晶體製造製程而言，存在用以在非晶層(諸如，氧化矽層)之上形成用於電晶體通道之高品質結晶半導體層的關鍵製程。在氧化矽層上製造結晶半導體之方法包括：(a)生長呈非晶態之半導體膜，接著以高溫退火；及(b)藉由使用自結晶Si基板生長之結晶種晶來生長半導體層。這兩種方法皆可能不適合用於後端工序製程，因為：對於方法(a)而言，存在熱預算之限制，例如，小於450℃；且對於方法(b)而言，結晶種晶層需要穿過若干金屬層及層間介電層。
本揭示案提供一種用以在非晶(非晶體)介電層上形成高品質結晶半導體層之方法。本揭示案亦提供一種用以在多晶或非晶半導體層轉換為具有較高結晶度之結晶層的區域中製造電晶體的自對準方法。
在以下實施例中，除非另有描述，否則一個實施例之材料、配置、尺寸及/或製程可用於另一實施例中，且可省略其詳細描述。
圖1至圖13A繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段。應理解，可在由圖1至圖13A所示之操作之前、在其期間以及在其之後提供額外操作，且可替代或消除以下所述之操作中的一些而獲得該方法之額外實施例。操作/製程之次序可互換。另外，在本揭示案中，可互換地使用源極及汲極，且源極/汲極指代源極及汲極中之至少一者。
如圖1中所示，提供基板10。在一些實施例中，基板10至少在其表面部分上包括單晶半導體層。基板10可包括單晶半導體材料，諸如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在某些實施例中，基板10由結晶Si、SiGe或Ge製成。在一些實施例中，基板10可在其表面區域中包括一或多個緩衝層(未示出)。緩衝層可用以逐漸地使晶格常數自基板之晶格常數改變為源極/汲極區域之晶格常數。緩衝層可由磊晶生成之單晶半導體材料形成，諸如但不限於Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP。在特定實施例中，基板10包括磊晶生成於矽基板10上之矽鍺(SiGe)緩衝層。SiGe緩衝層之鍺濃度可自最底部緩衝層之30原子百分比鍺增大至最頂部緩衝層之70原子百分比鍺。
另外，如圖1中所示，在基板10之上形成一或多個介電層20。在一些實施例中，在基板10上形成諸如電晶體、記憶體(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)、靜態RAM、磁性MRAM及/或相變RAM)的一或多個電子裝置，且一或多個介電層20覆蓋這些電子裝置。另外，一或多個金屬佈線結構嵌入在介電層20中。用於介電層20之介電材料包括藉由低壓化學氣相沉積(low pressure chemical vapor deposition；LPCVD)、電漿CVD或可流動CVD或任何其他合適之膜形成方法而形成的氧化矽、氮化矽、氧氮化矽(SiON)、SiCN、氟摻雜之矽酸鹽玻璃(fluorine-doped silicate glass；FSG)或低K介電材料。可在形成介電層20之後執行退火操作。在一些實施例中，執行諸如化學機械研磨(chemical mechanical polishing；CMP)方法及/或回蝕方法之平坦化操作，以使介電層20之表面變平。
仍參考圖1，在介電層20之上形成作為通道半導體材料之半導體層30。在一些實施例中，用於半導體層30之半導體材料包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在某些實施例中，半導體層30由Si、SiGe或Ge製成。
在一些實施例中，藉由CVD、ALD或任何其他合適之膜形成方法來形成半導體層30。在一些實施例中，在低於約450℃之溫度下執行膜形成。在一些實施例中，在等於或高於約25℃之溫度下執行膜形成。在一些實施例中，將Si2H6氣體用作Si之源氣體，且將Ge2H6氣體用作Ge之源氣體。在某些實施例中，替代於Ge2H6及/或Si2H6或除了Ge2H6及/或Si2H6以外，使用GeH4及/或SiH4。在一些實 施例中，半導體層30為非晶的或多晶的。在一些實施例中，半導體層30適當地摻雜有雜質，諸如，P、As、Sb及/或B。該等雜質是在膜形成期間原位地摻雜，或在半導體層30形成之後藉由離子佈植或電漿摻雜進行摻雜。半導體層30之厚度在一些實施例中在自約5nm至約500nm之範圍中，且在其他實施例中在自約10nm至約50nm之範圍中。
接著，如圖2中所示，在半導體層30之上形成種晶層40。在一些實施例中，無種晶層形成在半導體層30下方。在一些實施例中，種晶層40由金屬氧化物製成，該金屬氧化物具有在沉積時結晶之性質或在約300℃至約450℃之低溫退火下結晶之性質。在某些實施例中，種晶層40由氧化鎂(MgO)製成。在一些實施例中，MgO種晶層40為單晶的。在其他實施例中，MgO種晶層40為多晶的或具有單晶之多個晶疇。可藉由CVD、原子層沉積(atomic layer deposition；ALD)、物理氣相沉積(包括濺射)或任何其他合適之膜形成方法來形成種晶層40。種晶層40之厚度在一些實施例中在自約1nm至約100nm之範圍中，且在其他實施例中在自約2nm至約20nm之範圍中。在某些實施例中，種晶層40之厚度在自約1nm至約10nm之範圍中。在其他實施例中，將HfO2、La2Hf2O7、Y2O3、SrTiO3及HfZrO2中之一者作為種晶層40。
接下來，如圖3中所示，藉由使用一或多個微影操作及蝕刻操作將種晶層40圖案化成經圖案化之種晶層45。微影操作包括紫外線(UV)微影、深UV(DUV)微影、 極UV(EUV)微影、電子束(e-beam)微影，且蝕刻操作包括電漿乾式蝕刻。經圖案化之種晶層45對應於隨後形成之FET之閘電極。因此，經圖案化之種晶層45的寬度W1對應於FET之閘極長度，且經圖案化之種晶層45具有對應於FET之閘電極的形狀。在一些實施例中，經圖案化之種晶層45具有線形形狀。寬度W1在一些實施例中在自約5nm至約500nm之範圍中，且在其他實施例中在自約20nm至約200nm之範圍中。
隨後，如圖4至圖7中所示，執行結晶製程以使半導體層30結晶。結晶製程包括熱退火。在一些實施例中，熱退火包括使用奈秒雷射之雷射退火製程，該奈秒雷射對種晶層透明。在其他實施例中，熱退火包括在自約350℃至450℃之範圍中之溫度下的低溫退火。
如圖5及圖6中所示，半導體層30開始自經圖案化之種晶層的底部(對應於隨後形成之FET的通道區域)結晶為晶體模板。藉由繼續熱退火製程，半導體層30之已結晶部分35橫向地擴展至源極/汲極區域中，如圖7中所示。在一些實施例中，整個半導體層30變成晶體。
隨後，如圖8中所示，在經圖案化之種晶層45之相對側面上形成側壁間隔物50。藉由使用CVD或其他合適方法保形地形成用於側壁間隔物50之絕緣材料的毯覆層(blanket layer)。以保形方式來沉積毯覆層，以使得該毯覆層經形成而在經圖案化之種晶層45的垂直表面(諸如，側壁)、水平表面及頂部上具有大體上相等之厚度。在一些 實施例中，將毯覆層沉積至自約2nm至約30nm之範圍中的厚度。在一個實施例中，毯覆層之絕緣材料不同於經圖案化之種晶層45的材料，且由基於氮化矽之材料製成，諸如，氮化矽、SiON、SiOCN或SICN及其組合。在一些實施例中，毯覆層(側壁間隔物50)由氮化矽製成。如圖8中所示，藉由各向異性蝕刻，在經圖案化種晶層45之相對側面上形成側壁間隔物50。在閘極替代技術中，經圖案化之種晶層45充當虛設閘電極。
接著，如圖9中所示，形成源極區域及汲極區域。在一些實施例中，源極/汲極區域60包括一或多個磊晶半導體層。源極/汲極磊晶層60包括一或多層用於n通道FET之Si、SiP、SiC及SICP或用於p通道FET之Si、SiGe、Ge。對於P通道FET而言，亦可在源極/汲極區域中含有硼(B)。藉由使用CVD、ALD或MBE之磊晶生成方法來形成源極/汲極磊晶層50。在一些實施例中，藉由蝕刻使已結晶之半導體層35的源極/汲極區域凹陷，且接著在已結晶之半導體層35的凹陷源極/汲極區域之上形成源極/汲極磊晶層60。在其他實施例中，執行一或多個離子佈植製程，以將雜質引入已結晶之半導體層35的源極/汲極區域中。
接著，在源極/汲極磊晶層60及經圖案化之種晶層45之上形成第一層間介電質(interlayer dielectric；ILD)層65。用於第一ILD層65之材料包括化合物，該等化合物包括Si、O、C及/或H，諸如，氧化矽、SiCOH及SiOC。可將諸如聚合物之有機材料用於第一ILD層65。在形成了第 一ILD層65之後，執行平坦化操作(諸如，CMP)，以使得經圖案化之種晶層45的頂部被暴露，如圖10中所示。在一些實施例中，經圖案化之種晶層45充當CMP終止層。在一些實施例中，在第一ILD層65形成之前，形成接觸蝕刻終止層，諸如，氮化矽層或氧氮化矽層。
接著，移除經圖案化之種晶層45，藉此形成閘極空間47，如圖11中所示。可使用電漿乾式蝕刻及/或濕式蝕刻來移除經圖案化之種晶層45。
在移除了經圖案化之種晶層45之後，在閘極空間47中形成閘極介電層70及閘電極75，如圖12中所示。在一些實施例中，閘極介電層70包括一或多層介電材料，諸如，氧化矽、氮化矽或高k介電材料、其他合適介電材料及/或其組合。高k介電材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料，及/或其組合。在一些實施例中，閘極介電層70包括藉由使用化學氧化形成於通道層35與介電材料之間的界面層。可藉由CVD、ALD或任何合適方法形成閘極介電層70。在一個實施例中，使用諸如ALD之高度保形沉積製程形成閘極介電層70，以便確保形成在每一通道層周圍具有均勻厚度的閘極介電層。在一個實施例中，閘極介電層70之厚度在自約1nm至約10nm之範圍中。
隨後，在閘極介電層70上形成閘電極層75。閘電極層75包括一或多層導電材料，諸如，多晶矽、鋁、銅、 鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金屬合金、其他合適材料及/或其組合。可藉由CVD、ALD、電鍍或其他合適方法形成閘電極層75。用於閘極介電層70及閘電極層75之金屬亦被沉積在第一ILD層65之上表面之上。接著藉由使用例如CMP來平坦化形成於ILD層65之上的用於閘電極層之材料，直至露出ILD層65之頂表面為止。在一些實施例中，在平坦化操作之後，金屬閘電極層75凹陷且在凹陷閘電極層之上形成覆蓋絕緣層(未示出)。該覆蓋絕緣層包括一或多層基於氮化矽之材料，諸如，氮化矽。可藉由沉積絕緣材料繼之以平坦化操作來形成覆蓋絕緣層。
在本揭示案之某些實施例中，將一或多個功函數調整層(未示出)插入閘極介電層70與閘電極層75之間。功函數調整層由導電材料製成，諸如，單層之TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或該等材料中之兩者或兩者以上的多層。對於n通道FET而言，將TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中之一或多者用作功函數調整層，且對於p通道FET而言，將TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調整層。可藉由ALD、PVD、CVD、電子束蒸鍍或其他合適製程來形成功函數調整層。另外，可針對可使用不同金屬層之n通道FET及p通道FET單獨地形成功函數調整層。
另外，如圖13A中所示，第二ILD層80形成於第一ILD層65之上，且穿過第二ILD層80或第二ILD層與第一ILD層之導電接觸件85經形成而接觸閘電極75及源極/汲極磊晶層60。在第一ILD層及/或第二ILD層中形成接觸開口。在接觸開口中及在接觸開口之上形成一或多層導電材料，且接著執行平坦化操作(諸如，CMP操作)以形成導電接觸件85，如圖13A中所示。在一些實施例中，導電接觸件85包括襯墊層及主體層。該襯墊層為阻障層及/或膠(黏合)層。在一些實施例中，在源極/汲極磊晶層55上形成Ti層，且在Ti層上形成TiN或TaN層，作為襯墊層。該主體層包括一或多層Co、Ni、W、Ti、Ta、Cu及AI，或任何其他合適材料。
應理解，FET經受進一步CMOS製程，以形成各種特徵，諸如，接觸點/通孔、互連金屬層、介電層、鈍化層，等等。
在其他實施例中，如圖13B中所示，當在必要區域(諸如，通道區域及源極/汲極區域)中形成了已結晶部分35時，結晶製程終止。因此，存在未結晶之半導體層30的部分，其為非晶晶體或多晶晶體。
圖14至圖23繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段。應理解，可在由圖14至圖23所示之操作之前、在其期間以及在其之後提供額外操作，且可替代或消除以下所述之操作中的一些而獲得該方法之額外實施例。操作/製程之次序可互換。
類似於圖1及圖2，在半導體層30之上形成種晶層40。接下來，如圖14中所示，藉由使用一或多個微影操作及蝕刻操作將種晶層40圖案化成多個經圖案化之種晶層45。微影操作包括UV微影、DUV微影、EUV微影、電子束微影，且蝕刻操作包括電漿乾式蝕刻。經圖案化之種晶層45對應於隨後形成之FET之閘電極。在一些實施例中，經圖案化之種晶層45具有線形形狀。經圖案化之種晶層45之寬度在一些實施例中在自約5nm至約500nm之範圍中，且在其他實施例中在自約20nm至約200nm之範圍中。
隨後，如圖15至圖18中所示，執行結晶製程以使半導體層30結晶。結晶製程包括熱退火。在一些實施例中，熱退火包括使用奈秒雷射之雷射退火製程，該奈秒雷射對種晶層透明。在其他實施例中，熱退火包括在自約350℃至450℃之範圍中之溫度下的低溫退火。
如圖16及圖17中所示，半導體層30開始自經圖案化之種晶層45的底部(對應於隨後形成之FET的通道區域)結晶為晶體模板。藉由繼續熱退火製程，半導體層30之已結晶部分35橫向地擴展至源極/汲極區域中，如圖17中所示。
如圖18中所示，已結晶之半導體層35的前部中之每一者與已結晶之半導體層35的相鄰前部會合，從而形成晶界37。
隨後，如圖19中所示，在經圖案化之種晶層45之相對側面上形成側壁間隔物50。藉由使用CVD或其他合 適方法保形地形成用於側壁間隔物50之絕緣材料的毯覆層。以保形方式來沉積毯覆層，以使得該毯覆層經形成而在經圖案化之種晶層45的垂直表面(諸如，側壁)、水平表面及頂部上具有大體上相等之厚度。在一些實施例中，將毯覆層沉積至自約2nm至約30nm之範圍中的厚度。在一個實施例中，毯覆層之絕緣材料不同於經圖案化之種晶層45的材料，且由基於氮化矽之材料製成，諸如，氮化矽、SiON、SiOCN或SICN及其組合。在一些實施例中，毯覆層(側壁間隔物50)由氮化矽製成。如圖8中所示，藉由各向異性蝕刻，在經圖案化之種晶層45之相對側面上形成側壁間隔物50。在閘極替代技術中，經圖案化之種晶層45充當虛設閘電極。
接著，如圖20中所示，形成源極區域及汲極區域。在一些實施例中，源極/汲極區域60包括一或多個磊晶半導體層。源極/汲極磊晶層60包括一或多層用於n通道FET之Si、SiP、SiC及SICP或用於p通道FET之Si、SiGe、Ge。對於P通道FET而言，亦可在源極/汲極區域中含有硼(B)。藉由使用CVD、ALD或MBE之磊晶生成方法來形成源極/汲極磊晶層50。在一些實施例中，藉由蝕刻使已結晶之半導體層35的源極/汲極區域凹陷，且接著在已結晶之半導體層35的凹陷源極/汲極區域之上形成源極/汲極磊晶層60。在其他實施例中，執行一或多個離子佈植製程，以將雜質引入已結晶之半導體層35的源極/汲極區域中。在一些實施例中，源極/汲極磊晶層60完全地填充相鄰虛設閘電極 (經圖案化之種晶層45)之間的空間，且在其他實施例中，源極/汲極磊晶層60僅部分地填充相鄰虛設閘電極之間的空間。
接著，在源極/汲極磊晶層60及經圖案化之種晶層45之上形成第一層間介電質(ILD)層65。用於第一ILD層65之材料包括化合物，該等化合物包括Si、O、C及/或H，諸如，氧化矽、SiCOH及SiOC。可將諸如聚合物之有機材料用於第一ILD層65。在形成了第一ILD層65之後，執行平坦化操作(諸如，CMP)，以使得經圖案化之種晶層45的頂部被暴露，如圖21中所示。在一些實施例中，經圖案化之種晶層45充當CMP終止層。在一些實施例中，在第一ILD層65形成之前，形成接觸蝕刻終止層，諸如，氮化矽層或氧氮化矽層。
接著，移除經圖案化之種晶層45，藉此形成閘極空間47，如圖22中所示。可使用電漿乾式蝕刻及/或濕式蝕刻來移除經圖案化之種晶層45。
在移除了經圖案化之種晶層45之後，在閘極空間47中之每一者中形成閘極介電層70及閘電極75，如圖23中所示。在一些實施例中，閘極介電層70包括一或多層介電材料，諸如，氧化矽、氮化矽或高k介電材料、其他合適介電材料及/或其組合。高k介電材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料，及/或其組合。在一些實施例中，閘極 介電層70包括藉由使用化學氧化形成於通道層35與介電材料之間的界面層。可藉由CVD、ALD或任何合適方法形成閘極介電層70。在一個實施例中，使用諸如ALD之高度保形沉積製程形成閘極介電層70，以便確保形成在每一通道層周圍具有均勻厚度的閘極介電層。在一個實施例中，閘極介電層70之厚度在自約1nm至約10nm之範圍中。
隨後，在閘極介電層70上形成閘電極層75。閘電極層75包括一或多層導電材料，諸如，多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金屬合金、其他合適材料及/或其組合。可藉由CVD、ALD、電鍍或其他合適方法形成閘電極層75。用於閘極介電層70及閘電極層75之金屬亦被沉積在第一ILD層65之上表面之上。接著藉由使用例如CMP來平坦化形成於ILD層65之上的用於閘電極層之材料，直至露出ILD層65之頂表面為止。在一些實施例中，在平坦化操作之後，金屬閘電極層75凹陷且在凹陷閘電極層之上形成覆蓋絕緣層(未示出)。該覆蓋絕緣層包括一或多層基於氮化矽之材料，諸如，氮化矽。可藉由沉積絕緣材料繼之以平坦化操作來形成覆蓋絕緣層。
在本揭示案之某些實施例中，將一或多個功函數調整層(未示出)插入閘極介電層70與閘電極層75之間。功函數調整層由導電材料製成，諸如，單層TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或該等材料中之兩者或兩者以上的多層。對於n 通道FET而言，將TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中之一或多者用作功函數調整層，且對於p通道FET而言，將TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調整層。可藉由ALD、PVD、CVD、電子束蒸鍍或其他合適製程來形成功函數調整層。另外，可針對可使用不同金屬層之n通道FET及p通道FET單獨地形成功函數調整層。
另外，類似於圖13A，第二ILD層形成於第一ILD層之上，且穿過第二ILD層或第二ILD層與第一ILD層之導電接觸件經形成而接觸閘電極及源極/汲極磊晶層。
在其他實施例中，在已結晶之半導體層35的前部中之每一者與已結晶之半導體層35的相鄰前部會合之前，結晶製程終止。在此情形下，未結晶之半導體層30的部分保持在相鄰FET之間。
應理解，FET經受進一步CMOS製程，以形成各種特徵，諸如，接觸點/通孔、互連金屬層、介電層、鈍化層，等等。
圖24至圖36A繪示根據本揭示案之實施例的製造半導體FET裝置之各個階段。應理解，可在由圖24至圖36A所示之操作之前、在其期間以及在其之後提供額外操作，且可替代或消除以下所述之操作中的一些而獲得該方法之額外實施例。操作/製程之次序可互換。
類似於圖1，在設置於基板10之上的介電層20之上形成半導體層30，如圖25中所示。接著，類似於圖2， 在半導體層30之上形成種晶層40’，如圖25中所示。在一些實施例中，種晶層40’由金屬氧化物製成，該金屬氧化物具有在沉積時結晶之性質或具有在約350℃至約450℃之低溫退火下結晶之性質。在某些實施例中，種晶層40’由氧化鎂(MgO)製成。在一些實施例中，MgO種晶層40’為單晶的。在其他實施例中，MgO種晶層40’為多晶的或具有單晶之多個晶疇。可藉由CVD、原子層沉積(ALD)、物理氣相沉積(包括濺射)或任何其他合適之膜形成方法來形成種晶層40’。種晶層40’之厚度在一些實施例中在自約1nm至約100nm之範圍中，且在其他實施例中在自約2nm至約20nm之範圍中。在某些實施例中，種晶層40’之厚度在自約1nm至約10nm之範圍中。
接著，如圖26中所示，在種晶層40’之上形成虛設閘極層90。在一些實施例中，虛設閘極層90由多晶矽或非晶矽製成。亦可使用可相對於ILD層及側壁間隔物選擇性地移除之其他半導體材料或介電材料。虛設閘極層90之厚度在一些實施例中在自約50nm至約500nm之範圍中，且在其他實施例中在自約100nm至200nm之範圍中。可藉由CVD、原子層沉積(ALD)、物理氣相沉積(包括濺射)或任何其他合適之膜形成方法來形成虛設閘極層90。
接下來，如圖27中所示，藉由使用一或多個微影操作及蝕刻操作將虛設閘極層90及種晶層40’圖案化成多個經圖案化之虛設閘極層95及經圖案化之種晶層45’。微影操作包括UV微影、DUV微影、EUV微影、電子束微影， 且蝕刻操作包括電漿乾式蝕刻。經圖案化之虛設閘極層95及經圖案化之種晶層45’對應於隨後形成之FET的閘電極。在一些實施例中，經圖案化之虛設閘極層95及經圖案化之種晶層45’具有線形形狀。經圖案化之虛設閘極層95及經圖案化之種晶層45’之寬度在一些實施例中在自約5nm至約500nm之範圍中，且在其他實施例中在自約20nm至約200nm之範圍中。
隨後，如圖28至圖31中所示，執行結晶製程以使半導體層30結晶。結晶製程包括熱退火。在一些實施例中，熱退火包括使用奈秒雷射之雷射退火製程，該奈秒雷射對種晶層透明。在其他實施例中，熱退火包括在自約350℃至450℃之範圍中之溫度下的低溫退火。
如圖29及圖30中所示，半導體層30開始自經圖案化之種晶層45’的底部(對應於隨後形成之FET的通道區域)結晶為晶體模板。藉由繼續熱退火製程，半導體層30之已結晶部分35橫向地擴展至源極/汲極區域中，如圖30中所示。
如圖31中所示，已結晶之半導體層35的前部中之每一者與已結晶之半導體層35的相鄰前部會合，從而形成晶界37。
隨後，如圖32中所示，在經圖案化之虛設閘極層95及經圖案化之種晶層45’之相對側面上形成側壁間隔物50。藉由使用CVD或其他合適方法保形地形成用於側壁間隔物50之絕緣材料的毯覆層。以保形方式來沉積毯覆 層，以使得該毯覆層經形成而在經圖案化之虛設閘極層95及經圖案化之種晶層45’的垂直表面(諸如，側壁)、水平表面及頂部上具有大體上相等之厚度。在一些實施例中，將毯覆層沉積至自約2nm至約30nm之範圍中的厚度。在一個實施例中，毯覆層之絕緣材料不同於經圖案化之虛設閘極層95及經圖案化之種晶層45’的材料，且由基於氮化矽之材料製成，諸如，氮化矽、SiON、SiOCN或SICN及其組合。在一些實施例中，毯覆層(側壁間隔物50)由氮化矽製成。如圖8中所示，藉由各向異性蝕刻，在經圖案化之虛設閘極層95及經圖案化之種晶層45’之相對側面上形成側壁間隔物50。在閘極替代技術中，經圖案化之虛設閘極層95及經圖案化之種晶層45’充當虛設閘電極。
接著，如圖33中所示，形成源極區域及汲極區域。在一些實施例中，源極/汲極區域60包括一或多個磊晶半導體層。源極/汲極磊晶層60包括一或多層用於n通道FET之Si、SiP、SiC及SICP或用於p通道FET之Si、SiGe、Ge。對於P通道FET而言，亦可在源極/汲極區域中含有硼(B)。藉由使用CVD、ALD或MBE之磊晶生成方法來形成源極/汲極磊晶層50。在一些實施例中，藉由蝕刻使已結晶之半導體層35的源極/汲極區域凹陷，且接著在已結晶之半導體層35的凹陷源極/汲極區域之上形成源極/汲極磊晶層60。在其他實施例中，執行一或多個離子佈植製程，以將雜質引入已結晶之半導體層35的源極/汲極區域中。在一些實施例中，源極/汲極磊晶層60完全地填充相鄰虛設閘電極 (經圖案化之虛設閘極層95及經圖案化之種晶層45’)之間的空間，且在其他實施例中，源極/汲極磊晶層60僅部分地填充相鄰虛設閘電極之間的空間。
接著，在源極/汲極磊晶層60以及經圖案化之虛設閘極層95及經圖案化之種晶層45’之上形成第一層間介電質(ILD)層65。用於第一ILD層65之材料包括化合物，該等化合物包括Si、O、C及/或H，諸如，氧化矽、SiCOH及SiOC。可將諸如聚合物之有機材料用於第一ILD層65。在形成了第一ILD層65之後，執行平坦化操作(諸如，CMP)，以使得經圖案化之虛設閘極層95及經圖案化之種晶層45’的頂部被暴露，如圖34中所示。在一些實施例中，經圖案化之虛設閘極層95充當CMP終止層。在一些實施例中，在第一ILD層65形成之前，形成接觸蝕刻終止層，諸如，氮化矽層或氧氮化矽層。
接著，移除經圖案化之虛設閘極層95及經圖案化之種晶層45’，藉此形成閘極空間47，如圖35中所示。可使用電漿乾式蝕刻及/或濕式蝕刻來移除經圖案化之虛設閘極層95及經圖案化之種晶層45’。當經圖案化之虛設閘極層95為多晶矽或非晶矽時，可使用諸如四甲基氫氧化銨(tetramethylammonium hydroxide；TMAH)溶液之濕蝕刻劑來選擇性地移除虛設閘極層。其後使用電漿乾式蝕刻及/或濕式蝕刻來移除經圖案化之種晶層45’。
在移除了經圖案化之虛設閘極層95及經圖案化之種晶層45’之後，在閘極空間47中之每一者中形成閘極 介電層70及閘電極75，如圖36A中所示。在一些實施例中，閘極介電層70包括一或多層介電材料，諸如，氧化矽、氮化矽或高k介電材料、其他合適介電材料及/或其組合。高k介電材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料，及/或其組合。在一些實施例中，閘極介電層70包括藉由使用化學氧化形成於通道層35與介電材料之間的界面層。可藉由CVD、ALD或任何合適方法形成閘極介電層70。在一個實施例中，使用諸如ALD之高度保形沉積製程形成閘極介電層70，以便確保形成在每一通道層周圍具有均勻厚度的閘極介電層。在一個實施例中，閘極介電層70之厚度在自約1nm至約10nm之範圍中。
隨後，在閘極介電層70上形成閘電極層75。閘電極層70包括一或多層導電材料，諸如，多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金屬合金、其他合適材料及/或其組合。可藉由CVD、ALD、電鍍或其他合適方法形成閘電極層75。用於閘極介電層70及閘電極層75之金屬亦被沉積在第一ILD層65之上表面之上。接著藉由使用例如CMP來平坦化形成於ILD層65之上的用於閘電極層之材料，直至露出ILD層65之頂表面為止。在一些實施例中，在平坦化操作之後，金屬閘電極層75凹陷且在凹陷閘電極層之上形成覆蓋絕緣層(未示出)。該覆蓋絕緣層包括一或 多層基於氮化矽之材料，諸如，氮化矽。可藉由沉積絕緣材料繼之以平坦化操作來形成覆蓋絕緣層。
在本揭示案之某些實施例中，將一或多個功函數調整層(未示出)插入閘極介電層70與閘電極層75之間。功函數調整層由導電材料製成，諸如，單層TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或該等材料中之兩者或兩者以上的多層。對於n通道FET而言，將TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中之一或多者用作功函數調整層；且對於p通道FET而言，將TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調整層。可藉由ALD、PVD、CVD、電子束蒸鍍或其他合適製程來形成功函數調整層。另外，可針對可使用不同金屬層之n通道FET及p通道FET單獨地形成功函數調整層。
另外，類似於圖13A，第二ILD層形成於第一ILD層之上，且穿過第二ILD層或第二ILD層與第一ILD層之導電接觸件經形成而接觸閘電極及源極/汲極磊晶層。如圖13A中所示，在一些實施例中，製造之FET為薄膜電晶體(TFT)。
在其他實施例中，在已結晶之半導體層35的前部中之每一者與已結晶之半導體層35的相鄰前部會合之前，結晶製程終止。在此情形下，未結晶之半導體層30的部分保持在相鄰FET之間，如圖36B中所示。
應理解，FET經受進一步CMOS製程，以形成各種特徵，諸如，接觸點/通孔、互連金屬層、介電層、鈍化層，等等。
圖37繪示根據本揭示案之實施例之半導體裝置的橫截面圖。如圖37中所示，在基板之上形成下層元件100。下層元件100包括一或多個鰭式場效應電晶體(fin field effect transistor；FinFET)、環繞式閘極FET(gate-all-around FET；GAA FET)、平面FET、垂直FET或任何其他電子裝置。圖37亦繪示設置於下層元件100之上的上層元件200。在一些實施例中，將一或多個ILD層、金屬佈線層及/或通孔接觸件設置在下層元件100與上層元件200之間。在一些實施例中，上層元件200包括藉由本揭示案之前述實施例製造的一或多個FET。
本文所述之各種實施例或實例提供了勝於現有技術之各種優勢。舉例而言，在本揭示案中，使用形成於非晶體半導體層(頂部種晶層)上的經圖案化之種晶層來執行非晶體半導體層之結晶製程。因為非晶體半導體層之結晶是自經圖案化之種晶層的底部開始，且將經圖案化之種晶層用作虛設閘極，所以有可能將具有較高結晶品質的最初結晶部分(更靠近種晶層)用作FET之通道區域。換言之，可藉由自對準方式將最佳結晶部分用作通道區域。另外，藉由將種晶層作為虛設閘極用於閘極替代製程，有可能抑制製造半導體裝置之操作步驟的增加。本揭示案之操作與半導體製造之後端工序製程相容。
應將理解，未必已在本文中論述了所有優勢，對於所有實施例或實例而言無特定優勢為必需，且其他實施例或實例可提供不同優勢。
根據本揭示案之一態樣，在一種製造半導體裝置之方法中，在設置在基板之上的介電層上形成半導體層。在半導體層上形成種晶層。將種晶層圖案化成經圖案化之種晶層。使用經圖案化之種晶層作為結晶之種晶來對半導體層執行結晶操作，藉此形成已結晶之半導體層。在前述及以下實施例中之一或多者中，種晶層為MgO。在前述及以下實施例中之一或多者中，半導體層為非晶或多晶晶體。在前述及以下實施例中之一或多者中，半導體層為Si、SiGe及Ge中之一者。在前述及以下實施例中之一或多者中，種晶層之厚度在自1nm至10nm之範圍中。在前述及以下實施例中之一或多者中，半導體層之厚度在自10nm至50nm之範圍中。在前述及以下實施例中之一或多者中，結晶操作包括在自350℃至450℃之溫度下的熱退火，或雷射退火。在前述及以下實施例中之一或多者中，在經圖案化之種晶層之相對側面上形成多個側壁間隔物。形成源極/汲極結構。在這些側壁間隔物、經圖案化之種晶層及源極/汲極結構之上形成層間介電質(ILD)層。在形成ILD層之後，移除經圖案化之種晶層，藉此形成閘極空間。在閘極空間中形成閘極介電層及閘電極層。
根據本揭示案之另一態樣，在一種製造半導體裝置之方法中，在設置在基板之上的介電層上形成半導體 層。在該半導體層上形成種晶層。將種晶層圖案化成經圖案化之種晶層。使用這些經圖案化之種晶層作為結晶之種晶來對半導體層執行結晶操作，藉此形成多個已結晶之半導體層。在前述及以下實施例中之一或多者中，種晶層為MgO。在前述及以下實施例中之一或多者中，半導體層為Si、SiGe及Ge中之一者的非晶或多晶晶體。在前述及以下實施例中之一或多者中，結晶操作包括在自350℃至450℃之溫度下的熱退火，或雷射退火。在前述及以下實施例中之一或多者中，在經圖案化之種晶層之相對側面上形成多個側壁間隔物。形成源極/汲極結構。在這些側壁間隔物、經圖案化之種晶層及源極/汲極結構之上形成層間介電質(ILD)層。在形成該ILD層之後，移除經圖案化之種晶層，藉此形成多個閘極空間。在這些閘極空間中之每一者中形成閘極介電層及閘電極層。在前述及以下實施例中之一或多者中，執行結晶操作，以使得在種晶層中之一者下方的已結晶半導體層之前部與在鄰近種晶層中之該者的種晶層中之另一者下方的已結晶半導體層之前部會合，藉此形成晶界。在前述及以下實施例中之一或多者中，在種晶層中之一者下方的已結晶半導體層之前部與在鄰近種晶層中之該者的種晶層中之另一者下方的已結晶半導體層之前部會合之前，終止結晶操作。
根據本揭示案之另一態樣，在一種製造半導體裝置之方法中，在設置在基板之上的介電層上形成半導體層。在該半導體層上形成種晶層。在種晶層上形成虛設閘極層。將虛設閘極層及種晶層形成為經圖案化之虛設閘極層及 經圖案化之種晶層。使用經圖案化之種晶層作為結晶之種晶來對半導體層執行結晶操作，藉此形成已結晶之半導體層。在前述及以下實施例中之一或多者中，虛設閘極層為Si、SiGe及Ge中之一者的非晶或多晶晶體。在前述及以下實施例中之一或多者中，虛設閘極層之厚度在自50nm至200nm之範圍中。在前述及以下實施例中之一或多者中，種晶層為MgO。在前述及以下實施例中之一或多者中，在經圖案化之虛設閘極層及經圖案化之種晶層之相對側面上形成多個側壁間隔物。形成源極/汲極結構。在這些側壁間隔物、經圖案化之虛設閘極層及源極/汲極結構之上形成層間介電質(ILD)層。在形成該ILD層之後，移除經圖案化之虛設閘極層及經圖案化之種晶層，藉此形成閘極空間。在閘極空間中形成閘極介電層及閘電極層。
根據本揭示案之一個態樣，一種半導體裝置包括通道，通道形成為設置在介電層上之半導體層的部分；設置在通道之上的閘極介電層；設置在閘極介電層之上的閘電極層；設置在閘電極層之相對側面上的多個側壁間隔物；以及源極及汲極。半導體層包括作為通道之晶體部分及非晶體部分。在前述及以下實施例中之一或多者中，半導體裝置進一步包括被介電層覆蓋之一或多個電晶體。在前述及以下實施例中之一或多者中，一或多個電晶體包括鰭式場效應電晶體。在前述及以下實施例中之一或多者中，半導體層由Si、SiGe及Ge中之一者製成。在前述及以下實施例中之一或多者中，半導體層之厚度在自10nm至50nm之範圍中。
根據本揭示案之另一態樣，一種半導體裝置包括設置於基板上之電子裝置、設置在該電子裝置之上的一或多個介電層、設置在一或多個介電層之最上層上的薄膜電晶體。這些薄膜電晶體中之每一者包括通道，通道形成為設置在最上層上之半導體層的部分；設置在通道之上的閘極介電層；設置在閘極介電層之上的閘電極層；設置在閘電極層之相對側面上的多個側壁間隔物；以及源極及汲極。半導體層為單晶，且晶界存在於薄膜電晶體中之一者的半導體層與鄰近薄膜電晶體中之該者的薄膜電晶體中之另一者的半導體層之間。在前述及以下實施例中之一或多者中，電子裝置為電晶體。在前述及以下實施例中之一或多者中，電晶體為鰭式場效應電晶體及環繞式閘極電晶體中之一者。在前述及以下實施例中之一或多者中，半導體層由Si、SiGe及Ge中之一者製成。在前述及以下實施例中之一或多者中，最上層由氧化矽製成。在前述及以下實施例中之一或多者中，半導體層之厚度在自10nm至50nm之範圍中。在前述及以下實施例中之一或多者中，源極及汲極包括磊晶半導體層。在前述及以下實施例中之一或多者中，磊晶半導體層與薄膜電晶體中之一者的側壁間隔物中之一者以及薄膜電晶體中之另一者的側壁間隔物中之一者接觸。
根據本揭示案之另一態樣，一種半導體裝置包括設置於基板上之電子裝置、設置在電子裝置之上的一或多個介電層，及設置在一或多個介電層之最上層上的薄膜電晶體。這些薄膜電晶體中之每一者包括通道，通道形成為設置 在最上層上之半導體層的部分；設置在通道之上的閘極介電層；設置在閘極介電層之上的閘電極層；設置在閘電極層之相對側面上的多個側壁間隔物；以及源極及汲極。通道為單晶，且由與半導體層相同之材料製成的非晶半導體層存在於薄膜電晶體中之一者的半導體層與鄰近薄膜電晶體之該者的薄膜電晶體之另一者的半導體層之間。在前述及以下實施例中之一或多者中，電子裝置為電晶體。在前述及以下實施例中之一或多者中，電晶體為鰭式場效應電晶體及環繞式閘極電晶體中之一者。在前述及以下實施例中之一或多者中，半導體層由Si、SiGe及Ge中之一者製成。在前述及以下實施例中之一或多者中，半導體層之厚度在自10nm至50nm之範圍中。在前述及以下實施例中之一或多者中，源極及汲極包括磊晶半導體層。在前述及以下實施例中之一或多者中，磊晶半導體層與薄膜電晶體中之一者的側壁間隔物中之一者以及薄膜電晶體中之另一者的側壁間隔物中之一者接觸。
前文概述了若干實施例或實例之特徵，使得熟習此項技藝者可較佳理解本揭示案之態樣。熟習此項技藝者應瞭解，他們可容易地使用本揭示案作為設計或修改用於實現相同目的及/或達成本文中所介紹之實施例或實例之相同優勢的其他製程及結構之基礎。熟習此項技藝者亦應認識到，此等等效構造不脫離本揭示案之精神及範疇，且他們可在不脫離本揭示案之精神及範疇的情況下於本文中進行各種改變、代替及修改。
10:基板
20:介電層
35:已結晶部分
50:側壁間隔物
60:源極/汲極區域
65:第一層間介電質(ILD)層
70:閘極介電層
75:閘電極
80:第二ILD
85:導電接觸件

Claims (10)

  1. 一種製造半導體裝置之方法，該方法包括：在設置於一基板之上的一介電層上形成一半導體層；在該半導體層上形成一種晶層；將該種晶層圖案化成一經圖案化之種晶層；使用該經圖案化之種晶層作為結晶之一種晶來對該半導體層執行一結晶操作，藉此形成一已結晶之半導體層；以及在該經圖案化之種晶層之相對側面上形成多個側壁間隔物。
  2. 如請求項1所述之方法，其中該種晶層為MgO。
  3. 如請求項1所述之方法，其中該半導體層為非晶或多晶晶體。
  4. 如請求項1所述之方法，進一步包括：形成一源極/汲極結構；在該等側壁間隔物、該經圖案化之種晶層及該源極/汲極結構之上形成一層間介電質(ILD)層；在形成該ILD層之後，移除該經圖案化之種晶層，藉此形成一閘極空間；以及在該閘極空間中形成一閘極介電層及一閘電極層。
  5. 一種製造半導體裝置之方法，該方法包括：在設置於一基板之上的一介電層上形成一非晶或一多晶的半導體層；在該半導體層上形成一種晶層；將該種晶層圖案化成多個經圖案化之種晶層；使用該等經圖案化之種晶層作為結晶之一種晶來對該半導體層執行一結晶操作，藉此在該介電層之上形成多個單晶半導體層；以及在該等經圖案化之種晶層之相對側面上形成多個側壁間隔物。
  6. 如請求項5所述之方法，其中該結晶操作包括在自350℃至450℃之一溫度下的一熱退火，或一雷射退火。
  7. 如請求項5所述之方法，進一步包括：形成一源極/汲極結構；在該等側壁間隔物、該等經圖案化之種晶層及該源極/汲極結構之上形成一層間介電質(ILD)層；在形成該ILD層之後，移除該等經圖案化之種晶層，藉此形成多個閘極空間；以及在該等閘極空間中之每一者中形成一閘極介電層及一閘電極層。
  8. 如請求項5所述之方法，其中執行該結晶操作，以使得在該等種晶層中之一者下方的一已結晶半導體層之一前部與在鄰近該等種晶層中之該者的該等種晶層中之另一者下方的一已結晶半導體層之一前部會合，藉此形成一晶界。
  9. 如請求項5所述之方法，其中於在該等種晶層中之一者下方的一已結晶半導體層之一前部與在鄰近該等種晶層中之該者的該等種晶層中之另一者下方的一已結晶半導體層之一前部會合之前，終止該結晶操作。
  10. 一種半導體裝置，包括：一電子裝置，該電子裝置被設置在一基板上；一或多個介電層，該一或多個介電層被設置在該電子裝置之上；以及多個薄膜電晶體，該等薄膜電晶體被設置在該一或多個介電層中之一最上層上，其中：該等薄膜電晶體中之每一者包括：一通道，該通道形成為設置在該最上層上之一半導體層之一部分；一閘極介電層，該閘極介電層被設置在該通道之上；一閘電極層，該閘電極層被設置在該閘極介電層之上； 多個側壁間隔物，該等側壁間隔物被設置在該閘電極層之相對側面上；以及一源極及一汲極，該通道為單晶，一晶界存在於該等薄膜電晶體中之一者的該半導體層與鄰近該等薄膜電晶體中之該者的該等薄膜電晶體中之另一者的該半導體層之間。
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