CN110970360B - 半导体装置和制造半导体装置的方法 - Google Patents

半导体装置和制造半导体装置的方法 Download PDF

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CN110970360B
CN110970360B CN201910916825.0A CN201910916825A CN110970360B CN 110970360 B CN110970360 B CN 110970360B CN 201910916825 A CN201910916825 A CN 201910916825A CN 110970360 B CN110970360 B CN 110970360B
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layer
semiconductor
seed
semiconductor layer
gate
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CN110970360A (zh
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乔治凡利亚尼提斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置和制造半导体装置的方法。在一种制造半导体装置的方法中，在基板之上形成单晶氧化物层。在形成单晶氧化物层之后，形成用以限定活性区域的隔离结构。在活性区域中于单晶氧化物层之上形成栅极结构。形成源极/漏极结构。

Description

半导体装置和制造半导体装置的方法
技术领域
本揭示是关于一种半导体装置和一种制造半导体装置的方法。
背景技术
经常实施传统的互补金属氧化物半导体(complementary metal-oxide-semiconductor；CMOS)技术以在单个集成电路(integrated-circuit；IC)晶片上的大致同一层级处制造大量半导体元件，诸如，金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor；MOSFET)及双极接面晶体管(bipolarjunction transistor；BJT)。在先进IC晶片中，将晶体管设置在多个层上。
发明内容
根据本揭示案的一态样，在一种制造半导体装置的方法中，在设置于基板之上的介电层上形成半导体层；在半导体层上形成种晶层；将种晶层图案化成经图案化的种晶层；以及使用经图案化的种晶层作为结晶的种晶来对半导体层执行结晶操作，借此形成已结晶的半导体层。
根据本揭示案的一态样，在一种制造半导体装置的方法中，在设置于基板之上的介电层上形成非晶或多晶的半导体层；在半导体层上形成种晶层；将种晶层图案化成多个经图案化的种晶层；以及使用这些经图案化的种晶层作为结晶的种晶来对半导体层执行结晶操作，借此在介电层之上形成多个单晶半导体层。
根据本揭示案的一态样，一种半导体装置包括：电子装置、一或多个介电层及多个薄膜晶体管。电子装置被设置在基板上。一或多个介电层被设置在电子装置之上。这些薄膜晶体管被设置在一或多个介电层中的一最上层上。这些薄膜晶体管中的每一者包括：通道、栅极介电层、栅电极层、多个侧壁间隔物，以及源极及漏极。通道形成为设置在最上层上的一半导体层的一部分。栅极介电层被设置在通道之上。栅电极层被设置在栅极介电层之上。这些侧壁间隔物被设置在栅电极层的相对侧面上。通道为单晶。晶界存在于这些薄膜晶体管中的一者的半导体层与邻近这些薄膜晶体管中的该者的这些薄膜晶体管中的另一者的半导体层之间。
附图说明
本揭示案当结合附图阅读时将自以下详细描述中最佳地理解。应强调，根据工业上的标准实务，各种特征并未按比例绘制且仅用于说明目的。事实上，为了论述清楚，可任意地增大或减小各种特征的尺寸。
图1绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图2绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图3绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图4绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图5绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图6绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图7绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图8绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图9绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图10绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图11绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图12绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图13A及图13B绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段中的一者；
图14绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图15绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图16绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图17绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图18绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图19绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图20绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图21绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图22绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图23绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图24绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图25绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图26绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图27绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图28绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图29绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图30绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图31绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图32绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图33绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图34绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图35绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图36A绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图36B绘示根据本揭示案的另一实施例的制造半导体FET装置的各个阶段中的一者；
图37绘示根据本揭示案的实施例的半导体FET装置的横截面图。
【符号说明】
10 基板
20 介电层
30 半导体层
35 已结晶部分
37 晶界
40 种晶层
45 经图案化的种晶层
47 栅极空间
50 侧壁间隔物
60 源极/漏极区域
65 第一层间介电质(ILD)层
70 栅极介电层
75 栅电极
80 第二ILD
85 导电接触件
90 虚设栅极层
95 经图案化的虚设栅极层
100 下层元件
200 上层元件
具体实施方式
应理解，以下揭示内容提供了用于实施本发明的不同特征的许多不同实施例或实例。以下描述元件及布置的特定实施例或实例以简化本揭示案。当然，此些仅为实例，且并不意欲为限制性的。举例而言，元件的尺寸并不限于所揭示的范围或值，而可视制程条件及/或装置的所需性质而定。此外，在如下描述中的第一特征在第二特征之上或在第二特征上的形成可包括其中第一特征与第二特征形成为直接接触的实施例，且亦可包括其中额外特征可形成为插入第一特征与第二特征之间而使得第一特征与第二特征可不直接接触的实施例。为了简化及清楚起见，可以不同比例任意地绘制各种特征。
另外，为了便于描述起见，可在本文中使用诸如“在……之下”、“在……下方”、“下部”、“在……上方”、“上部”的空间相对术语及其类似术语，以描述如诸图中所绘示的一个元件或特征与另一(其他)元件或特征的关系。除了诸图中所描绘的定向以外，这些空间相对术语意欲涵盖装置在使用或操作中的不同定向。设备可以其他方式定向(旋转90度或以其他定向)，且可同样相应地解释本文中所使用的空间相对描述词。另外，术语“由……制成”可意谓“包括”抑或“由……组成”。在本揭示案中，词语“A、B及C中的一者”意谓“A、B及/或C”(A、B、C、A与B、A与C、B与C，或者A、B及C)，且并不意谓来自A的一个元件、来自B的一个元件以及来自C的一个元件，除非另有描述。
对于后端工序(back-end of line)中的晶体管制造制程而言，存在用以在非晶层(诸如，氧化硅层)之上形成用于晶体管通道的高品质结晶半导体层的关键制程。在氧化硅层上制造结晶半导体的方法包括：(a)生长呈非晶态的半导体膜，接着以高温退火；及(b)通过使用自结晶Si基板生长的结晶种晶来生长半导体层。这两种方法皆可能不适合用于后端工序制程，因为：对于方法(a)而言，存在热预算的限制，例如，小于450℃；且对于方法(b)而言，结晶种晶层需要穿过若干金属层及层间介电层。
本揭示案提供一种用以在非晶(非晶体)介电层上形成高品质结晶半导体层的方法。本揭示案亦提供一种用以在多晶或非晶半导体层转换为具有较高结晶度的结晶层的区域中制造晶体管的自对准方法。
在以下实施例中，除非另有描述，否则一个实施例的材料、配置、尺寸及/或制程可用于另一实施例中，且可省略其详细描述。
图1至图13A绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段。应理解，可在由图1至图13A所示的操作之前、在其期间以及在其之后提供额外操作，且可替代或消除以下所述的操作中的一些而获得该方法的额外实施例。操作/制程的次序可互换。另外，在本揭示案中，可互换地使用源极及漏极，且源极/漏极指代源极及漏极中的至少一者。
如图1中所示，提供基板10。在一些实施例中，基板10至少在其表面部分上包括单晶半导体层。基板10可包括单晶半导体材料，诸如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在某些实施例中，基板10由结晶Si、SiGe或Ge制成。在一些实施例中，基板10可在其表面区域中包括一或多个缓冲层(未示出)。缓冲层可用以逐渐地使晶格常数自基板的晶格常数改变为源极/漏极区域的晶格常数。缓冲层可由磊晶生成的单晶半导体材料形成，诸如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP。在特定实施例中，基板10包括磊晶生成于硅基板10上的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可自最底部缓冲层的30原子百分比锗增大至最顶部缓冲层的70原子百分比锗。
另外，如图1中所示，在基板10之上形成一或多个介电层20。在一些实施例中，在基板10上形成诸如晶体管、记忆体(例如，动态随机存取记忆体(dynamic random accessmemory；DRAM)、静态RAM、磁性MRAM及/或相变RAM)的一或多个电子装置，且一或多个介电层20覆盖这些电子装置。另外，一或多个金属布线结构嵌入在介电层20中。用于介电层20的介电材料包括通过低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)、电浆CVD或可流动CVD或任何其他合适的膜形成方法而形成的氧化硅、氮化硅、氧氮化硅(SiON)、SiCN、氟掺杂的硅酸盐玻璃(fluorine-doped silicate glass；FSG)或低K介电材料。可在形成介电层20之后执行退火操作。在一些实施例中，执行诸如化学机械研磨(chemical mechanical polishing；CMP)方法及/或回蚀方法的平坦化操作，以使介电层20的表面变平。
仍参考图1，在介电层20之上形成作为通道半导体材料的半导体层30。在一些实施例中，用于半导体层30的半导体材料包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在某些实施例中，半导体层30由Si、SiGe或Ge制成。
在一些实施例中，通过CVD、ALD或任何其他合适的膜形成方法来形成半导体层30。在一些实施例中，在低于约450℃的温度下执行膜形成。在一些实施例中，在等于或高于约25℃的温度下执行膜形成。在一些实施例中，将Si2H6气体用作Si的源气体，且将Ge2H6气体用作Ge的源气体。在某些实施例中，替代于Ge2H6及/或Si2H6或除了Ge2H6及/或Si2H6以外，使用GeH4及/或SiH4。在一些实施例中，半导体层30为非晶的或多晶的。在一些实施例中，半导体层30适当地掺杂有杂质，诸如，P、As、Sb及/或B。这些杂质是在膜形成期间原位地掺杂，或在半导体层30形成之后通过离子布植或电浆掺杂进行掺杂。半导体层30的厚度在一些实施例中在自约5nm至约500nm的范围中，且在其他实施例中在自约10nm至约50nm的范围中。
接着，如图2中所示，在半导体层30之上形成种晶层40。在一些实施例中，无种晶层形成在半导体层30下方。在一些实施例中，种晶层40由金属氧化物制成，该金属氧化物具有在沉积时结晶的性质或在约300℃至约450℃的低温退火下结晶的性质。在某些实施例中，种晶层40由氧化镁(MgO)制成。在一些实施例中，MgO种晶层40为单晶的。在其他实施例中，MgO种晶层40为多晶的或具有单晶的多个晶畴。可通过CVD、原子层沉积(atomic layerdeposition；ALD)、物理气相沉积(包括溅射)或任何其他合适的膜形成方法来形成种晶层40。种晶层40的厚度在一些实施例中在自约1nm至约100nm的范围中，且在其他实施例中在自约2nm至约20nm的范围中。在某些实施例中，种晶层40的厚度在自约1nm至约10nm的范围中。在其他实施例中，将HfO2、La2Hf2O7、Y2O3、SrTiO3及HfZrO2中的一者作为种晶层40。
接下来，如图3中所示，通过使用一或多个微影操作及蚀刻操作将种晶层40图案化成经图案化的种晶层45。微影操作包括紫外线(UV)微影、深UV(DUV)微影、极UV(EUV)微影、电子束(e-beam)微影，且蚀刻操作包括电浆干式蚀刻。经图案化的种晶层45对应于随后形成的FET的栅电极。因此，经图案化的种晶层45的宽度W1对应于FET的栅极长度，且经图案化的种晶层45具有对应于FET的栅电极的形状。在一些实施例中，经图案化的种晶层45具有线形形状。宽度W1在一些实施例中在自约5nm至约500nm的范围中，且在其他实施例中在自约20nm至约200nm的范围中。
随后，如图4至图7中所示，执行结晶制程以使半导体层30结晶。结晶制程包括热退火。在一些实施例中，热退火包括使用纳秒激光的激光退火制程，该纳秒激光对种晶层透明。在其他实施例中，热退火包括在自约350℃至450℃的范围中的温度下的低温退火。
如图5及图6中所示，半导体层30开始自经图案化的种晶层的底部(对应于随后形成的FET的通道区域)结晶为晶体模板。通过继续热退火制程，半导体层30的已结晶部分35横向地扩展至源极/漏极区域中，如图7中所示。在一些实施例中，整个半导体层30变成晶体。
随后，如图8中所示，在经图案化的种晶层45的相对侧面上形成侧壁间隔物50。通过使用CVD或其他合适方法保形地形成用于侧壁间隔物50的绝缘材料的毯覆层(blanketlayer)。以保形方式来沉积毯覆层，以使得该毯覆层经形成而在经图案化的种晶层45的垂直表面(诸如，侧壁)、水平表面及顶部上具有大体上相等的厚度。在一些实施例中，将毯覆层沉积至自约2nm至约30nm的范围中的厚度。在一个实施例中，毯覆层的绝缘材料不同于经图案化的种晶层45的材料，且由基于氮化硅的材料制成，诸如，氮化硅、SiON、SiOCN或SICN及其组合。在一些实施例中，毯覆层(侧壁间隔物50)由氮化硅制成。如图8中所示，通过各向异性蚀刻，在经图案化种晶层45的相对侧面上形成侧壁间隔物50。在栅极替代技术中，经图案化的种晶层45充当虚设栅电极。
接着，如图9中所示，形成源极区域及漏极区域。在一些实施例中，源极/漏极区域60包括一或多个磊晶半导体层。源极/漏极磊晶层60包括一或多层用于n通道FET的Si、SiP、SiC及SICP或用于p通道FET的Si、SiGe、Ge。对于P通道FET而言，亦可在源极/漏极区域中含有硼(B)。通过使用CVD、ALD或MBE的磊晶生成方法来形成源极/漏极磊晶层50。在一些实施例中，通过蚀刻使已结晶的半导体层35的源极/漏极区域凹陷，且接着在已结晶的半导体层35的凹陷源极/漏极区域之上形成源极/漏极磊晶层60。在其他实施例中，执行一或多个离子布植制程，以将杂质引入已结晶的半导体层35的源极/漏极区域中。
接着，在源极/漏极磊晶层60及经图案化的种晶层45之上形成第一层间介电质(interlayer dielectric；ILD)层65。用于第一ILD层65的材料包括化合物，这些化合物包括Si、O、C及/或H，诸如，氧化硅、SiCOH及SiOC。可将诸如聚合物的有机材料用于第一ILD层65。在形成了第一ILD层65之后，执行平坦化操作(诸如，CMP)，以使得经图案化的种晶层45的顶部被暴露，如图10中所示。在一些实施例中，经图案化的种晶层45充当CMP终止层。在一些实施例中，在第一ILD层65形成之前，形成接触蚀刻终止层，诸如，氮化硅层或氧氮化硅层。
接着，移除经图案化的种晶层45，借此形成栅极空间47，如图11中所示。可使用电浆干式蚀刻及/或湿式蚀刻来移除经图案化的种晶层45。
在移除了经图案化的种晶层45之后，在栅极空间47中形成栅极介电层70及栅电极75，如图12中所示。在一些实施例中，栅极介电层70包括一或多层介电材料，诸如，氧化硅、氮化硅或高k介电材料、其他合适介电材料及/或其组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料，及/或其组合。在一些实施例中，栅极介电层70包括通过使用化学氧化形成于通道层35与介电材料之间的界面层。可通过CVD、ALD或任何合适方法形成栅极介电层70。在一个实施例中，使用诸如ALD的高度保形沉积制程形成栅极介电层70，以便确保形成在每一通道层周围具有均匀厚度的栅极介电层。在一个实施例中，栅极介电层70的厚度在自约1nm至约10nm的范围中。
随后，在栅极介电层70上形成栅电极层75。栅电极层75包括一或多层导电材料，诸如，多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金属合金、其他合适材料及/或其组合。可通过CVD、ALD、电镀或其他合适方法形成栅电极层75。用于栅极介电层70及栅电极层75的金属亦被沉积在第一ILD层65的上表面之上。接着通过使用例如CMP来平坦化形成于ILD层65之上的用于栅电极层的材料，直至露出ILD层65的顶表面为止。在一些实施例中，在平坦化操作之后，金属栅电极层75凹陷且在凹陷栅电极层之上形成覆盖绝缘层(未示出)。该覆盖绝缘层包括一或多层基于氮化硅的材料，诸如，氮化硅。可通过沉积绝缘材料继之以平坦化操作来形成覆盖绝缘层。
在本揭示案的某些实施例中，将一或多个功函数调整层(未示出)插入栅极介电层70与栅电极层75之间。功函数调整层由导电材料制成，诸如，单层的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或这些材料中的两者或两者以上的多层。对于n通道FET而言，将TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中的一或多者用作功函数调整层，且对于p通道FET而言，将TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中的一或多者用作功函数调整层。可通过ALD、PVD、CVD、电子束蒸镀或其他合适制程来形成功函数调整层。另外，可针对可使用不同金属层的n通道FET及p通道FET单独地形成功函数调整层。
另外，如图13A中所示，第二ILD层80形成于第一ILD层65之上，且穿过第二ILD层80或第二ILD层与第一ILD层的导电接触件85经形成而接触栅电极75及源极/漏极磊晶层60。在第一ILD层及/或第二ILD层中形成接触开口。在接触开口中及在接触开口之上形成一或多层导电材料，且接着执行平坦化操作(诸如，CMP操作)以形成导电接触件85，如图13A中所示。在一些实施例中，导电接触件85包括衬垫层及主体层。该衬垫层为阻障层及/或胶(粘合)层。在一些实施例中，在源极/漏极磊晶层55上形成Ti层，且在Ti层上形成TiN或TaN层，作为衬垫层。该主体层包括一或多层Co、Ni、W、Ti、Ta、Cu及AI，或任何其他合适材料。
应理解，FET经受进一步CMOS制程，以形成各种特征，诸如，接触点/通孔、互连金属层、介电层、钝化层，等等。
在其他实施例中，如图13B中所示，当在必要区域(诸如，通道区域及源极/漏极区域)中形成了已结晶部分35时，结晶制程终止。因此，存在未结晶的半导体层30的部分，其为非晶晶体或多晶晶体。
图14至图23绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段。应理解，可在由图14至图23所示的操作之前、在其期间以及在其之后提供额外操作，且可替代或消除以下所述的操作中的一些而获得该方法的额外实施例。操作/制程的次序可互换。
类似于图1及图2，在半导体层30之上形成种晶层40。接下来，如图14中所示，通过使用一或多个微影操作及蚀刻操作将种晶层40图案化成多个经图案化的种晶层45。微影操作包括UV微影、DUV微影、EUV微影、电子束微影，且蚀刻操作包括电浆干式蚀刻。经图案化的种晶层45对应于随后形成的FET的栅电极。在一些实施例中，经图案化的种晶层45具有线形形状。经图案化的种晶层45的宽度在一些实施例中在自约5nm至约500nm的范围中，且在其他实施例中在自约20nm至约200nm的范围中。
随后，如图15至图18中所示，执行结晶制程以使半导体层30结晶。结晶制程包括热退火。在一些实施例中，热退火包括使用纳秒激光的激光退火制程，该纳秒激光对种晶层透明。在其他实施例中，热退火包括在自约350℃至450℃的范围中的温度下的低温退火。
如图16及图17中所示，半导体层30开始自经图案化的种晶层45的底部(对应于随后形成的FET的通道区域)结晶为晶体模板。通过继续热退火制程，半导体层30的已结晶部分35横向地扩展至源极/漏极区域中，如图17中所示。
如图18中所示，已结晶的半导体层35的前部中的每一者与已结晶的半导体层35的相邻前部会合，从而形成晶界37。
随后，如图19中所示，在经图案化的种晶层45的相对侧面上形成侧壁间隔物50。通过使用CVD或其他合适方法保形地形成用于侧壁间隔物50的绝缘材料的毯覆层。以保形方式来沉积毯覆层，以使得该毯覆层经形成而在经图案化的种晶层45的垂直表面(诸如，侧壁)、水平表面及顶部上具有大体上相等的厚度。在一些实施例中，将毯覆层沉积至自约2nm至约30nm的范围中的厚度。在一个实施例中，毯覆层的绝缘材料不同于经图案化的种晶层45的材料，且由基于氮化硅的材料制成，诸如，氮化硅、SiON、SiOCN或SICN及其组合。在一些实施例中，毯覆层(侧壁间隔物50)由氮化硅制成。如图8中所示，通过各向异性蚀刻，在经图案化的种晶层45的相对侧面上形成侧壁间隔物50。在栅极替代技术中，经图案化的种晶层45充当虚设栅电极。
接着，如图20中所示，形成源极区域及漏极区域。在一些实施例中，源极/漏极区域60包括一或多个磊晶半导体层。源极/漏极磊晶层60包括一或多层用于n通道FET的Si、SiP、SiC及SICP或用于p通道FET的Si、SiGe、Ge。对于P通道FET而言，亦可在源极/漏极区域中含有硼(B)。通过使用CVD、ALD或MBE的磊晶生成方法来形成源极/漏极磊晶层50。在一些实施例中，通过蚀刻使已结晶的半导体层35的源极/漏极区域凹陷，且接着在已结晶的半导体层35的凹陷源极/漏极区域之上形成源极/漏极磊晶层60。在其他实施例中，执行一或多个离子布植制程，以将杂质引入已结晶的半导体层35的源极/漏极区域中。在一些实施例中，源极/漏极磊晶层60完全地填充相邻虚设栅电极(经图案化的种晶层45)之间的空间，且在其他实施例中，源极/漏极磊晶层60仅部分地填充相邻虚设栅电极之间的空间。
接着，在源极/漏极磊晶层60及经图案化的种晶层45之上形成第一层间介电质(ILD)层65。用于第一ILD层65的材料包括化合物，这些化合物包括Si、O、C及/或H，诸如，氧化硅、SiCOH及SiOC。可将诸如聚合物的有机材料用于第一ILD层65。在形成了第一ILD层65之后，执行平坦化操作(诸如，CMP)，以使得经图案化的种晶层45的顶部被暴露，如图21中所示。在一些实施例中，经图案化的种晶层45充当CMP终止层。在一些实施例中，在第一ILD层65形成之前，形成接触蚀刻终止层，诸如，氮化硅层或氧氮化硅层。
接着，移除经图案化的种晶层45，借此形成栅极空间47，如图22中所示。可使用电浆干式蚀刻及/或湿式蚀刻来移除经图案化的种晶层45。
在移除了经图案化的种晶层45之后，在栅极空间47中的每一者中形成栅极介电层70及栅电极75，如图23中所示。在一些实施例中，栅极介电层70包括一或多层介电材料，诸如，氧化硅、氮化硅或高k介电材料、其他合适介电材料及/或其组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料，及/或其组合。在一些实施例中，栅极介电层70包括通过使用化学氧化形成于通道层35与介电材料之间的界面层。可通过CVD、ALD或任何合适方法形成栅极介电层70。在一个实施例中，使用诸如ALD的高度保形沉积制程形成栅极介电层70，以便确保形成在每一通道层周围具有均匀厚度的栅极介电层。在一个实施例中，栅极介电层70的厚度在自约1nm至约10nm的范围中。
随后，在栅极介电层70上形成栅电极层75。栅电极层75包括一或多层导电材料，诸如，多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金属合金、其他合适材料及/或其组合。可通过CVD、ALD、电镀或其他合适方法形成栅电极层75。用于栅极介电层70及栅电极层75的金属亦被沉积在第一ILD层65的上表面之上。接着通过使用例如CMP来平坦化形成于ILD层65之上的用于栅电极层的材料，直至露出ILD层65的顶表面为止。在一些实施例中，在平坦化操作之后，金属栅电极层75凹陷且在凹陷栅电极层之上形成覆盖绝缘层(未示出)。该覆盖绝缘层包括一或多层基于氮化硅的材料，诸如，氮化硅。可通过沉积绝缘材料继之以平坦化操作来形成覆盖绝缘层。
在本揭示案的某些实施例中，将一或多个功函数调整层(未示出)插入栅极介电层70与栅电极层75之间。功函数调整层由导电材料制成，诸如，单层TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或这些材料中的两者或两者以上的多层。对于n通道FET而言，将TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中的一或多者用作功函数调整层，且对于p通道FET而言，将TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中的一或多者用作功函数调整层。可通过ALD、PVD、CVD、电子束蒸镀或其他合适制程来形成功函数调整层。另外，可针对可使用不同金属层的n通道FET及p通道FET单独地形成功函数调整层。
另外，类似于图13A，第二ILD层形成于第一ILD层之上，且穿过第二ILD层或第二ILD层与第一ILD层的导电接触件经形成而接触栅电极及源极/漏极磊晶层。
在其他实施例中，在已结晶的半导体层35的前部中的每一者与已结晶的半导体层35的相邻前部会合之前，结晶制程终止。在此情形下，未结晶的半导体层30的部分保持在相邻FET之间。
应理解，FET经受进一步CMOS制程，以形成各种特征，诸如，接触点/通孔、互连金属层、介电层、钝化层，等等。
图24至图36A绘示根据本揭示案的实施例的制造半导体FET装置的各个阶段。应理解，可在由图24至图36A所示的操作之前、在其期间以及在其之后提供额外操作，且可替代或消除以下所述的操作中的一些而获得该方法的额外实施例。操作/制程的次序可互换。
类似于图1，在设置于基板10之上的介电层20之上形成半导体层30，如图25中所示。接着，类似于图2，在半导体层30之上形成种晶层40’，如图25中所示。在一些实施例中，种晶层40’由金属氧化物制成，该金属氧化物具有在沉积时结晶的性质或具有在约350℃至约45’0℃的低温退火下结晶的性质。在某些实施例中，种晶层40’由氧化镁(MgO)制成。在一些实施例中，MgO种晶层40’为单晶的。在其他实施例中，MgO种晶层40’为多晶的或具有单晶的多个晶畴。可通过CVD、原子层沉积(ALD)、物理气相沉积(包括溅射)或任何其他合适的膜形成方法来形成种晶层40’。种晶层40’的厚度在一些实施例中在自约1nm至约100nm的范围中，且在其他实施例中在自约2nm至约20nm的范围中。在某些实施例中，种晶层40’的厚度在自约1nm至约10nm的范围中。
接着，如图26中所示，在种晶层40’之上形成虚设栅极层90。在一些实施例中，虚设栅极层90由多晶硅或非晶硅制成。亦可使用可相对于ILD层及侧壁间隔物选择性地移除的其他半导体材料或介电材料。虚设栅极层90的厚度在一些实施例中在自约50nm至约500nm的范围中，且在其他实施例中在自约100nm至200nm的范围中。可通过CVD、原子层沉积(ALD)、物理气相沉积(包括溅射)或任何其他合适的膜形成方法来形成虚设栅极层90。
接下来，如图27中所示，通过使用一或多个微影操作及蚀刻操作将虚设栅极层90及种晶层40’图案化成多个经图案化的虚设栅极层95及经图案化的种晶层45’。微影操作包括UV微影、DUV微影、EUV微影、电子束微影，且蚀刻操作包括电浆干式蚀刻。经图案化的虚设栅极层95及经图案化的种晶层45’对应于随后形成的FET的栅电极。在一些实施例中，经图案化的虚设栅极层95及经图案化的种晶层45’具有线形形状。经图案化的虚设栅极层95及经图案化的种晶层45’的宽度在一些实施例中在自约5nm至约500nm的范围中，且在其他实施例中在自约20nm至约200nm的范围中。
随后，如图28至图31中所示，执行结晶制程以使半导体层30结晶。结晶制程包括热退火。在一些实施例中，热退火包括使用纳秒激光的激光退火制程，该纳秒激光对种晶层透明。在其他实施例中，热退火包括在自约350℃至450℃的范围中的温度下的低温退火。
如图29及图30中所示，半导体层30开始自经图案化的种晶层45’的底部(对应于随后形成的FET的通道区域)结晶为晶体模板。通过继续热退火制程，半导体层30的已结晶部分35横向地扩展至源极/漏极区域中，如图30中所示。
如图31中所示，已结晶的半导体层35的前部中的每一者与已结晶的半导体层35的相邻前部会合，从而形成晶界37。
随后，如图32中所示，在经图案化的虚设栅极层95及经图案化的种晶层45’的相对侧面上形成侧壁间隔物50。通过使用CVD或其他合适方法保形地形成用于侧壁间隔物50的绝缘材料的毯覆层。以保形方式来沉积毯覆层，以使得该毯覆层经形成而在经图案化的虚设栅极层95及经图案化的种晶层45’的垂直表面(诸如，侧壁)、水平表面及顶部上具有大体上相等的厚度。在一些实施例中，将毯覆层沉积至自约2nm至约30nm的范围中的厚度。在一个实施例中，毯覆层的绝缘材料不同于经图案化的虚设栅极层95及经图案化的种晶层45’的材料，且由基于氮化硅的材料制成，诸如，氮化硅、SiON、SiOCN或SICN及其组合。在一些实施例中，毯覆层(侧壁间隔物50)由氮化硅制成。如图8中所示，通过各向异性蚀刻，在经图案化的虚设栅极层95及经图案化的种晶层45’的相对侧面上形成侧壁间隔物50。在栅极替代技术中，经图案化的虚设栅极层95及经图案化的种晶层45’充当虚设栅电极。
接着，如图33中所示，形成源极区域及漏极区域。在一些实施例中，源极/漏极区域60包括一或多个磊晶半导体层。源极/漏极磊晶层60包括一或多层用于n通道FET的Si、SiP、SiC及SICP或用于p通道FET的Si、SiGe、Ge。对于P通道FET而言，亦可在源极/漏极区域中含有硼(B)。通过使用CVD、ALD或MBE的磊晶生成方法来形成源极/漏极磊晶层50。在一些实施例中，通过蚀刻使已结晶的半导体层35的源极/漏极区域凹陷，且接着在已结晶的半导体层35的凹陷源极/漏极区域之上形成源极/漏极磊晶层60。在其他实施例中，执行一或多个离子布植制程，以将杂质引入已结晶的半导体层35的源极/漏极区域中。在一些实施例中，源极/漏极磊晶层60完全地填充相邻虚设栅电极(经图案化的虚设栅极层95及经图案化的种晶层45’)之间的空间，且在其他实施例中，源极/漏极磊晶层60仅部分地填充相邻虚设栅电极之间的空间。
接着，在源极/漏极磊晶层60以及经图案化的虚设栅极层95及经图案化的种晶层45’之上形成第一层间介电质(ILD)层65。用于第一ILD层65的材料包括化合物，这些化合物包括Si、O、C及/或H，诸如，氧化硅、SiCOH及SiOC。可将诸如聚合物的有机材料用于第一ILD层65。在形成了第一ILD层65之后，执行平坦化操作(诸如，CMP)，以使得经图案化的虚设栅极层95及经图案化的种晶层45’的顶部被暴露，如图34中所示。在一些实施例中，经图案化的虚设栅极层95充当CMP终止层。在一些实施例中，在第一ILD层65形成的前，形成接触蚀刻终止层，诸如，氮化硅层或氧氮化硅层。
接着，移除经图案化的虚设栅极层95及经图案化的种晶层45’，借此形成栅极空间47，如图35中所示。可使用电浆干式蚀刻及/或湿式蚀刻来移除经图案化的虚设栅极层95及经图案化的种晶层45’。当经图案化的虚设栅极层95为多晶硅或非晶硅时，可使用诸如四甲基氢氧化铵(tetramethylammonium hydroxide；TMAH)溶液的湿蚀刻剂来选择性地移除虚设栅极层。其后使用电浆干式蚀刻及/或湿式蚀刻来移除经图案化的种晶层45’。
在移除了经图案化的虚设栅极层95及经图案化的种晶层45’之后，在栅极空间47中的每一者中形成栅极介电层70及栅电极75，如图36A中所示。在一些实施例中，栅极介电层70包括一或多层介电材料，诸如，氧化硅、氮化硅或高k介电材料、其他合适介电材料及/或其组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料，及/或其组合。在一些实施例中，栅极介电层70包括通过使用化学氧化形成于通道层35与介电材料之间的界面层。可通过CVD、ALD或任何合适方法形成栅极介电层70。在一个实施例中，使用诸如ALD的高度保形沉积制程形成栅极介电层70，以便确保形成在每一通道层周围具有均匀厚度的栅极介电层。在一个实施例中，栅极介电层70的厚度在自约1nm至约10nm的范围中。
随后，在栅极介电层70上形成栅电极层75。栅电极层70包括一或多层导电材料，诸如，多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAIN、TaCN、TaC、TaSiN、金属合金、其他合适材料及/或其组合。可通过CVD、ALD、电镀或其他合适方法形成栅电极层75。用于栅极介电层70及栅电极层75的金属亦被沉积在第一ILD层65的上表面之上。接着通过使用例如CMP来平坦化形成于ILD层65之上的用于栅电极层的材料，直至露出ILD层65的顶表面为止。在一些实施例中，在平坦化操作之后，金属栅电极层75凹陷且在凹陷栅电极层之上形成覆盖绝缘层(未示出)。该覆盖绝缘层包括一或多层基于氮化硅的材料，诸如，氮化硅。可通过沉积绝缘材料继之以平坦化操作来形成覆盖绝缘层。
在本揭示案的某些实施例中，将一或多个功函数调整层(未示出)插入栅极介电层70与栅电极层75之间。功函数调整层由导电材料制成，诸如，单层TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或这些材料中的两者或两者以上的多层。对于n通道FET而言，将TaN、TaAIC、TiN、TiC、Co、TiAI、HfTi、TiSi及TaSi中的一或多者用作功函数调整层；且对于p通道FET而言，将TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中的一或多者用作功函数调整层。可通过ALD、PVD、CVD、电子束蒸镀或其他合适制程来形成功函数调整层。另外，可针对可使用不同金属层的n通道FET及p通道FET单独地形成功函数调整层。
另外，类似于图13A，第二ILD层形成于第一ILD层之上，且穿过第二ILD层或第二ILD层与第一ILD层的导电接触件经形成而接触栅电极及源极/漏极磊晶层。如图13A中所示，在一些实施例中，制造的FET为薄膜晶体管(TFT)。
在其他实施例中，在已结晶的半导体层35的前部中的每一者与已结晶的半导体层35的相邻前部会合之前，结晶制程终止。在此情形下，未结晶的半导体层30的部分保持在相邻FET之间，如图36B中所示。
应理解，FET经受进一步CMOS制程，以形成各种特征，诸如，接触点/通孔、互连金属层、介电层、钝化层，等等。
图37绘示根据本揭示案的实施例的半导体装置的横截面图。如图37中所示，在基板之上形成下层元件100。下层元件100包括一或多个鳍式场效应晶体管(fin fieldeffect transistor；FinFET)、环绕式栅极FET(gate-all-around FET；GAA FET)、平面FET、垂直FET或任何其他电子装置。图37亦绘示设置于下层元件100之上的上层元件200。在一些实施例中，将一或多个ILD层、金属布线层及/或通孔接触件设置在下层元件100与上层元件200之间。在一些实施例中，上层元件200包括通过本揭示案的前述实施例制造的一或多个FET。
本文所述的各种实施例或实例提供了胜于现有技术的各种优势。举例而言，在本揭示案中，使用形成于非晶体半导体层(顶部种晶层)上的经图案化的种晶层来执行非晶体半导体层的结晶制程。因为非晶体半导体层的结晶是自经图案化的种晶层的底部开始，且将经图案化的种晶层用作虚设栅极，所以有可能将具有较高结晶品质的最初结晶部分(更靠近种晶层)用作FET的通道区域。换言之，可通过自对准方式将最佳结晶部分用作通道区域。另外，通过将种晶层作为虚设栅极用于栅极替代制程，有可能抑制制造半导体装置的操作步骤的增加。本揭示案的操作与半导体制造的后端工序制程相容。
应将理解，未必已在本文中论述了所有优势，对于所有实施例或实例而言无特定优势为必需，且其他实施例或实例可提供不同优势。
根据本揭示案的一态样，在一种制造半导体装置的方法中，在设置在基板之上的介电层上形成半导体层。在半导体层上形成种晶层。将种晶层图案化成经图案化的种晶层。使用经图案化的种晶层作为结晶的种晶来对半导体层执行结晶操作，借此形成已结晶的半导体层。在前述及以下实施例中的一或多者中，种晶层为MgO。在前述及以下实施例中的一或多者中，半导体层为非晶或多晶晶体。在前述及以下实施例中的一或多者中，半导体层为Si、SiGe及Ge中的一者。在前述及以下实施例中的一或多者中，种晶层的厚度在自1nm至10nm的范围中。在前述及以下实施例中的一或多者中，半导体层的厚度在自10nm至50nm的范围中。在前述及以下实施例中的一或多者中，结晶操作包括在自350℃至450℃的温度下的热退火，或激光退火。在前述及以下实施例中的一或多者中，在经图案化的种晶层的相对侧面上形成多个侧壁间隔物。形成源极/漏极结构。在这些侧壁间隔物、经图案化的种晶层及源极/漏极结构之上形成层间介电质(ILD)层。在形成ILD层之后，移除经图案化的种晶层，借此形成栅极空间。在栅极空间中形成栅极介电层及栅电极层。
根据本揭示案的另一态样，在一种制造半导体装置的方法中，在设置在基板之上的介电层上形成半导体层。在该半导体层上形成种晶层。将种晶层图案化成经图案化的种晶层。使用这些经图案化的种晶层作为结晶的种晶来对半导体层执行结晶操作，借此形成多个已结晶的半导体层。在前述及以下实施例中的一或多者中，种晶层为MgO。在前述及以下实施例中的一或多者中，半导体层为Si、SiGe及Ge中的一者的非晶或多晶晶体。在前述及以下实施例中的一或多者中，结晶操作包括在自350℃至450℃的温度下的热退火，或激光退火。在前述及以下实施例中的一或多者中，在经图案化的种晶层的相对侧面上形成多个侧壁间隔物。形成源极/漏极结构。在这些侧壁间隔物、经图案化的种晶层及源极/漏极结构之上形成层间介电质(ILD)层。在形成该ILD层之后，移除经图案化的种晶层，借此形成多个栅极空间。在这些栅极空间中的每一者中形成栅极介电层及栅电极层。在前述及以下实施例中的一或多者中，执行结晶操作，以使得在种晶层中的一者下方的已结晶半导体层的前部与在邻近种晶层中的该者的种晶层中的另一者下方的已结晶半导体层的前部会合，借此形成晶界。在前述及以下实施例中的一或多者中，在种晶层中的一者下方的已结晶半导体层的前部与在邻近种晶层中的该者的种晶层中的另一者下方的已结晶半导体层的前部会合之前，终止结晶操作。
根据本揭示案的另一态样，在一种制造半导体装置的方法中，在设置在基板之上的介电层上形成半导体层。在该半导体层上形成种晶层。在种晶层上形成虚设栅极层。将虚设栅极层及种晶层形成为经图案化的虚设栅极层及经图案化的种晶层。使用经图案化的种晶层作为结晶的种晶来对半导体层执行结晶操作，借此形成已结晶的半导体层。在前述及以下实施例中的一或多者中，虚设栅极层为Si、SiGe及Ge中的一者的非晶或多晶晶体。在前述及以下实施例中的一或多者中，虚设栅极层的厚度在自50nm至200nm的范围中。在前述及以下实施例中的一或多者中，种晶层为MgO。在前述及以下实施例中的一或多者中，在经图案化的虚设栅极层及经图案化的种晶层的相对侧面上形成多个侧壁间隔物。形成源极/漏极结构。在这些侧壁间隔物、经图案化的虚设栅极层及源极/漏极结构之上形成层间介电质(ILD)层。在形成该ILD层之后，移除经图案化的虚设栅极层及经图案化的种晶层，借此形成栅极空间。在栅极空间中形成栅极介电层及栅电极层。
根据本揭示案的一个态样，一种半导体装置包括通道，通道形成为设置在介电层上的半导体层的部分；设置在通道之上的栅极介电层；设置在栅极介电层之上的栅电极层；设置在栅电极层的相对侧面上的多个侧壁间隔物；以及源极及漏极。半导体层包括作为通道的晶体部分及非晶体部分。在前述及以下实施例中的一或多者中，半导体装置进一步包括被介电层覆盖的一或多个晶体管。在前述及以下实施例中的一或多者中，一或多个晶体管包括鳍式场效应晶体管。在前述及以下实施例中的一或多者中，半导体层由Si、SiGe及Ge中的一者制成。在前述及以下实施例中的一或多者中，半导体层的厚度在自10nm至50nm的范围中。
根据本揭示案的另一态样，一种半导体装置包括设置于基板上的电子装置、设置在该电子装置之上的一或多个介电层、设置在一或多个介电层的最上层上的薄膜晶体管。这些薄膜晶体管中的每一者包括通道，通道形成为设置在最上层上的半导体层的部分；设置在通道之上的栅极介电层；设置在栅极介电层之上的栅电极层；设置在栅电极层的相对侧面上的多个侧壁间隔物；以及源极及漏极。半导体层为单晶，且晶界存在于薄膜晶体管中的一者的半导体层与邻近薄膜晶体管中的该者的薄膜晶体管中的另一者的半导体层之间。在前述及以下实施例中的一或多者中，电子装置为晶体管。在前述及以下实施例中的一或多者中，晶体管为鳍式场效应晶体管及环绕式栅极晶体管中的一者。在前述及以下实施例中的一或多者中，半导体层由Si、SiGe及Ge中的一者制成。在前述及以下实施例中的一或多者中，最上层由氧化硅制成。在前述及以下实施例中的一或多者中，半导体层的厚度在自10nm至50nm的范围中。在前述及以下实施例中的一或多者中，源极及漏极包括磊晶半导体层。在前述及以下实施例中的一或多者中，磊晶半导体层与薄膜晶体管中的一者的侧壁间隔物中的一者以及薄膜晶体管中的另一者的侧壁间隔物中的一者接触。
根据本揭示案的另一态样，一种半导体装置包括设置于基板上的电子装置、设置在电子装置之上的一或多个介电层，及设置在一或多个介电层的最上层上的薄膜晶体管。这些薄膜晶体管中的每一者包括通道，通道形成为设置在最上层上的半导体层的部分；设置在通道之上的栅极介电层；设置在栅极介电层之上的栅电极层；设置在栅电极层的相对侧面上的多个侧壁间隔物；以及源极及漏极。通道为单晶，且由与半导体层相同的材料制成的非晶半导体层存在于薄膜晶体管中的一者的半导体层与邻近薄膜晶体管的该者的薄膜晶体管的另一者的半导体层之间。在前述及以下实施例中的一或多者中，电子装置为晶体管。在前述及以下实施例中的一或多者中，晶体管为鳍式场效应晶体管及环绕式栅极晶体管中的一者。在前述及以下实施例中的一或多者中，半导体层由Si、SiGe及Ge中的一者制成。在前述及以下实施例中的一或多者中，半导体层的厚度在自10nm至50nm的范围中。在前述及以下实施例中的一或多者中，源极及漏极包括磊晶半导体层。在前述及以下实施例中的一或多者中，磊晶半导体层与薄膜晶体管中的一者的侧壁间隔物中的一者以及薄膜晶体管中的另一者的侧壁间隔物中的一者接触。
前文概述了若干实施例或实例的特征，使得熟悉此项技艺者可较佳理解本揭示案的态样。熟悉此项技艺者应了解，他们可容易地使用本揭示案作为设计或修改用于实现相同目的及/或达成本文中所介绍的实施例或实例的相同优势的其他制程及结构的基础。熟悉此项技艺者亦应认识到，此等等效构造不脱离本揭示案的精神及范畴，且他们可在不脱离本揭示案的精神及范畴的情况下于本文中进行各种改变、代替及修改。

Claims (20)

1.一种制造半导体装置的方法，其特征在于，该方法包括：
在设置于一基板之上的一介电层上形成一半导体层；
在该半导体层上形成一种晶层；
将该种晶层图案化成一经图案化的种晶层；
使用该经图案化的种晶层作为结晶的一种晶来对该半导体层执行一结晶操作，借此形成一已结晶的半导体层；以及
在该经图案化的种晶层的相对侧面上形成多个侧壁间隔物。
2.根据权利要求1所述的方法，其特征在于，该种晶层为MgO。
3.根据权利要求1所述的方法，其特征在于，该半导体层为非晶或多晶晶体。
4.根据权利要求3所述的方法，其特征在于，其中该半导体层为Si、SiGe及Ge中的一者。
5.根据权利要求1所述的方法，其特征在于，其中该种晶层的一厚度在自1nm至10nm的一范围中。
6.根据权利要求1所述的方法，其特征在于，其中该半导体层的一厚度在自10nm至50nm的一范围中。
7.根据权利要求1所述的方法，其特征在于，其中该结晶操作包括在自350℃至450℃的一温度下的一热退火，或一激光退火。
8.根据权利要求1所述的方法，其特征在于，进一步包括：
形成一源极/漏极结构；
在所述多个侧壁间隔物、该经图案化的种晶层及该源极/漏极结构之上形成一层间介电质层；
在形成该层间介电质层之后，移除该经图案化的种晶层，借此形成一栅极空间；以及
在该栅极空间中形成一栅极介电层及一栅电极层。
9.一种制造半导体装置的方法，其特征在于，该方法包括：
在设置于一基板之上的一介电层上形成一非晶或一多晶的半导体层；
在该半导体层上形成一种晶层；
将该种晶层图案化成多个经图案化的种晶层；
使用所述多个经图案化的种晶层作为结晶的一种晶来对该半导体层执行一结晶操作，借此在该介电层之上形成多个单晶半导体层；以及
在所述多个经图案化的种晶层的相对侧面上形成多个侧壁间隔物。
10.根据权利要求9所述的方法，其特征在于，其中该种晶层为MgO。
11.根据权利要求9所述的方法，其特征在于，其中该半导体层为Si、SiGe及Ge中的一者的非晶或多晶晶体。
12.根据权利要求9所述的方法，其特征在于，该结晶操作包括在自350℃至450℃的一温度下的一热退火，或一激光退火。
13.根据权利要求9所述的方法，其特征在于，进一步包括：
形成一源极/漏极结构；
在所述多个侧壁间隔物、所述多个经图案化的种晶层及该源极/漏极结构之上形成一层间介电质层；
在形成该层间介电质层之后，移除所述多个经图案化的种晶层，借此形成多个栅极空间；以及
在所述多个栅极空间中的每一者中形成一栅极介电层及一栅电极层。
14.根据权利要求9所述的方法，其特征在于，执行该结晶操作，以使得在所述多个种晶层中的一者下方的一已结晶半导体层的一前部与在邻近所述多个种晶层中的该者的所述多个种晶层中的另一者下方的一已结晶半导体层的一前部会合，借此形成一晶界。
15.根据权利要求9所述的方法，其特征在于，于在所述多个种晶层中的一者下方的一已结晶半导体层的一前部与在邻近所述多个种晶层中的该者的所述多个种晶层中的另一者下方的一已结晶半导体层的一前部会合之前，终止该结晶操作。
16.一种半导体装置，其特征在于，包括：
一电子装置，该电子装置被设置在一基板上；
一或多个介电层，该一或多个介电层被设置在该电子装置之上；以及
多个薄膜晶体管，所述多个薄膜晶体管被设置在该一或多个介电层中的一最上层上，其中：
所述多个薄膜晶体管中的每一者包括：
一通道，该通道形成为设置在该最上层上的一半导体层的一部分；
一栅极介电层，该栅极介电层被设置在该通道之上；
一栅电极层，该栅电极层被设置在该栅极介电层之上；
多个侧壁间隔物，所述多个侧壁间隔物被设置在该栅电极层的相对侧面上；以及
一源极及一漏极，
该通道为单晶，
一晶界存在于所述多个薄膜晶体管中的一者的该半导体层与邻近所述多个薄膜晶体管中的该者的所述多个薄膜晶体管中的另一者的该半导体层之间。
17.根据权利要求16所述的半导体装置，其特征在于，其中该电子装置为一晶体管。
18.根据权利要求17所述的半导体装置，其特征在于，其中该晶体管为一鳍式场效应晶体管及一环绕式栅极晶体管中的一者。
19.根据权利要求16所述的半导体装置，其特征在于，其中该半导体层由Si、SiGe及Ge中的一者制成。
20.根据权利要求16所述的半导体装置，其特征在于，其中该最上层由氧化硅制成。
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