CN113380800A - 集成半导体器件、晶体管和制造突起场效应晶体管的方法 - Google Patents

集成半导体器件、晶体管和制造突起场效应晶体管的方法 Download PDF

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CN113380800A
CN113380800A CN202110591884.2A CN202110591884A CN113380800A CN 113380800 A CN113380800 A CN 113380800A CN 202110591884 A CN202110591884 A CN 202110591884A CN 113380800 A CN113380800 A CN 113380800A
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layer
dielectric
protrusions
gate
transistor
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马可·范·达尔
荷尔本·朵尔伯斯
乔治奥斯·韦理安尼堤斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/222,028 external-priority patent/US11569352B2/en
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Publication of CN113380800A publication Critical patent/CN113380800A/zh
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Abstract

提供了晶体管、集成半导体器件及制造方法。该晶体管包括：具有多个介电突起的介电层；共形地覆盖介电层的突起以在两个相邻的介电突起之间形成多个沟槽的沟道层；设置在沟道层上的栅极层。栅极层106具有配接到沟槽中的多个栅极突起。该晶体管还包含栅极层旁边的有源区。有源区电连接至沟道层。

Description

集成半导体器件、晶体管和制造突起场效应晶体管的方法
技术领域
本申请的实施例涉及集成半导体器件、晶体管和制造突起场效应晶体管的方法。
背景技术
在半导体工业中，增加集成电路的面密度是一直期望的。为此，个体晶体管变得越来越小。然而，可将个体晶体管制造得更小的速度一直在减慢。将外围晶体管从制造的前段制程(FEOL)移至制造的后段制程(BEOL)可能较为有利，因为可以在BEOL中添加功能，而在FEOL中可以制成可用的宝贵芯片面积。由氧化物半导体制成的薄膜晶体管(TFT)是BEOL集成的一个有吸引力的选择，因为TFT可以在低温下进行处理，并且因此不会损坏先前制造的器件。然而，薄膜晶体管通常是平面的。因此，它们具有相对较大的占位面积，这阻碍它们用于布线，并且因此不利于芯片面积尺寸缩放。
发明内容
本申请的一些实施例提供了一种晶体管，包括：介电层，具有多个介电突起；沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。
本申请的另一些实施例提供了一种集成半导体器件，包括：突起场效应晶体管，位于所述集成半导体器件的后段制程(BEOL)部分中，所述突起场效应晶体管包括：介电层，具有多个介电突起；沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。
本申请的又一些实施例提供了一种制造突起场效应晶体管的方法，包括：提供衬底，所述衬底包括具有多个介电突起的介电层；共形地形成覆盖所述多个介电突起的沟道层以在两个相邻的介电突起之间形成多个沟槽；形成设置在所述沟道层上的栅极层，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及在所述栅极层的任意一侧上形成有源区，其中，所述有源区电连接至所述沟道层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A是根据本发明实施例的在形成突起场效应晶体管阵列之前的第一示例性结构的垂直截面图。
图1B是根据本发明实施例的在形成突起场效应晶体管阵列之后的第一示例性结构的垂直截面图。
图1C是根据本发明实施例的在形成高层级金属互连结构之后的第一示例性结构的垂直截面图。
图2A是示出根据本发明实施例的在制造晶体管的方法中在衬底中形成突起的步骤的顶视图。
图2B是穿过图2A的线AA’的垂直截面图。
图2C是穿过图2A的线BB’的垂直截面图。
图3A是示出根据本发明实施例的在制造晶体管的方法中在衬底上方沉积连续沟道层的步骤的顶视图。
图3B是穿过图3A的线AA’的垂直截面图。
图3C是穿过图3A的线BB’的垂直截面图。
图4A是示出根据本发明实施例的在制造晶体管的方法中对沟道层进行图案化的步骤的顶视图。
图4B是穿过图4A的线AA’的垂直截面图。
图4C是穿过图4A的线BB’的垂直截面图。
图5A是示出根据本发明实施例的在制造晶体管的方法中在沟道层上方沉积高k介电层和金属栅极层的步骤的顶视图。
图5B是穿过图5A的线AA’的垂直截面图。
图5C是穿过图5A的线BB’的垂直截面图。
图6A是示出根据本发明实施例的在制造晶体管的方法中对沟道层进行离子注入以形成有源区的步骤的顶视图。
图6B是穿过图6A的线AA’的垂直截面图。
图6C是穿过图6A的线BB’的垂直截面图。
图7A是示出根据本发明实施例的在制造晶体管的方法中在图6A至图6C所示的中间结构上方沉积互连层级介电层并形成有源区接触件的步骤的顶视图。
图7B是穿过图7A的线AA’的垂直截面图。
图7C是穿过图7A的线BB’的垂直截面图。
图8A是示出根据本发明实施例的在与图7A至图7C所示的实施例中形成的突起的方向垂直的方向上形成突起的晶体管的可选实施例的顶视图。
图8B是穿过图8A的线AA’的垂直截面图。
图8C是穿过图8A的线BB’的垂直截面图。
图9是示出根据本发明实施例的具有二维突起阵列的衬底的可选实施例的顶视图。
图10A是示出根据本发明实施例的具有以图9中所示的衬底制成的二维突起阵列的晶体管的可选实施例的顶视图。
图10B是穿过图10A的线AA’的垂直截面图。
图10C是穿过图10A的线BB’的垂直截面图。
图11A是示出根据本发明实施例的其中突起具有三角形截面轮廓的衬底的可选实施例的顶视图。
图11B是穿过图11A的线AA’的垂直截面图。
图11C是穿过图11A的线BB’的垂直截面图。
图12A是示出根据本发明实施例的其中突起具有圆化的三角形截面轮廓的衬底的可选实施例的顶视图。
图12B是穿过图12A的线AA’的垂直截面图。
图12C是穿过图12A的线BB’的垂直截面图。
图13是示出本发明的方法的一般处理步骤的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明涉及半导体器件，并且具体地涉及突起场效应晶体管及其形成方法。实施例还包括具有突起场效应晶体管的集成电路，具体为位于BEOL中的突起薄膜场效应晶体管。在各个实施例中，突起场效应晶体管可以具有一个或多个突起，这些突起具有3-30nm的突起宽度PW和10-250nm的突起高度PH。
薄膜晶体管(TFT)对于BEOL集成有若干优势。例如，TFT可以在低温下进行处理，并且可以向BEOL添加功能，同时可以在FEOL中制成可用的宝贵芯片面积。通过将外围器件(诸如功率栅极或输入/输出(I/O)器件)从FEOL移到BEOL的更高金属层级，在BEOL中使用TFT可以用作3nm节点制造(N3)或以外的缩放路径。对于给定的器件，将TFT从FEOL移到BEOL可以产生约5-10％的面积缩小。
可从FEOL移到BEOL的TFT包括但不限于功率栅极、输入/输出元件和存储器选择器。在目前技术中，功率栅极是位于FEOL中的逻辑晶体管。功率栅极可以用于在待机状态下截止逻辑块，从而减小静态功耗。I/O器件是计算元件(例如，CPU)与外界(例如，硬盘驱动)之间的接口，并且也在FEOL中进行处理。用于存储元件的选择器，例如磁阻式随机存取存储器(MRAM)或电阻式随机存取存储器(RRAM)目前位于FEOL中，并且可以被移到BEOL。典型地，每个存储元件都有一个选择器TFT。
与其中栅电极位于晶体管的顶部的顶栅晶体管相比，背栅或底栅晶体管在TFT的底部具有栅电极。一般来说，可以按如下步骤制造底栅TFT。首先，可以在衬底上沉积栅极金属层并对栅极金属层进行图案化以形成栅电极。衬底可以由任何合适的材料制成，诸如硅或绝缘体上硅。栅极金属可以由铜、铝、锆、钛、钨、钽、钌、钯、铂、钴、镍或其合金制成。其他合适的材料属于本发明的可设想范围内。可以通过任何合适的技术来沉积栅极金属，诸如化学气相沉积(CVD)、物理气相沉积(PVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)。
接下来，可以在栅电极上方沉积高k介电层。高k介电材料是介电常数高于二氧化硅的材料，并且包括但不限于二氧化铪(HfO2)、氧化铪硅(HfSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)。其他合适的材料属于本发明的可设想范围内。
接下来，可以在高k介电层上方沉积半导体材料层。可以对半导体材料层进行图案化并且离子注入以形成有源区(源极/漏极区)和位于有源区之间的沟道区。半导体材料可以由非晶硅或半导体氧化物制成，诸如InGaZnO、InWO、InZnO、InSnO、GaOx、InOx等。其他合适的材料属于本发明的可设想范围内。半导体材料可以通过任何合适的方法形成，诸如CVD、PECVD或原子层沉积ALD。
图1A是根据本发明实施例的，在形成突起场效应晶体管阵列之前的第一示例性结构的垂直截面图。参考图1A，其中示出在形成突起场效应晶体管的阵列之前的根据本发明实施例的第一示例性结构。第一示例性结构包括衬底8，该衬底包含半导体材料层10。衬底8可以包括块状半导体衬底，诸如硅衬底，其中半导体材料层从衬底8的顶面连续地延伸到衬底8的底面，或者包括半导体材料层10的绝缘体上半导体层，半导体材料层10作为掩埋绝缘体层(诸如氧化硅层)上面的顶部半导体层。该示例性结构可以包括各个器件区，其可以包括存储器阵列区100，该存储器阵列区100中可以随后形成至少一个突起场效应晶体管阵列。该示例性结构还可以包括外围区200，在该外围区200中可以随后形成突起场效应晶体管的每个阵列与包括场效应晶体管的外围电路之间的电连接。可以采用存储器阵列区100和外围区200的区域来形成外围电路的各个元件。
诸如场效应晶体管的半导体器件可以形成在半导体材料层10上和/或之中。例如，可以通过形成浅沟槽并随后以诸如氧化硅的介电材料填充该浅沟槽而在半导体材料层10的上部中形成浅沟槽隔离结构12。其他合适的介电材料属于本发明的可设想范围内。可以通过执行掩模离子注入工艺，在半导体材料层10的上部的各个区中形成各个掺杂阱(未明确示出)。
可以通过沉积和图案化栅极介电层、栅电极层和栅极覆盖介电层，在衬底8的顶面上方形成栅极结构20。每个栅极结构20可以包括栅极电介质22、栅电极24和栅极覆盖电介质28的垂直堆叠件，其在本文中将其被称为栅极堆叠件(22、24、28)。可以执行离子注入工艺以形成延伸注入区，其可以包括源极延伸区和漏极延伸区。可以在栅极堆叠件(22、24、28)周围形成介电栅极间隔件26。栅极堆叠件(22、24、28)和介电栅极间隔件26的每个组件构成栅极结构20。可以执行附加的离子注入工艺，其使用栅极结构20作为自对准注入掩模以形成深有源区。此类深有源区可以包括深源极区和深漏极区。深有源区的上部可以与延伸注入区的一部分重叠。延伸注入区和深有源区的每个组合可以构成有源区14，该有源区可以是源极区或漏极区，具体取决于电偏压。可以在相邻成对的有源区14之间的每个栅极堆叠件(22、24、28)下方形成半导体沟道15。金属-半导体合金区域18可以形成在每个有源区14的顶面上。可以在半导体材料层10上和/或中形成场效应晶体管。每个场效应晶体管可以包括栅极结构20、半导体沟道15、一对有源区14(其中一个用作源极区而另一个用作漏极区)以及可选的金属-半导体合金区18。可以在半导体材料层10上提供互补金属氧化物半导体(CMOS)电路330，其可以包括用于随后形成的突起场效应晶体管的阵列的外围电路。
如上所述和图1A所示，电路330中的晶体管可以是平面晶体管。然而，如下文更详细地论述，电路330中的所示平面晶体管也可以被替代为下文参考图2A至图12B描述的FinFET或突起场效应晶体管。即，在各个实施例中，这些晶体管的半导体沟道15可以具有从衬底8表面的平面向外延伸的三维“鳍”形状。除了沟道的顶面之外，可以将栅极结构20形成在鳍形沟道的侧壁上。在下面更详细描述的可选实施例中，衬底8(或互连层级结构的任何其他介电层)可以包括介电突起，而不是半导体沟道15。由此，在介电突起上方形成的半导体沟道15也将具有三维结构。
可以随后形成各个互连层级结构，其在形成突起场效应晶体管的阵列之前形成，并且在本文中称为下部互连层级结构(L0、L1、L2)。如果随后要在两个层级互连层级金属线上方形成突起场效应晶体管的二维阵列，则下部互连层级结构(L0、L1、L2)可以包括接触层级结构L0、第一互连层级结构L1和第二互连层级结构L2。接触层级结构L0可以包括平坦化介电层31A，该平坦化介电层31A包括诸如氧化硅的平坦化介电材料，以及接触有源区14或栅电极24中相应一个并形成在平坦化介电层31A内的多个接触通孔结构41V。第一互连层级结构L1包括第一互连层级介电层31B和形成在第一互连层级介电层31B内的第一金属线41L。第一互连层级介电层31B也称为第一线层级介电层。第一金属线41L可以接触接触通孔结构41V中的相应一个。第二互连层级结构L2包括第二互连层级介电层32，该第二互连层级介电层32可以包括第一通孔层级介电材料层和第二线层级介电材料层或线和通孔层级介电材料层的堆叠件。第二互连层级介电层32可以在其内形成有第二互连层级金属互连结构(42V、42L)，其包括第一金属通孔结构42V和第二金属线42L。第二金属线42L的顶面可以与第二互连层级介电层32的顶面共面。
图1B是根据本发明实施例的，在形成突起场效应晶体管阵列之后的第一示例性结构的垂直截面图。参考图1B，可以将突起场效应晶体管的阵列95形成在第二互连层级结构L2上方的存储器阵列区100中。下文详细描述突起场效应晶体管的阵列95的结构和处理步骤的细节。可以在形成突起场效应晶体管的阵列95期间形成第三互连层级介电层33。在突起场效应晶体管的阵列95的层级处形成的所有结构的集合在本文中称为第三互连层级结构L3。
图1C是根据本发明实施例的，在形成高层级金属互连结构期间的第一示例性结构的垂直截面图。参考图1C，可以在第三互连层级介电层33中形成第三互连层级金属互连结构(43V、43L)。第三互连层级金属互连结构(43V、43L)可以包括第二金属通孔结构43V和第三金属线43L。可以随后形成附加互连层级结构，在本文中将其称为上部互连层级结构(L4、L5、L6、L7)。例如，上部互连层级结构(L4、L5、L6、L7)可以包括第四互连层级结构L4、第五互连层级结构L5、第六互连层级结构L6和第七互连层级结构L7。第四互连层级结构L4可以包括第四互连层级介电层34，该第四互连层级介电层在其中形成有第四互连层级金属互连结构(44V、44L)，该第四互连层级金属互连结构可以包括第三金属通孔结构44V和第四金属线44L。第五互连层级结构L5可以包括第五互连层级介电层35，该第五互连层级介电层在其中形成有第五互连层级金属互连结构(45V、45L)，该第五互连层级金属互连结构可以包括第四金属通孔结构45V和第五金属线45L。第六互连层级结构L6可以包括第六互连层级介电层36，该第六互连层级介电层在其中形成有第六互连层级金属互连结构(46V、46L)，该第六互连层级金属互连结构可以包括第五金属通孔结构46V和第六金属线46L。第七互连层级结构L7可以包括第七互连层级介电层37，该第七互连层级介电材料层在其中形成有第六金属通孔结构47V(其是第七互连层级金属互连结构)和金属接合焊盘47B。金属接合焊盘47B可以配置成用于焊料接合(其可以采用C4球接合或引线接合)，或者可以配置成用于金属至金属接合(诸如铜至铜接合)。
每个互连层级介电层可以称为互连层级介电层(ILD)层30。每个互连层级金属互连结构可以称为金属互连结构40。金属通孔结构和位于同一互连层级结构(L2-L7)内的上面的金属线的每个连续组合可以通过采用两个单镶嵌工艺顺序形成为两个不同的结构，或者可以采用双重镶嵌工艺同时形成为整体结构。每个金属互连结构40可以包括相应的金属衬垫(诸如厚度在2nm至20nm的范围内的TiN、TaN或WN层)和相应的金属填充材料(诸如W、Cu、Co、Mo、Ru、其他元素金属或其合金或组合)。用作金属衬垫和金属填充材料的其他合适的材料属于可设想的发明公开范围内。可以将多个蚀刻停止介电层和介电保护层插入在多个成对垂直相邻的ILD层30之间，或者可以合并到一个或多个ILD层30中。
尽管采用可将突起场效应晶体管的阵列95形成为第三互连层级结构L3的组件的实施例来描述本发明，但是本文明确地可设想其中可以将突起场效应晶体管的阵列95形成为任何其他互连层级结构(例如L1-L7)的组件的实施例。此外，尽管本发明描述形成八个互连层级结构的集合的实施例，但是本文明确地可设想其中采用不同数量的互连层级结构的实施例。此外，本文明确地可设想其中可以在存储器阵列区100中的多个互连层级结构内提供两个或更多个突起场效应晶体管的阵列95的实施例。尽管采用其中在单个互连层级结构中形成突起场效应晶体管的阵列95的实施例来描述本发明，但是本文明确地可设想其中可以在两个垂直相邻的互连层级结构上方形成突起场效应晶体管的阵列95的实施例。
图2A至图12B示出多个突起TFT以及制造多个突起TFT的方法。图2A是示出根据本发明实施例的制造晶体管的方法中的在衬底中形成突起的步骤的顶视图。图2B是穿过图2A的线AA’的垂直截面图。图2C是穿过图2A的线BB’的垂直截面图。参考图2A至图2C，介电层102可以设置有可以形成在其上的多个介电突起103。可以呈一维阵列形成多个突起。如本文所定义，一维阵列的突起是其中存在图2A所示的单行或单列突起的阵列。如图所示，沿线A-A’形成介电突起103的一维阵列。下面更详细地讨论且图9中示出的介电突起103的二维阵列包括在同一器件中多行和多列突起。该一维阵列可以沿着垂直于有源区之间的第一方向的第二方向形成。在各个实施例中，可以通过用光刻胶(未示出)掩蔽介电层102并蚀刻介电层102中的沟槽105来形成多个介电突起103，从而在沟槽105之间形成多个介电突起103。可选地，可以用光刻胶(未示出)掩蔽介电层102，并且在介电层102中的开口中生长多个介电突起103。在各个实施例中，介电层102可以由诸如SiO2的介电材料制成。在可选的实施例中，介电层102可以是由介电材料制成的衬底的顶部。在各个实施例中，多个介电突起103可具有在10-250nm范围内的高度PH和在3-30nm范围内的宽度PW。在各个实施例中，多个介电突起103可以具有在20-200nm范围内的突起高度PH，尽管可以使用更高或更低的突起高度。在各个实施例中，多个介电突起103中的每个都可以具有在5-25nm范围内的突起宽度PW，尽管可以使用更宽或更窄的突起宽度。
图3A是示出根据本发明实施例的在制造晶体管的方法中在衬底上方沉积连续沟道层的步骤的顶视图。图3B是穿过图3A的线AA’的垂直截面图。图3C是穿过图3A的线BB’的垂直截面图。参考图3A至图3C，可以将连续沟道层104L共形地沉积在介电层102上以覆盖多个介电突起103，从而在两个相邻的介电突起103之间形成多个沟槽。以这种方式，可以在多个介电突起103上方和沟槽105中形成具有基本均匀厚度的层。在实施例中，突起TFT可以形成为集成半导体器件中的互连结构的一部分。例如，突起TFT可以形成为第三互连层级结构L3的一部分，此情况中，第二互连层级介电层32可以代替介电层102。连续沟道层104L可以由任何合适的半导体材料制成，诸如非晶硅或半导体氧化物，诸如InGaZnO、InWO、InZnO、InSnO、GaOx、InOx等。其他合适的材料属于本发明的可设想范围内。在各个实施例中，连续沟道层104L的厚度可以在1-20nm的范围内，诸如5-15nm，但是可以使用更大或更小的厚度。连续沟道层104L可以通过任何合适的技术来沉积，诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)。
图4A是示出根据本发明实施例的在制造晶体管的方法中对沟道层进行图案化的步骤的顶视图。图4B是穿过图4A的线AA’的垂直截面图。图4C是穿过图4A的线BB’的垂直截面图。参考图4A至图4C，可以对连续沟道层104L进行图案化。为了对连续沟道层104L进行图案化，可以在连续沟道层104L上方沉积光刻胶(未示出)并对其进行图案化。然后，在对连续沟道层104L进行图案化时，可以将图案化光刻胶用作掩模。对连续沟道层104L进行图案化所得到是图案化的沟道层104。图案化可以通过湿蚀刻或干蚀刻来执行。蚀刻之后，可以通过灰化或用溶剂溶解去除任何残留的光刻胶。
图5A是示出根据本发明实施例的在制造晶体管的方法中在沟道层上方沉积高k介电层和金属栅极层的步骤的顶视图。图5B是穿过图5A的线AA’的垂直截面图。图5C是穿过图5A的线BB’的垂直截面图。参考图5A至图5C，可以将高k介电层108共形地沉积在介电层102和图案化的沟道层104上方。接下来，可以在高k介电层108上方沉积栅极层106。高k介电层108可以包括但不限于二氧化铪(HfO2)、氧化铪硅(HfSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)。其他合适的材料属于本发明的可设想范围内。栅极层106可以由任何适合的金属制成，诸如铜、铝、锆、钛、钨、钽、钌、钯、铂、钴、镍或其合金。其他合适的材料属于本发明的可设想范围内。栅极层106可以通过任何合适的技术来沉积，诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)。高k介电层108和栅极层106可以通过首先沉积光刻胶层(未示出)并对其进行图案化，从而使得高k介电层108和栅极层106具有如图5A和图5C所示的轨迹形状来形成。再者，如图5B所示，当可以用栅极层106的栅极材料填充介电层102上的突起之间的沟槽105时，可以形成栅极突起106P。在各个实施例中，高k介电层108可以具有在0.5-5nm范围内的厚度thk，诸如1-4nm，诸如2.5-3.5nm，但是可以使用更大或更小的厚度。
参考图6A至图6C，可以对图案化的沟道层104的在栅极层106之下暴露的部分进行离子注入111，以在沟道区104R的任意一侧上形成有源区(例如，源极/漏极区)113。可以注入有源区113，使得有源区113中原子的平均原子浓度在1.0×1016/cm3至1.0×1020/cm3的范围内，诸如从1.0×1017/cm3至5.0×1019/cm3，但是可以使用更大或更小的原子浓度。此外，由于在形成有源区113时可以将栅极层106用作掩模，所以可以说有源区113与沟道区104R是自对准的。
图7A是示出根据本发明实施例的在制造晶体管的方法中在图6A至图6C所示的中间结构上方沉积互连层级介电层并形成有源区接触件的步骤的顶视图。图7B是穿过图7A的线AA’的垂直截面图。图7C是穿过图7A的线BB’的垂直截面图。参考图7A至图7C，可以将互连层级介电层30沉积在图7A至图7C所示的中间结构上方。互连层级介电层30可以由任何合适的材料制成，包括但不限于SiO2。其他合适的材料属于本发明的可设想范围内。然后可以在互连层级介电层30中形成向下至有源区113表面的通孔(未示出)。接下来，可以用导电材料填充通孔以形成有源区通孔接触件112。导电材料可以是TiN、W、Al、Cu或任何其他合适的材料。在形成有源区通孔接触件112之后，可以执行平坦化步骤以对互连层级介电层30的表面和有源区通孔接触件112的顶面进行平坦化。平坦化步骤可以通过例如化学机械抛光(CMP)来执行。最终得到突起场效应晶体管300。
参考图7B所示，与FinFET类似，所得的突起场效应晶体管300具有三维图案化的沟道层104。不同于平面沟道，诸如FinFET技术或在实施例中的突起场效应晶体管300的三维构造提供优于平面FET的若干优势。例如，鳍结构可以对于给定的晶体管占位面积能够实现更高的驱动电流，从而产生更高的速度。三维结构还可以实现较低的泄漏，从而产生较低的功耗。三维结构还可以实现降低的掺杂剂波动，从而产生更好的迁移率和晶体管的缩放。因此，所得的突起场效应晶体管300可以称为三维场效应晶体管。如图7B所示，所得到的突起场效应晶体管300的有效沟道宽度Weff可以显著宽于沟道宽度W(其中，沟道长度是从有源区至有源区的距离，例如，源极到漏极的距离，而沟道宽度是垂直于沟道长度的距离)。虽然沟道宽度W可以是沟道材料108的横向距离，但是由于图案化的沟道层104遵循如箭头所示的介电层102和多个介电突起103的轮廓，因此图案化的沟道层104的有效沟道宽度Weff显著地更长。如上文论述，在各个实施例中，多个介电突起103可具有在10-250nm范围内的突起高度PH和在3-100nm范围内的突起长度PL。突起高度PH可以显著地影响有效沟道宽度Weff。
图8A至图8C示出突起场效应晶体管400的另一实施例。图8A是示出根据本发明实施例的，在与图7A至图7C所示的实施例中形成的突起方向垂直的方向上形成突起的晶体管的可选实施例的顶视图。图8B是穿过图8A的线AA’的垂直截面图。图8C是穿过图8A的线BB’的垂直截面图。该实施例类似于图7A至图7C所示的突起场效应晶体管。然而，在该可选的实施例中，多个介电突起103的一维阵列可以在有源区113之间的第一方向上。可以沿着沟道长度L，即有源区113之间的距离，形成多个介电突起103的一维阵列。如图8C所示，由于图案化的沟道层遵循箭头指示的从第一有源区113到第二有源区113的介电层102与多个介电突起103的轮廓，因此所得到的突起场效应晶体管400的有效沟道长度Leff显著长于图案化的沟道层104的长度L。有效沟道长度Leff可以随多个介电突起103的数量和突起103的尺寸而变化。如上文论述，在各个实施例中，多个介电突起103可具有在10-250nm范围内的突起高度PH和在3-100nm范围内的突起长度PL。突起高度PH可以显著地影响有效沟道长度Leff。
图9是示出根据本发明的第三实施例的在制造晶体管的方法中在衬底中形成突起的步骤的顶视图。在图8A至图8C所示的本发明的第三实施例中，可以在x和y方向上形成介电突起103的阵列。可以将沟道层104和介电层108共形地沉积在介电突起103的阵列上方。连续沟道层104L可以由任何合适的半导体材料制成，诸如非晶硅或半导体氧化物，诸如InGaZnO、InWO、InZnO、InSnO、GaOx、InOx等。其他合适的材料属于本发明的可设想范围内。在各个实施例中，连续沟道层104L的厚度可以在1-20nm的范围内，诸如5-15nm，但是可以使用更大或更小的厚度。连续沟道层104L可以通过任何合适的技术来沉积，诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)。高k介电层108可以包括但不限于二氧化铪(HfO2)、氧化铪硅(HfSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)。其他合适的材料属于本发明的可设想范围内。随后可以在高k介电层108上方沉积栅极层106。栅极层106可以由任何适合的金属制成，诸如铜、铝、锆、钛、钨、钽、钌、钯、铂、钴、镍或其合金。其他合适的材料属于本发明的可设想范围内。栅极层106可以通过任何合适的技术来沉积，诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)。
图10A至图10C示出本发明的第三实施例的完成的突起场效应晶体管500的顶视图和垂直截面图。本实施例与前两个实施例相似。然而，如上文提到的，本实施例的突起场效应晶体管500包括同时沿着沟道宽度W和沟道长度L的介电突起103的二维阵列。因此，有效沟道宽度Weff和有效沟道长度Leff可以大于如有源区113之间且沿着栅极层106的实际距离W测量的沟道宽度W和沟道长度L。
图11A至图11C示出了根据又一实施例的介电层102。与图2A和图2B所示的实施例相反，图2A和图2B所示的实施例包括矩形截面的介电突起103，在图11A至图11C所示的实施例中，介电突起103可以具有基本三角形的截面轮廓。即，靠近介电层102顶面的介电突起103的基底可以比远离介电层102顶面的尖端部分宽。多个介电突起103可包括靠近衬底102的第一端和远离衬底102的第二端，并且其中第一端的宽度比第二端的宽度宽。本实施例的三角形截面突起103使有效沟道长度Leff和/或有效沟道宽度Weff连续地增大。然而，突起高度PH以及突起基底宽度PBW可能影响有效沟道宽度Weff和有效沟道长度Leff。
图12A至图12C示出根据又一实施例的介电层102。与图2A和图2B所示的实施例相反，图2A和图2B所示的实施例包括矩形截面的介电突起103，在图12A至图12C所示的实施例中，介电突起103可以具有“圆化的三角形”截面轮廓。与先前的实施例中一样，靠近介电层102顶面的介电突起103的基底可以比远离介电层102顶面的尖端部分宽。然而，在该实施例中，介电突起103的截面可以具有正弦、抛物线或其他曲线形状。即，靠近介电层102顶面的突起103的基底可以比远离介电层102顶面的尖端部分宽。本实施例的“圆化的三角形”截面突起103使得有效沟道长度Leff和/或有效沟道宽度Weff连续地增大。然而，突起高度PH以及突起基底宽度PBW以及曲率半径可能影响有效沟道宽度Weff和有效沟道长度Leff。
在另一实施例中，以上实施例中的任一实施例的连续沟道层104L可以掺杂有选择为改善连续沟道层104L的稳定性的掺杂剂。掺杂剂可以改善沟道层104L的稳定性。例如，沟道层104L可以掺杂有Si。用于改善沟道层104L的稳定性的其他合适掺杂剂属于本发明的可设想范围内。
在另一实施例中，连续沟道层104L可以包括层压结构。一方面，多层的该层压结构包括具有不同摩尔百分比的In、Ga和Zn的InxGayZnzO层。在实施例中，0<x≤0.5，0<y≤0.5以及0<z≤0.5。在各个实施例中，多层的层压结构包括其他氧化物层，诸如但不限于InWO、InZnO、InSnO、GaOx和InOx。
图13是示出制造突起场效应晶体管300、400、500的一般方法600的流程图。参考步骤602，该方法包括提供衬底的步骤，该衬底包括具有多个介电突起103的介电层102。参考步骤604，该方法包括在介电层102的多个介电突起103上方共形地沉积沟道层104以在两个相邻介电突起103之间形成多个沟槽105的步骤。参考步骤606，该方法包括形成设置在沟道层104上的栅极层106，其中该栅极层106具有配接到沟槽105中的多个栅极突起106P。参考步骤608，该方法包括在栅极层106的任意一侧上形成有源区113的步骤，其中该有源区113可以电连接至沟道层104。
一般地，本发明的结构和方法可用于在后段制程的金属互连层级中形成突起场效应晶体管和突起场效应晶体管的至少一层二维阵列。场效应晶体管(TFT)对于BEOL集成很有吸引力，因为它们可以在低温下进行处理，并且可以为BEOL添加功能，同时可以释放FEOL中的面积。通过将外围器件(诸如功率栅极或I/O器件)从FEOL移到BEOL的更高金属层级，在BEOL中使用TFT可以用作N3或以外的缩放路径。对于给定的器件，将TFT从FEOL移到BEOL可以产生约5-10％的面积缩小。
实施例涉及晶体管，包括具有多个介电突起103的介电层102；沟道层104，其共形地覆盖介电层102的多个介电突起103以在两个相邻的介电突起103之间形成多个沟道105；设置在沟道层上的栅极层106。栅极层106具有配接到沟槽105中的多个栅极突起106P。该晶体管还包括形成在栅极层106的任意一侧上的有源区113。有源区113电连接至沟道层104。
另一实施例涉及集成半导体器件，其包括位于集成半导体器件的后段制程(BEOL)部分中的突起场效应晶体管300、400、500。突起场效应晶体管300、400、500包括具有多个介电突起103的介电层102；沟道层104，其共形地覆盖介电层102的突起103以在两个相邻介电突起103之间形成多个沟槽105；以及设置在沟道层104上的栅极层106。栅极层106具有配接到沟槽105中的多个栅极突起106P。突起场效应晶体管300、400、500还包括可形成在栅极层106的任意一侧上的有源区113。有源区113电连接至沟道层104。
另一实施例涉及制造突起场效应晶体管300、400、500的方法，该方法包括提供衬底，该衬底包括具有多个介电突起103的介电层102；共形地形成覆盖介电层102的突起103的沟道层104，以在两个相邻的介电突起103之间形成多个沟槽105；形成设置在沟道层上的栅极层106。栅极层106具有配接到沟槽105中的多个栅极突起106P。该方法还包括在栅极层106的任意一侧上形成有源区113。有源区113电连接至沟道层104。
本申请的一些实施例提供了一种晶体管，包括：介电层，具有多个介电突起；沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。在一些实施例中，所述多个栅极突起沿着始于所述有源区的第一方向形成为一维阵列。在一些实施例中，所述多个栅极突起沿着与始于所述有源区的第一方向垂直的第二方向形成为一维阵列。在一些实施例中，所述多个栅极突起包括沿着始于所述有源区的第一方向和垂直于所述第一方向的第二方向的二维阵列。在一些实施例中，所述多个介电突起包括靠近衬底的第一端和远离所述衬底的第二端，以及其中，所述第一端的宽度比所述第二端的宽度宽。在一些实施例中，所述多个介电突起的每个介电突起具有三角形截面轮廓。在一些实施例中，所述多个介电突起的每个介电突起具有圆化的三角形截面轮廓。在一些实施例中，所述沟道层是层压结构，所述层压结构包括InWO层、InZnO层、InSnO层、GaOx层、InOx层或其组合。在一些实施例中，晶体管还包括接触所述有源区的有源区通孔接触件，所述有源区通孔接触件包括TiN、W、Al、Cu或其组合。在一些实施例中，所述沟道层是包括具有不同浓度的In、Ga和Zn的多个InGaZnO层的层压结构。
本申请的另一些实施例提供了一种集成半导体器件，包括：突起场效应晶体管，位于所述集成半导体器件的后段制程(BEOL)部分中，所述突起场效应晶体管包括：介电层，具有多个介电突起；沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。在一些实施例中，所述突起场效应晶体管包括功率栅极、逻辑晶体管、输入/输出器件或用于存储器元件的选择器。
本申请的又一些实施例提供了一种制造突起场效应晶体管的方法，包括：提供衬底，所述衬底包括具有多个介电突起的介电层；共形地形成覆盖所述多个介电突起的沟道层以在两个相邻的介电突起之间形成多个沟槽；形成设置在所述沟道层上的栅极层，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及在所述栅极层的任意一侧上形成有源区，其中，所述有源区电连接至所述沟道层。在一些实施例中，形成所述栅极层使得所述多个栅极突起沿着所述有源区之间的第一方向形成为一维阵列。在一些实施例中，形成所述栅极层使得所述多个栅极突起沿着所述有源区之间的垂直于第一方向的第二方向形成为一维阵列。在一些实施例中，形成所述栅极层使得沿着所述有源区之间的第一方向和垂直于所述第一方向的第二方向产生突起的二维阵列。在一些实施例中，提供包括具有多个介电突起的介电层的衬底包括：形成所述多个介电突起，使得所述介电突起包括靠近所述衬底的第一端和远离所述衬底的第二端，以及其中，所述第一端的宽度比所述第二端的宽度宽。在一些实施例中，方法还包括形成具有三角形截面轮廓的所述多个介电突起的每个。在一些实施例中，共形地形成沟道层包括：形成包含具有不同浓度的In、Ga和Zn的InGaZnO层的层压结构。在一些实施例中，方法还包括形成具有圆化的三角形截面轮廓的所述多个介电突起的每个。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种晶体管，包括：
介电层，具有多个介电突起；
沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；
栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及
有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。
2.根据权利要求1所述的晶体管，其中，所述多个栅极突起沿着始于所述有源区的第一方向形成为一维阵列。
3.根据权利要求1所述的晶体管，其中，所述多个栅极突起沿着与始于所述有源区的第一方向垂直的第二方向形成为一维阵列。
4.根据权利要求1所述的晶体管，其中，所述多个栅极突起包括沿着始于所述有源区的第一方向和垂直于所述第一方向的第二方向的二维阵列。
5.根据权利要求1所述的晶体管，其中，所述多个介电突起包括靠近衬底的第一端和远离所述衬底的第二端，以及其中，所述第一端的宽度比所述第二端的宽度宽。
6.根据权利要求5所述的晶体管，其中，所述多个介电突起的每个介电突起具有三角形截面轮廓。
7.根据权利要求5所述的晶体管，其中，所述多个介电突起的每个介电突起具有圆化的三角形截面轮廓。
8.根据权利要求1所述的晶体管，其中，所述沟道层是层压结构，所述层压结构包括InWO层、InZnO层、InSnO层、GaOx层、InOx层或其组合。
9.一种集成半导体器件，包括：
突起场效应晶体管，位于所述集成半导体器件的后段制程(BEOL)部分中，所述突起场效应晶体管包括：
介电层，具有多个介电突起；
沟道层，共形地覆盖所述多个介电突起以在两个相邻的介电突起之间形成多个沟槽；
栅极层，设置在所述沟道层上，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及
有源区，形成在所述栅极层的任意一侧上，其中，所述有源区电连接至所述沟道层。
10.一种制造突起场效应晶体管的方法，包括：
提供衬底，所述衬底包括具有多个介电突起的介电层；
共形地形成覆盖所述多个介电突起的沟道层以在两个相邻的介电突起之间形成多个沟槽；
形成设置在所述沟道层上的栅极层，其中，所述栅极层具有配接在所述沟槽中的多个栅极突起；以及
在所述栅极层的任意一侧上形成有源区，其中，所述有源区电连接至所述沟道层。
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