CN111566803B - 用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法 - Google Patents

用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法 Download PDF

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CN111566803B
CN111566803B CN201880085673.8A CN201880085673A CN111566803B CN 111566803 B CN111566803 B CN 111566803B CN 201880085673 A CN201880085673 A CN 201880085673A CN 111566803 B CN111566803 B CN 111566803B
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fin structure
stacked
channel
stacked fin
channel material
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CN111566803A (zh
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杰弗里·史密斯
苏巴迪普·卡尔
安东·J·德维莱尔
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Tokyo Electron Ltd
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Abstract

一种制造半导体器件的方法，该方法包括：提供衬底，该衬底包括用于形成第一环绕栅极(GAA)晶体管的沟道的第一堆叠翅片结构和用于形成第二GAA晶体管的沟道的第二堆叠翅片结构，第一堆叠翅片结构包括初始体积的第一沟道材料，第二堆叠翅片结构包括初始体积的第二沟道材料；将第二沟道材料的所述初始体积相对于第一沟道材料的初始体积减小预定量，该预定量对应于第一GAA晶体管的延迟；相应地围绕所述第一沟道材料和所述第二沟道材料形成第一GAA栅极结构和第二GAA栅极结构。

Description

用于控制纳米线或纳米片晶体管器件的晶体管延迟的方法
相关申请的交叉引用
本公开要求于2017年12月4日提交的美国临时申请No.62/594,352“Method forControlling Transistor Delay and for Balancing ofNMOS and PMOS Nanowires onNanosheets in Transistor Devices(用于在晶体管器件中控制晶体管延迟以及平衡纳米片上的NMOS纳米线和PMOS纳米线的方法)”的权益，该临时申请的全部内容通过参引并入本文中。
技术领域
本公开涉及制造诸如集成电路以及用于集成电路的晶体管和晶体管部件的半导体器件的方法。
背景技术
本文提供的背景描述是为了总体地呈现本公开的背景的目的。在此背景技术部分中所描述的工作的范围内的当前署名的发明人的工作以及说明书的在提交申请时可能原本没有资格被视为现有技术的各方面，均不被明确承认或暗示承认为相对于本公开的现有技术。
在半导体器件的制造期间，执行各种制造过程，比如成膜沉积、蚀刻掩模生产、图案化、光刻胶显影、材料蚀刻和去除以及掺杂处理。重复进行这些过程以在衬底上形成期望的半导体器件元件。历史上，利用微制造，已经在一个平面中形成了晶体管，并在上面形成了布线/金属化，并且晶体管因此已被表征为二维(2D)电路或2D制造。缩放工作极大地增加了2D电路中每单位面积的晶体管数量，但是随着缩放进入个位数纳米半导体器件制造节点，缩放工作正面临更大的挑战。半导体器件制造商已经表达了对三维(3D)半导体器件的需求，在这种器件中，晶体管和标准单元彼此叠置地堆叠，以作为继续缩放的一种手段。3D半导体器件的制造提出了许多新的且独特的挑战，这些挑战涉及新的工艺整合、新颖的硬件和处理能力、设计、制造后处理、电子设计自动化以及3D制造工艺的其他方面。
发明内容
在一个实施方式中，制造半导体器件的方法包括：提供包括第一堆叠翅片结构和第二堆叠翅片结构的衬底，该第一堆叠翅片结构用于形成第一环绕栅极(GAA)晶体管的沟道，该第一堆叠翅片结构包括初始体积的第一沟道材料，该第一沟道材料设置在第一牺牲材料的上部部分与下部部分之间，使得第一沟道材料和第一牺牲材料在第一堆叠翅片结构的侧部处暴露，该第二堆叠翅片结构用于形成第二GAA晶体管的沟道，该第二堆叠翅片结构包括初始体积的第二沟道材料，该第二沟道材料设置在第二牺牲材料的上部部分与下部部分之间，使得第二沟道材料和第二牺牲材料在第二堆叠翅片结构的侧部处暴露；使第二沟道材料的所述初始体积相对于第一沟道材料的初始体积减小预定量，该预定量对应于第一GAA晶体管的延迟；以及分别围绕所述第一沟道材料和所述第二沟道材料形成第一GAA栅极结构和第二GAA栅极结构。
在另一个实施方式中，半导体器件包括：具有平坦表面的衬底；第一环绕栅极场效应晶体管(GAA-FET)，该第一环绕栅极场效应晶体管设置在所述衬底上并且包括第一沟道，第一沟道具有未修整体积的第一沟道材料，该未修整体积对应于第一沟道材料在第一堆叠翅片结构内的体积，第一沟道由该第一堆叠翅片结构形成；以及第二环绕栅极场效应晶体管，该第二环绕栅极场效应晶体管设置在所述衬底上并且包括第二沟道，该第二沟道具有修整体积的第二沟道材料，该修整体积比第一沟道材料的所述未修整体积小预定修整量，该预定修整量对应于第二环绕栅极场效应晶体管相对于第一环绕栅极场效应晶体管的延迟调整，其中，所述第一环绕栅极场效应晶体管和所述第二环绕栅极场效应晶体管作为互补的场效应晶体管而电连接。
在另一实施方式中，制造半导体器件的方法包括：提供包括第一堆叠翅片结构和第二堆叠翅片结构的衬底，该第一堆叠翅片结构用于形成第一环绕栅极(GAA)晶体管的沟道，该第一堆叠翅片结构包括初始体积的第一沟道材料，该第一沟道材料设置在第一牺牲材料的上部部分与下部部分之间，使得第一沟道材料和第一牺牲材料在第一堆叠翅片结构的侧部处暴露，该第二堆叠翅片结构用于形成第二GAA晶体管的沟道，该第二堆叠翅片结构包括初始体积的第二沟道材料，该第二沟道材料设置在第二牺牲材料的上部部分与下部部分之间，使得第二沟道材料和第二牺牲材料在第二堆叠翅片结构的侧部处暴露；使第二沟道材料的所述初始体积相对于第一沟道材料的初始体积减小预定量，该预定量对应于第一GAA晶体管的阈值电压；以及分别围绕所述第一沟道材料和所述第二沟道材料形成第一GAA栅极结构和第二GAA栅极结构。
注意，本发明内容部分并未明确指出本公开或所要求保护的发明的每个实施方式和/或递增的新颖方面。替代地，该发明内容仅提供对不同实施方式和对应的新颖性点的初步论述。对于本发明和各实施方式的附加细节和/或可能的观点，读者请参照如下文进一步论述的本公开的具体实施方式部分和对应附图。
附图说明
将参照以下附图详细描述本公开的作为示例提出的各种实施方式，其中，相似的附图标记表示相似的元件，并且在附图中：
图1示出了根据本公开的实施方式的三输入与非(NAND)电路的示例布局；
图2A示出了根据本公开实施方式的纳米线/纳米片场效应晶体管结构的等距视图；
图2B示出了制造半导体器件的方法的工艺流程；
图3示出了根据本公开的实施方式的翅片结构的横截面图，其中，掩模材料保护一组沟道；
图4示出了根据本公开的实施方式的包括已经被蚀刻的顶部沟道组的翅片结构的横截面图；
图5示出了根据本公开的实施方式的翅片结构的横截面图，该翅片结构包括已被蚀刻的顶部沟道组和已凹入的掩模材料；
图6示出了根据本公开的实施方式的翅片结构的横截面图，其中，块体翅片材料已被去除；
图7示出了根据本公开的实施方式的环绕栅极晶体管器件；
图8示出了根据本公开的实施方式的具有两种不同的沟道材料的翅片结构的横截面图，其中掩模材料保护一组沟道；
图9示出了根据本公开的实施方式的具有两种不同的沟道材料的翅片结构的横截面图，其中顶部沟道组已经被选择性蚀刻；
图10示出了根据本公开的实施方式的具有两种不同的沟道材料的翅片结构的横截面图，其中，块体翅片材料已被去除；以及
图11示出了根据本公开的实施方式的具有两种不同的沟道材料的环绕栅极晶体管器件。
具体实施方式
本文中描述的步骤的论述顺序是为清楚起见而呈现出的。总体上，这些步骤可以以任何合适的顺序执行。另外，尽管本文中的不同特征、技术、构型等中的每一者可能是在本公开的不同地方论述的，但是意图在于每个概念都可以彼此独立地或彼此组合地执行。因此，可以以许多不同的方式来实施和看待本发明。
现在参照附图，其中，贯穿若干视图，相似的附图标记表示相同或对应的部分，以下描述涉及用于通过各种各样的蚀刻技术来平衡晶体管器件中的晶体管延迟的系统、设备和相关联的方法。
某些类型的晶体管器件以互补的方式使用N型金属氧化物半导体(NMOS)以及P型金属氧化物半导体(PMOS)。NMOS器件基于电子的迁移率，相比于作为PMOS器件基础的空穴的迁移率，电子的迁移率可以快若干倍。已经开发出了通过在PMOS沟道上引起应变以增加PMOS器件中的迁移率或者通过将PMOS器件的沟道材料直接从硅改为硅锗来解决这种不匹配的方法。还有其他一些因素比如材料、排布、尺寸等会影响场效应晶体管(FET)中的晶体管延迟。例如，与场效应晶体管器件内NMOS与PMOS平衡相关联的延迟也可以是下述因素的结果：与互补的有源区域相比时，NMOS或PMOS有源区域中从电源轨至输出线的供给部之间的晶体管的数量之间不匹配。这种情况的示例在图1中示出，对应于包括有源PMOS区域110和有源NMOS区域120的三输入NAND电路布局100的情况。如所见，布局100包括栅极区域131、132和栅极区域133，所述栅极区域中的每个栅极区域向一对互补的晶体管提供公共栅极输入端(A、B或C)。
如NMOS有源区域120中的虚线箭头所示，进入NMOS有源区域120中Vss节点141的来自Vss轨140的供给在Vout节点151处到达Vout端子150之前将穿过三个晶体管。同时，在3出入NAND器件中Vdd的供给可以分为两个独立的点，使得对于PMOS有源区域110中来自Vdd轨160的供给而言只需要穿过单个晶体管即可到达Vout端子152。例如，如PMOS有源区域110中的虚线箭头所示(示出了三个不同的路径)，进入节点161的来自Vdd轨160的供给在到达Vout节点152之前将穿过单个晶体管。因此，由于与PMOS有源区域110相比需要穿过的晶体管数量增加为三倍而为NMOS有源区域120引入了延迟。在一些单元设计中，在有源区域之间的晶体管数量中的这种不平衡导致延迟效应，尤其是当通过给定晶体管的输出随后在给定单元设计中作为输入被供给至另一个晶体管时。
这种不平衡可以通过增加有源区域中的翅片结构的数量作为晶体管不平衡的一部分来解决。考虑三输入NAND单元作为示例，针对对应的PMOS有源区域中的每一个翅片结构，NMOS有源区域将使用三个翅片结构。此技术可以用于翅片式场效应晶体管(FinFET)处理和纳米线或纳米片处理，在翅片式场效应晶体管处理中器件沟道是翅片结构本身，在纳米线或纳米片处理中器件沟道由从基础翅片结构提供的一个或更多个离散的纳米结构组成。这种方法在此类2D设计中非常简单直接，并且只涉及在初始的翅片图案化过程(通常经由在图案化过程的开始、中间或结束时执行翅片切割(翅片去除)的自对准四重图案化(SAQP)进行)期间或者在翅片已经转移至块体硅中之后去除翅片结构。例如，利用这种2D设计，器件沟道在通常作为衬底的工作表面(例如晶片)的xy平面中分离。蚀刻系统可以垂直于衬底的工作表面(在z平面)定向蚀刻，并且因此可以使用蚀刻掩模来阻挡或切割横向间隔开的翅片或沟道，只要可以达到期望的分辨率即可。当晶体管沟道彼此叠置地竖向堆叠时，这种定向蚀刻技术是不合适的。
对于竖向堆叠的纳米线和/或纳米片的情况以及对于在3D构型中的互补场效应晶体管器件(CFET)的情况而言，平衡NMOS和PMOS沟道数更具挑战性，因为沟道不作为可以在后续图案化步骤期间简单地从器件上切除的独立实体而存在。
利用这样的3D电路，纳米线或纳米片可以彼此叠置地堆叠，其中在竖向堆叠的纳米线或纳米片之间具有非常有限的距离(类似于下面描述的图2的结构)。该分离距离可以为10nm以下的等级。因此，在3D电路中去除个别的纳米线或纳米片可以包括以很小的误差容差极其精确地定位切割介质、例如已被平坦化并向下凹陷的沉积膜。这样的平坦化和凹陷需要在整个晶片上的竖向堆叠的纳米线或纳米片之间的相对较高的精度。本发明人认识到即使使用自下而上的选择性沉积的膜沉积工艺，在复杂的拓扑结构内进行这种膜放置的能力也是有挑战性的。
作为另一选择，纳米线或纳米片可以彼此配对。例如，代替使四个堆叠的PMOS或NMOS纳米线或纳米片沟道在公共的原始翅片结构内竖向堆叠，将翅片数加倍使得在每个翅片结构上存在两个堆叠的线。该技术为使用上述简单的翅片切割技术提供了一些余量以适应晶体管平衡。该技术的一个缺点是，要将附加的翅片节距结合至给定的单元高度中。此外，如对于三输入NAND单元的情况来说将需要的，只能通过去除成对的沟道而不是去除单个沟道来处理延迟。更一般而言，通过完全去除即使单个沟道来实现的平衡也被限制在基于与整个沟道相关联的延迟的离散的调整值。
对于包括竖向堆叠在其互补沟道上的PMOS沟道或NMOS沟道(纳米线或纳米片)的互补场效应晶体管(CFET)器件而言，挑战增加。在这种构型中，将原始翅片结构配对对于CFET的情况不再有效，因为这将去除单个基础翅片结构内的NMOS沟道和PMOS沟道两者。
本文中的技术提供了实现这种3D CFET器件和其他CFET器件的晶体管平衡的方法。本文中的技术通过使用PMOS沟道和NMOS沟道材料的蚀刻选择性修整而不是完全去除沟道来提供平衡。对于三输入NAND单元的情况，代替驱动三个NMOS纳米线沟道和单个PMOS纳米线沟道，原始翅片数可以包含用于NMOS和PMOS两者的全部三个纳米线。该技术可以包括下述方法：其中，PMOS沟道被“修整”成使得剩余沟道的电容效应将校正晶体管的不平衡。因此，在该示例中，可以相对于NMOS线的尺寸修整PMOS线，以校正该不平衡或产生期望的平衡。
图2A示出了本公开的技术可以提供的示例结构。如所看到的，结构200包括衬底201，衬底201具有位于其上的基础翅片结构203。每个基础翅片结构203包括沿高度方向h堆叠在基础翅片203内的沟道材料205和牺牲材料207的交替层。基础翅片结构203沿着衬底201的宽度方向w以及沿着长度方向l横向地间隔开。每个基翅片结构203可以用于形成一个或更多个第一环绕栅极(GAA)晶体管。在图2A的示例结构中，基础翅片结构203各自包括用于形成第一GAA晶体管的沟道区域的第一堆叠翅片结构210和用于形成第二GAA晶体管的沟道区域的第二堆叠翅片结构220。第一堆叠翅片结构210和第二堆叠翅片结构220各自包括设置在牺牲材料207的下部部分与上部部分之间的沟道材料205的初始体积。虽然堆叠翅片结构210、220各自都被示出为包括两层沟道材料205，但是可以仅使用单层。如下文进一步论述，下部堆叠翅片结构210可以用于提供例如NMOS器件，而上部堆叠翅片结构220可以用于形成PMOS器件。
图2B示出了用于制造半导体器件的方法的工艺流程。如所看到的，该工艺包括提供其上具有第一堆叠翅片结构210和第二堆叠翅片结构220的半导体衬底的步骤251。这样的堆叠翅片结构210、220可以设置在单个基础翅片内，或者设置在衬底上彼此横向分离的单独翅片中。第一堆叠翅片结构210用于形成第一环绕栅极(GAA)晶体管的沟道，并且第二堆叠翅片结构220用于形成第二GAA晶体管的沟道。第一堆叠翅片结构210包括初始体积的第一沟道材料，其设置在第一牺牲材料的上部部分与下部部分之间，使得第一沟道材料和第一牺牲材料在第一堆叠翅片结构210的侧部处暴露。第二堆叠翅片结构220包括初始体积的第二沟道材料，其设置在第二牺牲材料的上部部分与下部部分之间，使得第二沟道材料和第二牺牲材料在第二堆叠翅片结构220的侧部处暴露。
在步骤253中，第二沟道材料的初始体积相对于第一沟道材料的初始体积减小了预定量。可以通过蚀刻“修整”沟道材料的初始体积的一部分来进行这种减小。预定的体积减小量对应于第一GAA晶体管的延迟。因此，该减小允许调整第一GAA晶体管的晶体管延迟，并且可以允许在第一GAA晶体管与第二GAA晶体管之中对延迟进行平衡。
在步骤255中，分别围绕第一沟道材料和第二沟道材料而形成第一GAA栅极结构第二GAA栅极结构。更具体地说，第一牺牲材料和第二牺牲材料被去除以“释放”第一沟道材料和第二沟道材料。然后，围绕被释放的沟道材料中的每一者而形成GAA栅极结构。第一GAA结构和第二GAA结构可以被电连接，使得它们彼此互补。因此，沟道材料中的一者从其初始体积的减小可以用于平衡互补器件中的延迟。
在一个实施方式中，通过修整的平衡技术可以应用于2D设计，在2D设计中，有源区域设置在横向间隔开的基础翅片结构中。在一个实施方式中，第一有源区域包括第一类型的晶体管、例如NMOS，并且第二有源区域包括第二类型的晶体管、例如PMOS。第一有源区域包括包含有第一类型的沟道、例如NMOS沟道的至少一个翅片结构。第二有源区域包括包含有第二类型的沟道、例如PMOS沟道的至少一个翅片结构。这些沟道可以是单个纳米线或纳米片沟道，或者由单个基础翅片结构形成的多个纳米结构。对具有这种2D设计的NMOS沟道或PMOS沟道的选择性修整非常简单直接，因为每组线都存在于其独特的有源区域(即基础翅片)中。这样，可以在执行蚀刻之前沉积掩模图案，使得例如为具有NMOS沟道的NMOS有源区域的一个有源区域不被蚀刻，而第二有源区域、例如具有PMOS沟道的PMOS有源区域受到蚀刻的影响。因此，可以通过“修整”PMOS沟道而不是完全去除基础翅片结构以及与其关联的所有沟道来平衡晶体管延迟。
对于其中NMOS沟道和PMOS沟道在同一基础翅片结构上的CFET器件的实施方式，该方法变得更具挑战性。但是，本文中有多种技术可以用于选择性地修整同一原始翅片结构内的NMOS和PMOS。例如，本发明人认识到，尽管NMOS沟道和PMOS沟道设置在同一基础翅片结构上，但是在NMOS沟道PMOS沟道的竖向位置方面存在一定程度的容差度量，使得在NMOS沟道与PMOS沟道之间的竖向(z平面)边界处可以存在大于10nm的间隔。这种较大的间隔可以促进材料填充，然后进行平坦化(CMP)，且然后向下凹陷以使NMOS或PMOS相对于其互补体选择性地打开。
在另一个实施方式中，在NMOS与PMOS之间使用不同的沟道材料，并且块体初始翅片结构可以由外延生长的膜组成，该膜对NMOS和PMOS的预期沟道材料两者都具有选择性以增加PMOS区域中空穴的迁移率。该实施方式的示例包括SiGe作为PMOS沟道材料、Si作为NMOS沟道材料以及特定类型的掺杂硅作为线释放过程中最终将被去除的翅片非沟道材料。在该实施方式中，使用具有不同蚀刻特性的至少两种沟道材料，其中，可以蚀刻第一沟道材料而不蚀刻(去除)第二沟道材料或第三块体翅片沟道材料。
所提出的利用对NMOS沟道或PMOS沟道的选择性修整的方法不仅适用于控制晶体管延迟，而且还可以用于控制阈值电压(Vt)。通常，通过在沟道上设定不同功函数金属厚度来调节Vt。在典型的FINFET或环绕栅极(GAA)器件中，这通常是通过在所有沟道上沉积预定量的功函数金属且然后利用一组复杂的阻挡掩模来实现的，这些阻挡掩模可以用于打开选定的晶体管以在待调节的晶体管上回蚀预定量的功函数金属。对于3D架构、比如其中NMOS器件和PMOS器件彼此叠置地堆叠的互补FET(CFET)，这种Vt调节方法执行起来可能是复杂的。该方法可以提出一种对3D逻辑器件的Vt进行调节的方式，其中，可以调整初始沟道宽度以控制Vt，而不是仅改变功函数金属的厚度。
本文中的技术使得能够通过改变沟道材料的体积来改变半导体沟道材料中的Vt或电延迟。本文中的工艺使得能够缩小翅片结构内的一层或更多层沟道材料，从而致使沟道材料部段的体积较小或横截面体量较小。可以通过沉积各种不同的层以形成期望的翅片堆叠来形成翅片结构。这可以包括在多个第二沟道材料层的顶部上形成的多个第一沟道材料层。每层沟道材料可以由诸如块体材料或载体材料之类的牺牲材料而隔开。在形成层堆叠件之后，可以在其上形成蚀刻掩模，并且该蚀刻掩模用于将图案非等向性地转移通过材料堆叠件，从而形成翅片结构(具有多个不同层的材料的线)。使用一个蚀刻掩模导致每一层具有基本相同的初始体积。对于某些设计，缩小沟道材料中的一些沟道材料以产生改变的(减小的)体积可能是有益的，改变的体积进而又导致产生不同的电延迟值或Vt。因此，不同类型的材料(NMOS和PMOS)可以彼此叠置地堆叠并形成有相同的初始体积，且然后选择性地缩小以改变沟道材料的体积，从而针对每种类型的材料产生期望的延迟或Vt。
返回至图2B的示例，图3示出了堆叠翅片结构300。堆叠翅片结构300可以提供具有多个沟道305的目标NMOS区域310和目标PMOS区域320。多个沟道305可以是纳米线或纳米片。在一个实施方式中，目标NMOS区域310或PMOS区域320的有源区域可以借助于阻挡掩模而被保护，同时保持互补体暴露以便被蚀刻。在互补体受保护的情况下，可以对暴露的纳米线或纳米片进行蚀刻。这样的重新制定尺寸可以通过选择性蚀刻修整来执行。这种选择性蚀刻修整可以是等向性的气相修整或化学氧化物去除(COR)。未被覆盖的沟道材料被横向修整，同时在沟道的上表面和下表面上由非沟道块体翅片材料307保护。例如，对于NMOS区域310的情况，选择Si作为沟道材料，并且选择SiGe作为块体翅片材料307。通过这样的选择和构型，蚀刻过程可以借助于对SiGe块体翅片材料307的非常高的选择性(不蚀刻SiGe或不显著蚀刻SiGe)而选择性地使沟道305的宽度横向凹入，从而对NMOS区域310的宽度进行调节。因此，在没有去除个别沟道的情况下平衡了NMOS区域310和PMOS区域320，而是替代性地通过调整延伸通过有源区域的累积沟道材料的总体积或面积来进行平衡。如上所述，由于在个别的纳米线或纳米片之间的间隙可能小于10nm，并且在当前工艺(例如，材料沉积、CMP、凹陷蚀刻)的情况下，以良好的容差安置覆盖膜或阻挡膜以保护任何期望的保留线从而使以刻蚀为目标的沟道305(纳米线或纳米片)暴露可能十分困难，因此在公共基础翅片结构303内移除个别的层变得困难。因此，在一个实施方式中，可以在NMOS区域310与PMOS区域320之间产生相对较大的间隔。
图3示出了堆叠翅片结构300，其中间隔足以实现使用填充材料330、例如电介质填充材料，随后进行CMP，随后进行凹陷以将一组沟道305相对于另一组沟道305进行保护或暴露。例如，电介质填充物330的材料可以包括SiO。在图3的示例中，NMOS区域310和PMOS区域320各自包括Si沟道305。也就是说，NMOS区域和PMOS区域的沟道材料具有相同的化学组成。电介质填充物330已经充分地凹陷以暴露出堆叠翅片结构300的上部部分中NMOS区域310中的沟道305。然后执行选择性蚀刻以横向修整暴露的沟道305的材料。例如，可以执行等向性的气相蚀刻。相对于在对应的翅片组成中使用的其他外延生长的晶体膜、比如SiGe或掺杂的Si，这种气相蚀刻可以具有100：1的蚀刻选择性。在该实施方式中，于是可以在PMOS区域320的沟道305被填充材料330保护而免受蚀刻的情况下对NMOS区域310的沟道305材料进行修整。该蚀刻改变了暴露的NMOS区域310的沟道305材料的轮廓，其中，沟道305的横截面或体积减小。
在一个实施方式中，可以通过在堆叠翅片结构300的顶部上沉积填充材料330而不覆盖PMOS区域320的沟道305材料来保护NMOS区域310的沟道305材料免受蚀刻。例如，填充材料330可以通过成角度的蒸镀的方法选择性地朝向堆叠翅片结构300的顶部沉积。可以在堆叠翅片结构300附近制造多个掩模翅片，以在暴露于成角度的蒸镀时提供掩模，其中，多个掩模翅片防止填充材料330沉积在多个掩模翅片的阴影中。例如，可以通过掠角沉积(GLAD)来提供成角度的蒸镀的方法。
经修整的沟道305材料的量可以基于用于平衡NMOS区域310和PMOS区域320的电学要求或规格，并且可以基于预期的晶体管延迟或Vt来计算，其中，预期的晶体管延迟或Vt可以基于被调节的特定单元的局部区域。因此，蚀刻量可以基于对应单元的尺寸、单元的布局、所使用的材料等。例如，可以使用循环蚀刻工艺将蚀刻调节到几埃的等级。可以使用其他蚀刻选择性工艺，比如原子层蚀刻法(ALE)蚀刻和准ALE。就此而言，这样的修整可以提供精细程度的延迟或Vt调整，这对于依靠如上所述的完全去除沟道的平衡技术是不可能的。
图4示出了示例性受蚀刻的堆叠翅片结构400，其中，暴露的NMOS区域310已经被蚀刻并且具有减小的宽度的沟道305′(即沟道体积)的特征。
在利用挡块填充进行修整蚀刻之后，剩余的填充物330可以被完全去除，或者进一步充分地凹陷以露出下面的沟道材料。图5示出了示例堆叠翅片结构500，其中，填充材料330进一步凹陷以暴露PMOS区域320，但是在适当的位置留下了浅沟槽隔离(STI)部分530。
然后可以针对特定区域、单元等去除牺牲性块体翅片材料307、例如SiGe。图6示出了从堆叠翅片结构去除SiGe块体翅片材料307以提供结构600的示例结果，该结构600包括竖向布置的NMOS 310和PMOS 320的沟道305和宽度减小的沟道305′部分。
如图7中所示，单元制造可以继续进行高k电介质705、NMOS功函数金属710、PMOS功函数金属715和栅极填充金属720的沉积，或者针对特定制造方案指定的其他过程以形成环绕栅极(GAA)晶体管器件700。换句话说，改变沟道305和减小宽度的沟道305′的尺寸以控制由NMOS区域310/PMOS区域320不平衡引起的延迟。在该实施方式中，PMOS区域320和NMOS区域310可以是相同的材料；在一种材料被阻挡或覆盖的情况下，另一种材料可以被重新制定尺寸。
在另一个实施方式中，可以通过选择性蚀刻并使用不同的沟道材料来改变NMOS沟道和PMOS沟道的尺寸或体积。这种尺寸改变控制由NMOS/PMOS不平衡引起的延迟，并提供对一种或两种沟道类型的调节。为了在不同沟道之中进行选择性蚀刻，必须使用多种不同的材料。如图8中所示，基础翅片堆叠件800包括在衬底801上的具有第一沟道材料805的第一堆叠翅片结构810、具有第二沟道材料809的第二堆叠翅片结构820以及牺牲性块体翅片材料807。例如，块体翅片材料807可以是掺杂的硅Si：X、例如Si：B材料。第一堆叠翅片结构810可以是PMOS材料，并且第二堆叠翅片结构820可以是NMOS材料。第一沟道材料805可以是SiGe，并且第二沟道材料809可以是Si，其中块体翅片材料807是第三材料。第一材料、第二材料和第三材料对于特定的蚀刻过程具有不同的蚀刻抗性。第二堆叠翅片结构820可以设置在第一堆叠翅片结构810上方，其中块体翅片材料807将两个区域分开。每种类型的沟道可以有多个沟道。更具体地，可以将不同的沟道材料用于第一沟道材料805和第二沟道材料809两者。注意，这是非限制性的并且可以选择更多的材料及组合。利用具有不同蚀刻抗性的材料，不需要覆盖或阻挡一个有源沟道类型的区域，因为蚀刻抗性本身将保护互补材料和块体材料免受蚀刻(免受显著蚀刻)。
执行蚀刻基础翅片堆叠件800中的一种材料而不蚀刻基础翅片堆叠件800中的其他材料的蚀刻过程。该蚀刻过程可以包括等向性蚀刻，以在任何方向上均匀地蚀刻暴露的材料。基础翅片堆叠件800可以是具有交替的有着不同的蚀刻抗性的材料层的翅片结构。如上所述，可以执行气相蚀刻、化学氧化物去除蚀刻、ALE或准ALE蚀刻。因此，由于沟道的侧壁被暴露，蚀刻导致横向蚀刻。这种选择性蚀刻可以横向修整能够通过特定蚀刻剂和所使用的工艺条件(化学化合物、腔室压力、温度等)蚀刻的给定材料的一部分。
在一个实施方式中，蚀刻过程可以选择性地蚀刻第二堆叠翅片结构820的沟道材料809，而不显著蚀刻第一堆叠翅片结构810的沟道材料805，其中，第二堆叠翅片结构820可以堆叠在第一堆叠翅片810的上方。在另一实施方式中，蚀刻过程可以选择性地蚀刻第一堆叠翅片结构810的沟道材料805，而不显著蚀刻第二堆叠翅片结构820的沟道材料809，其中，第二堆叠翅片结构820可以堆叠在第一堆叠翅片结构810的上方。
图9示出了在选择性蚀刻之后的示例性基础翅片堆叠件900的结果。注意，在该示例中，第二堆叠翅片结构820的沟道材料809′已经被横向蚀刻了预定量，而没有蚀刻第一堆叠翅片结构810的沟道材料805或块体翅片牺牲材料807。
在第一蚀刻过程之后，可以使用第二蚀刻过程来修整其他互补沟道材料(如果需要的话)。修整互补沟道材料可以基于器件设计和电路布局，以产生期望的晶体管延迟或满足晶体管延迟容差或Vt。修整互补沟道材料可以在给定的处理腔室中通过改变蚀刻化学品和蚀刻工艺参数而原位执行。修整的材料量可以基于电学要求或规格，以在沟道材料的竖向堆叠构型中平衡PMOS区域810和NMOS区域820。针对给定沟道材料的蚀刻量可以通过基于预期的晶体管延迟或者Vt的计算来确定，该预期的晶体管延迟或Vt基于针对中继而被调节的给定单元的局部面积或区域。
在蚀刻一种或两种(或更多种)沟道材料之后，块体翅片材料807然后可以被去除以露出区域810、820。可以在未被覆盖的部段中去除块体翅片材料807，使得纳米线或纳米片在每个端部处被支承。图10示出了示例结果。这种块体翅片材料去除也可以在相同的处理腔室比如使用气相蚀刻的腔室/系统中执行。
如图11中所示，在去除块体翅片材料之后，可以比如通过沉积高k电介质1105、NMOS功函数金属1110、PMOS功函数金属1115和栅极填充金属1120来继续进行处理以形成环绕栅极(GAA)沟道。值得注意的是，图11示出了对于PMOS和NMOS彼此叠置的堆叠器件而言通过功函数金属厚度减小来进行Vt调节可能有多困难。对于利用宽的纳米线/纳米片结构的堆叠式器件而言，从线或片的侧部相较于在片的中心底部或中心顶部中去除相同量的金属变得困难，尤其是当上方或下方有其他片时。因此，所公开的Vt调节方法可以通过改变沟道体积而不是改变各个晶体管的功函数金属厚度来实现。
本文描述的这种修整技术使得能够调整一个或两个沟道材料以精确地改变包括3D CFET器件的FET器件中的晶体管延迟或Vt。本领域技术人员能够理解的是，上述描述可能倾向于描述调整晶体管延迟，但是在确定沟道体积减小时，可以以期望的预定阈值电压调节而不是晶体管延迟来作为调整的目标。
在前面的描述中，已经阐述了具体细节、例如处理系统的特定几何形状以及本文中使用的各种部件和过程的描述。然而，应当理解的是，本文中的技术可以在背离这些具体细节的其他实施方式中实行，并且这样的细节是出于解释而非限制的目的。已经参照附图描述了本文中公开的实施方式。类似地，出于解释的目的，已经阐述了具体的数字、材料和构型以便提供透彻的理解。然而，可以在没有这样的具体细节的情况下实践各实施方式。具有基本相同的功能构造的部件由相似的附图标记表示，且因此可以省略任何多余的描述。
已经将各个技术描述为多个离散操作，以帮助理解各个实施方式。描述的顺序不应被解释为暗示这些操作必定与顺序有关。实际上，这些操作不需要按照所示顺序执行。可以以与所述的实施方式不同的顺序来执行所描述的操作。在附加的实施方式中，可以执行各种附加的操作并且/或者可以省略所描述的操作。
如本文中所用，“衬底”或“目标衬底”通常是指根据本发明被处理的物体。衬底可以包括器件、尤其是半导体或其他电子器件的任何材料部分或结构，并且可以例如是基础衬底结构，比如半导体晶片、掩模或基础衬底结构之上或覆盖基础衬底结构的比如薄膜的层。因此，衬底不限于图案化或未经图案化的任何特定基础结构、下方层或上覆层，而是可以被设想为包括任何此类层或基础结构以及层和/或基础结构的任何组合。该描述可能涉及特定类型的衬底，但这仅出于说明目的。
本领域技术人员还将理解的是，可以对上述技术的操作进行许多变型，同时仍然实现本发明的相同目的。这样的变型意在被本公开的范围涵盖。这样，对本发明的各实施方式的前述描述不意在是限制性的。更准确地说，对本发明的各实施方式的任何限制呈现于所附权利要求中。
尽管已经结合作为示例提出的本公开的特定实施方式描述了本公开的各方面，但是可以对示例进行替代、改型和变型。因此，本文中阐述的实施方式意在说明而不是限制。在不背离所附权利要求的范围的情况下可以进行改变。

Claims (14)

1.一种制造半导体器件的方法，所述方法包括：
提供衬底，所述衬底包括：
第一堆叠翅片结构，所述第一堆叠翅片结构用于形成第一环绕栅极(GAA)晶体管的沟道，所述第一堆叠翅片结构包括初始体积的第一沟道材料，所述第一沟道材料设置在第一牺牲材料的上部部分与下部部分之间，使得所述第一沟道材料和所述第一牺牲材料在所述第一堆叠翅片结构的侧部处暴露；以及
第二堆叠翅片结构，所述第二堆叠翅片结构用于形成第二环绕栅极晶体管的沟道，所述第二堆叠翅片结构包括初始体积的第二沟道材料，所述第二沟道材料设置在第二牺牲材料的上部部分与下部部分之间，使得所述第二沟道材料和所述第二牺牲材料在所述第二堆叠翅片结构的侧部处暴露；
遮蔽所述第一堆叠翅片结构的侧壁；
在所述遮蔽之后经由蚀刻所述第二堆叠翅片结构以将所述第二沟道材料的所述初始体积修整成与所述第二环绕栅极晶体管的预定延迟相对应的修整体积而使所述第二沟道材料的所述初始体积相对于所述第一沟道材料的所述初始体积减小预定量，所述预定量对应于所述第一环绕栅极晶体管的延迟；以及
分别围绕所述第一沟道材料和所述第二沟道材料形成第一环绕栅极式栅极结构和第二环绕栅极式栅极结构，
所述方法还包括在所述第一堆叠翅片结构与所述第二堆叠翅片结构之间提供预定厚度的牺牲间隔材料，所述预定厚度选择成提供用于遮蔽所述第一堆叠翅片结构的过程容差。
2.根据权利要求1所述的方法，其中，所述第二堆叠翅片结构在公共基础翅片结构内堆叠在所述第一堆叠翅片结构上方。
3.根据权利要求2的方法，其中，所述第一沟道材料具有与所述第二沟道材料的化学组成相同的化学组成。
4.根据权利要求1所述的方法，其中，牺牲材料的所述预定厚度大于10nm。
5.根据权利要求2所述的方法，其中：
所述第一沟道材料具有与所述第二沟道材料的化学组成不同的化学组成，并且
所述减小包括使第一堆叠沟道结构和第二堆叠沟道结构暴露于等向性蚀刻过程，所述等向性蚀刻过程相对于所述第一沟道材料选择性地蚀刻所述第二沟道材料。
6.根据权利要求1所述的方法，其中，所述第一堆叠翅片结构设置在第一基础翅片结构内，并且所述第二堆叠翅片结构设置在第二基础翅片结构内，所述第二基础翅片结构沿着所述衬底的平坦表面与所述第一基础翅片结构横向地间隔开。
7.根据权利要求6所述的方法，其中，所述减小包括：
遮蔽所述第一基础翅片结构；以及
蚀刻所述第二基础翅片结构减小所述第二沟道材料的所述初始体积。
8.根据权利要求1所述的方法，其中，所述第一堆叠翅片结构在公共基础翅片结构内堆叠在所述第二堆叠翅片结构上方。
9.根据权利要求1所述的方法，其中，
所述第一堆叠翅片结构在公共基础翅片结构内堆叠在所述第二堆叠翅片结构上方，并且
所述第一堆叠翅片结构经由使用成角度的沉积来沉积掩模材料而被遮蔽。
10.根据权利要求9所述的方法，还包括：
至少一个相邻的掩模结构，其中，
所述至少一个相邻的掩模结构的阴影防止所述掩模材料在所述成角度的沉积的期间沉积在所述第二堆叠翅片结构上。
11.一种制造半导体器件的方法，所述方法包括：
提供衬底，所述衬底包括：
第一堆叠翅片结构，所述第一堆叠翅片结构用于形成第一环绕栅极(GAA)晶体管的沟道，所述第一堆叠翅片结构包括初始体积的第一沟道材料，所述第一沟道材料设置在第一牺牲材料的上部部分与下部部分之间，使得所述第一沟道材料和所述第一牺牲材料在所述第一堆叠翅片结构的侧部处暴露；以及
第二堆叠翅片结构，所述第二堆叠翅片结构用于形成第二环绕栅极晶体管的沟道，所述第二堆叠翅片结构包括初始体积的第二沟道材料，所述第二沟道材料设置在第二牺牲材料的上部部分与下部部分之间，使得所述第二沟道材料和所述第二牺牲材料在所述第二堆叠翅片结构的侧部处暴露；
遮蔽所述第一堆叠翅片结构的侧壁；
在所述遮蔽之后经由蚀刻所述第二堆叠翅片结构以将所述第二沟道材料的所述初始体积修整成与所述第二环绕栅极晶体管的预定延迟相对应的修整体积而使所述第二沟道材料的所述初始体积相对于所述第一沟道材料的所述初始体积减小预定量，所述预定量对应于所述第一环绕栅极晶体管的阈值电压；以及
分别围绕所述第一沟道材料和所述第二沟道材料形成第一环绕栅极式栅极结构和第二环绕栅极式栅极结构，
所述方法还包括在所述第一堆叠翅片结构与所述第二堆叠翅片结构之间提供预定厚度的牺牲间隔材料，所述预定厚度选择成提供用于遮蔽所述第一堆叠翅片结构的过程容差。
12.根据权利要求11所述的方法，其中，所述第二堆叠翅片结构在公共基础翅片结构内堆叠在所述第一堆叠翅片结构上方。
13.根据权利要求11所述的方法，其中，
所述第一堆叠翅片结构在公共基础翅片结构内堆叠在所述第二堆叠翅片结构上方，并且
所述第一堆叠翅片结构经由使用成角度的沉积来沉积掩模材料而被遮蔽。
14.根据权利要求13所述的方法，还包括：
至少一个相邻的掩模结构，其中，
所述至少一个相邻的掩模结构的阴影防止所述掩模材料在所述成角度的沉积的期间沉积在所述第二堆叠翅片结构上。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404325B2 (en) * 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
KR102434993B1 (ko) * 2015-12-09 2022-08-24 삼성전자주식회사 반도체 소자
US10825933B2 (en) * 2018-06-11 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around structure and manufacturing method for the same
US20200295127A1 (en) * 2019-03-13 2020-09-17 Intel Corporation Stacked transistors with different crystal orientations in different device strata
US11069679B2 (en) 2019-04-26 2021-07-20 International Business Machines Corporation Reducing gate resistance in stacked vertical transport field effect transistors
US11037905B2 (en) * 2019-04-26 2021-06-15 International Business Machines Corporation Formation of stacked vertical transport field effect transistors
WO2020232025A2 (en) * 2019-05-13 2020-11-19 Board Of Regents, The University Of Texas System Catalyst influenced chemical etching for fabricating three-dimensional sram architectures and optical waveguides
US11710667B2 (en) * 2019-08-27 2023-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same
US11557655B2 (en) 2019-10-11 2023-01-17 Tokyo Electron Limited Device and method of forming with three-dimensional memory and three-dimensional logic
CN112951912B (zh) * 2019-12-10 2024-05-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11302692B2 (en) * 2020-01-16 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
US20210296306A1 (en) 2020-03-18 2021-09-23 Mavagail Technology, LLC Esd protection for integrated circuit devices
US11837280B1 (en) * 2020-05-20 2023-12-05 Synopsys, Inc. CFET architecture for balancing logic library and SRAM bitcell
CN116325174A (zh) * 2020-09-29 2023-06-23 华为技术有限公司 晶体管及其制作方法、集成电路、电子设备
EP4250265A1 (en) 2020-11-20 2023-09-27 Drovid Technologies Method for transmitting and tracking parameters detected by drones by means of a platform as a service (paas) with artificial intelligence (ai)
US20230411398A1 (en) * 2020-11-24 2023-12-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US11527535B2 (en) 2021-01-21 2022-12-13 International Business Machines Corporation Variable sheet forkFET device
US11424120B2 (en) 2021-01-22 2022-08-23 Tokyo Electron Limited Plasma etching techniques
CN113130489A (zh) * 2021-03-12 2021-07-16 中国科学院微电子研究所 一种半导体器件的制造方法
CN115425076A (zh) * 2021-05-14 2022-12-02 三星电子株式会社 纳米片晶体管器件及其形成方法
TW202247478A (zh) * 2021-05-14 2022-12-01 南韓商三星電子股份有限公司 奈米薄片電晶體裝置及其形成方法
US11843001B2 (en) 2021-05-14 2023-12-12 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
US20230066265A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation layers in stacked semiconductor devices
US11837604B2 (en) 2021-09-22 2023-12-05 International Business Machine Corporation Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
US20230086888A1 (en) * 2021-09-23 2023-03-23 International Business Machines Corporation Dual strained semiconductor substrate and patterning
WO2023225155A1 (en) * 2022-05-20 2023-11-23 Tokyo Electron Limited Sequential complimentary fet incorporating backside power distribution network through wafer bonding prior to formation of active devices

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029503A (ja) * 2009-07-28 2011-02-10 Toshiba Corp 半導体装置
CN105518840A (zh) * 2013-10-03 2016-04-20 英特尔公司 用于纳米线晶体管的内部间隔体及其制造方法
WO2017044107A1 (en) * 2015-09-10 2017-03-16 Intel Corporation Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
US9660028B1 (en) * 2016-10-31 2017-05-23 International Business Machines Corporation Stacked transistors with different channel widths
CN106876275A (zh) * 2015-11-30 2017-06-20 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107017205A (zh) * 2015-11-30 2017-08-04 台湾积体电路制造股份有限公司 半导体器件及其制造方法
WO2017171845A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Beaded fin transistor

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283066B (en) * 2004-09-07 2007-06-21 Samsung Electronics Co Ltd Field effect transistor (FET) having wire channels and method of fabricating the same
US8551833B2 (en) * 2011-06-15 2013-10-08 International Businesss Machines Corporation Double gate planar field effect transistors
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
DE112011106004B4 (de) 2011-12-23 2017-07-13 Intel Corporation Halbleiterstruktur und Verfahren zum Herstellen einer CMOS-Nanodraht-Halbleiterstruktur
WO2014018201A1 (en) 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
KR102002380B1 (ko) * 2012-10-10 2019-07-23 삼성전자 주식회사 반도체 장치 및 그 제조 방법
EP3123515B1 (en) * 2014-03-24 2021-04-28 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices and nanowire device with internal spacers
US9818872B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
EP3127862B1 (en) 2015-08-06 2018-04-18 IMEC vzw A method of manufacturing a gate-all-around nanowire device comprising two different nanowires
CN106531632B (zh) * 2015-09-10 2020-01-03 中国科学院微电子研究所 堆叠纳米线mos晶体管制作方法
US20170170268A1 (en) * 2015-12-15 2017-06-15 Qualcomm Incorporated NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES
US9899416B2 (en) 2016-01-11 2018-02-20 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
KR102416133B1 (ko) 2016-01-11 2022-07-01 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102360333B1 (ko) 2016-02-18 2022-02-08 삼성전자주식회사 반도체 장치
TWI625785B (zh) 2016-03-02 2018-06-01 東京威力科創股份有限公司 具有可調節選擇性之等向性矽與矽化鍺蝕刻

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029503A (ja) * 2009-07-28 2011-02-10 Toshiba Corp 半導体装置
CN105518840A (zh) * 2013-10-03 2016-04-20 英特尔公司 用于纳米线晶体管的内部间隔体及其制造方法
WO2017044107A1 (en) * 2015-09-10 2017-03-16 Intel Corporation Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
CN106876275A (zh) * 2015-11-30 2017-06-20 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107017205A (zh) * 2015-11-30 2017-08-04 台湾积体电路制造股份有限公司 半导体器件及其制造方法
WO2017171845A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Beaded fin transistor
US9660028B1 (en) * 2016-10-31 2017-05-23 International Business Machines Corporation Stacked transistors with different channel widths

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