TWI804535B - 製造半導體元件的方法、以及半導體元件 - Google Patents

製造半導體元件的方法、以及半導體元件 Download PDF

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TWI804535B
TWI804535B TW107143425A TW107143425A TWI804535B TW I804535 B TWI804535 B TW I804535B TW 107143425 A TW107143425 A TW 107143425A TW 107143425 A TW107143425 A TW 107143425A TW I804535 B TWI804535 B TW I804535B
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channel
channel material
semiconductor device
sacrificial
manufacturing
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TW201937611A (zh
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傑佛瑞 史密斯
蘇巴迪普 卡爾
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日商東京威力科創股份有限公司
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Abstract

製造半導體元件的方法包含：提供其上具有基鰭結構的基板，該基鰭結 構包含：用於形成第一環繞式閘極(GAA)電晶體之通道的第一堆疊部分，該第一堆疊部分包含第一通道材料；用於形成第二GAA電晶體之通道的第二堆疊部分，該第二堆疊部分包含第二通道材料；及犧牲性部分，其將第一堆疊部分與第二堆疊部分分開，其中第一通道材料、第二通道材料及犧牲性材料彼此具有不同的化學成分；將基鰭結構的側部曝露於等向性蝕刻製程，其選擇性地蝕刻第一通道材料、第二通道材料及犧牲性材料的其中一者；及分別在該第一通道材料及該第二通道材料周圍形成第一及第二GAA閘極結構。

Description

製造半導體元件的方法、以及半導體元件
本揭示內容關於製造半導體元件(諸如積體電路及用於積體電路之電晶體及電晶體元件)的方法。
[相關申請案]
本揭示內容主張於2017年12月4日申請之美國臨時專利申請案第62/594350號的權利，其全部內容於此藉由參照納入本案揭示內容。
本文提供的背景說明係為了一般性地呈現本揭示內容之背景。在此先前技術章節中所述之目前列名發明者的工作成果、以及可能未在申請時以其他方式適格作為習知技術之說明的實施態樣，均不被明示或暗示承認為對於本揭示內容的習知技術。
在半導體元件的製造期間，執行諸多製造製程，諸如膜形成的沉積、蝕刻遮罩之產生、圖案化、光阻顯影、材料蝕刻和移除、及摻雜處理。重複地執行這些製程以在基板上形成期望的半導體裝置元件。歷史上，利用微製造，已使電晶體在一平面中產生，而具有配線/金屬化形成於其上，並因此已被特性化為二維(2D)電路或2D製造。縮放努力已大幅增加2D電路中每單位面積之電晶體的數目，然而隨著縮放進入個位數奈米半導體元件製造節點，縮放努力正面 臨更大的挑戰。半導體元件製造者已表達對於三維(3D)半導體元件的需求，其中元件、電晶體及標準單元堆疊在彼此頂部上作為持續縮放的手段。3D半導體元件的製造引起許多與新製程整合、新穎硬體和製程能力、設計、製造後處理、電子設計自動化、及3D製造製程之其他方面相關之新及罕見的挑戰。
在一實施例中，製造半導體元件的方法包含：提供其上具有基鰭結構的基板，該基鰭結構包含：用於形成第一環繞式閘極(GAA)電晶體之通道的第一堆疊部分，該第一堆疊部分包含第一通道材料；用於形成第二GAA電晶體之通道的第二堆疊部分，該第二堆疊部分包含第二通道材料；及犧牲性部分，其將第一堆疊部分與設置在犧牲性材料之上部與下部間的第二堆疊部分分開，使得第一通道材料、第二通道材料及犧牲性材料在基鰭結構的一側處曝露，其中第一通道材料、第二通道材料及犧牲性材料彼此具有不同的化學成分；將基鰭結構的該側曝露於等向性蝕刻製程，其相對於第一通道材料、第二通道材料及犧牲性材料的其中二者選擇性地蝕刻第一通道材料、第二通道材料及犧牲性材料的其餘者；及分別在該第一通道材料及該第二通道材料周圍形成第一及第二GAA閘極結構。
注意此發明內容章節未明確指出本揭示內容或所請發明的所有實施例及/或增加的新穎實施態樣。取而代之的是，此發明內容僅提供不同實施例的初步討論及新穎性的對應點。對於本發明及實施例的額外細節及/或可能的看法，讀者可參照下方進一步討論的實施方式章節及本揭示內容之相對應的圖式。
100:鰭堆疊
110:第一型通道
120:犧牲性材料
130:第二型通道
145:高k介電質
150:第一型通道功函數金屬
155:第二型通道功函數金屬
160:填充金屬
191:鰭堆疊
192:鰭堆疊
200:鰭堆疊
210:第一型通道
220:犧牲性材料
230:第二型通道
245:高k介電質
250:第一型通道功函數金屬
255:第二型通道功函數金屬
260:填充金屬
291:鰭堆疊
292:鰭堆疊
294:鰭堆疊
300:結構
301:基板
303:基鰭結構
305:通道材料
306:通道材料
307:犧牲性材料
310:第一堆疊鰭部
320:第二堆疊鰭部
351:步驟
353:步驟
355:步驟
400:基板區段
500:基板區段
將參照以下圖式詳細描述作為示例提出之本揭示內容的諸多實施例，其中類似的號碼指示類似的元件，且其中：圖1A顯示根據本揭示內容的實施例之奈米線/奈米片FET結構的等角視圖；圖1B顯示根據本揭示內容的實施例之製造半導體元件之方法的製程流程；圖2A顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中遮罩材料保護一組通道；圖2B顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中一組頂部通道已選擇性地受蝕刻；圖2C顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中犧牲性材料已被移除；圖2D顯示根據本揭示內容的實施例之具有兩不同通道材料的環繞式閘極電晶體元件；圖3A顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中底部通道被製造成比該組頂部通道厚；圖3B顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中底部通道被蝕刻以產生垂直通道；圖3C顯示根據本揭示內容的實施例之具有兩不同通道材料之鰭結構的橫截面圖，其中通道已被蝕刻以產生垂直通道，且犧牲性材料已被移除；圖3D顯示根據本揭示內容的實施例之具有兩組不同通道的環繞式閘極電晶體元件，其中通道的其中一者是垂直通道；圖3E顯示根據本揭示內容的實施例之具有兩組不同通道的環繞式閘極電晶體元件，其中通道的其中一者是垂直通道； 圖4顯示根據本揭示內容的實施例之在源極/汲極和接點金屬化後之基板區段的立體橫截面圖；及圖5顯示根據本揭示內容的實施例之在摻雜的矽(或其他間隔件/填充物)的移除後及在閘極金屬化後之基板區段的立體橫截面圖。
以下揭示內容提供用於實施所提供之申請標的之不同特徵的許多不同實施例或示例。元件及配置的特定示例係於以下描述以簡化本揭示內容。當然，這些僅為示例且非意圖為限制性的。舉例而言，在隨後的描述中，第二特徵部上方或之上之第一特徵部的形成可包含第一及第二特徵部形成為直接接觸的實施例，且亦可包含額外特徵部可在第一及第二特徵部之間形成使得第一及第二特徵部可不直接接觸的實施例。此外，本揭示內容在諸多示例中可重複參考符號及/或字母。此重複係為了簡單及清楚之目的，且其本身並未規定所討論的諸多實施例及/或配置之間的關係。此外，為了易於描述，本文可使用諸如「在...下方」、「在...下面」、「下面的」、「在...上面」、「上面的」等空間上相對的術語，以描述與如圖中描繪之別的元件或特徵部之一元件或特徵部的關係。除了圖中描繪的定向之外，空間上相對性術語意圖涵蓋使用或操作中之裝置的不同定向。設備可以其他方式定向(旋轉90度或在其他定向)，且本文使用之空間上相對的描述詞同樣地可相應地解釋。
如本文描述之不同步驟的討論順序已為了清楚起見而呈現。通常，這些步驟可以任何適當的順序執行。此外，雖然本文各個不同的特徵、技術、配置等可在本揭示內容的不同地方討論，但吾人欲使各概念可彼此獨立或彼此結合而實行。因此，本發明可以許多不同的方式體現及審視。
注意，儘管本文示例實施例聚焦在矽和矽鍺上，但此聚焦係為了方便而非限制性的。本文技術亦可與任何磊晶生長材料或其摻雜的形式一起使用。此包含Si、P摻雜的Si、B摻雜的Si、SiGe、摻雜的SiGe、Ge及任何其他摻雜或未摻雜的磊晶生長通道材料。本文技術可針對成功的材料凹部及線/片釋放製程而使用氣相蝕刻或化學氧化物移除(COR)製程達成充分的選擇性蝕刻。
隨著功能性縮放不斷減小奈米線及/或奈米片的尺寸以實現區域縮放，重要的挑戰在於給定元件的驅動電流。對於鰭式場效電晶體(FINFET)元件而言，可透過不同源極和汲極(S/D)或甚至通道材料的選擇個別地將應變施加至pMOS及nMOS元件以改善電子遷移率。對於奈米線/奈米片製程的情況，可改善驅動電流並可藉由在n型金屬氧化物半導體(NMOS)及p型金屬氧化物半導體(PMOS)通道中納入不同材料而改善場效應轉變元件中的控制，以在線及/或奈米片上提供應變。元件上元件(device-on-device)或電晶體上電晶體(transistor-on-transistor)堆疊之挑戰發生在嘗試自不同材料製造兩個元件時，因為其橫向堆疊在彼此頂部之上，而對於FINFET及標準奈米線/奈米片元件而言，有可允許nMOS與pMOS通道間之獨特處理的p/n間隔。對於互補式FET(CFET)元件而言，nMOS與pMOS元件直接堆疊在彼此頂部之上。此外，對於特定設計而言，改變不同通道材料之厚度可導致不同的電性效能。
對於FET元件而言，NMOS通道可由諸如單晶矽的材料形成，而PMOS通道可由諸如SiGe的材料形成。利用其中nMOS及pMOS通道係由被p/n間隔距離分開之獨特FIN結構形成之奈米線及奈米片元件製造的一些方法，NMOS及PMOS就線的材料選擇及釋放材料而言可為二元的，即使其在NMOS(具有SiGe釋放的Si線)與PMOS(具有Si釋放的SiGe線)之間為相反的亦然。在使用磊晶沉積的Si/SiGe堆疊建構期間，可在磊晶沉積序列期間蝕刻NMOS或PMOS目標區域以提供高度不匹配而產生用於給定高度的Si或SiGe奈米線或奈米片。在其 中通道自初始FIN結構中的互補性材料釋放之奈米線/奈米片的線釋放製程期間，始於FIN結構的nMOS可被阻擋，而奈米線釋放製程在pMOS FIN上完成，且反之亦然。
在奈米線處理期間，NMOS部分可與PMOS部分不同地加以處理。例如，對於NMOS處理而言，SiGe可凹陷至低k閘極間隔件中以使殘留的矽線或奈米片突出穿過低k閘極間隔件。相反地，對於PMOS處理而言，矽可選擇性地凹陷至低k閘極間隔件中以使SiGe線突出穿過低k閘極間隔件。在替換閘極中的線釋放製程期間，NMOS閘極可使SiGe移除並留下Si線或奈米片。在PMOS閘極中，可移除矽以產生所需的SiGe線。
本文技術有效地作用於FET元件，因為即使NMOS及PMOS皆在共同的物理性閘極結構之內，兩個電晶體通常彼此分開。對於單獨的nMOS及pMOS物理性閘極的情況而言，pMOS電晶體可藉由納入配置在兩個物理性閘極之間的介電質切口而容易地與nMOS電晶體物理性地分隔。對於在相同的物理性或「共同的」閘極內之nMOS及pMOS電晶體的應用而言，nMOS與pMOS電晶體間的p/n間隔通常可為足夠地寬，以在個別的nMOS及pMOS電晶體上實施獨特的處理。
當NMOS及PMOS通道作為相對於彼此具有不同橫向或垂直定向的線或薄片而存在時，對於FET設計而言處理亦可為直接了當的，因為NMOS及PMOS將存在於單獨的主動區域之內，且因此可彼此個別地受處理，只要在nFET與pFET主動區域之間有足夠的p/n間隔距離。
本文技術有助於實現包含邏輯元件之三維半導體元件的製造。在一實施例中，方法在互補式場效電晶體元件(CFET)之內提供多通道材料，其中PMOS或NMOS奈米線及/或奈米片堆疊在其互補對應物的頂部之上。半導體元件通常在具有元件形成於其上之工作表面的基板(例如單晶矽晶圓)上製造。藉由彼此在「頂部之上」，PMOS及NMOS奈米線或奈米片在垂直於基板之工作表 面的平面中形成。在一實施例中，本文方法提供NMOS及PMOS通道的不同垂直或橫向定向，其係由不同磊晶生長晶體材料構成。
本文技術可應用於使用奈米線或奈米片之隨機和非隨機邏輯的元件製造。本文有幾個實施例、替代方案及優點。實施例可包含磊晶生長晶體材料的三元或甚至更高階基質，該磊晶生長晶體材料在PMOS及NMOS通道存在彼此頂部之上的CFET元件之內作用為多通道材料。本文蝕刻方法提供所需的選擇性，以使磊晶生長材料相對於NMOS或PMOS通道材料以等同性的方式選擇性地凹陷至具有足夠蝕刻選擇性的低k介電閘極間隔件中，使得堆疊的線或片可依序或同時形成。本文蝕刻方法包含其中PMOS或NMOS線/片釋放係在替換閘極之內執行的蝕刻，其中以非常高的選擇性等向性地蝕刻填充磊晶材料以保留NMOS及PMOS通道材料。
可執行沉積方法，其中垂直堆疊的線或片可藉由厚的磊晶生長形成並存在於材料基質之內，使得在磊晶生長選擇性基質中該垂直堆疊的線或片在其底部和頂部上由另一材料形成邊緣。技術包含其中上述厚的磊晶生長膜可相對於上側及下側上的材料加以「修整」的方法。可執行修整，使得薄片或線產生。如此奈米片可具有在水平(xy平面)方向上延伸的縱軸及奈米片的矩形橫截面。在該矩形橫截面的情況下，當矩形的較長邊在xy平面中延伸而較短邊在z平面中延伸時，該矩形橫截面係水平定向的。當矩形的較長邊在z平面中延伸而較短邊在xy平面中延伸時，該矩形橫截面係垂直定向的。諸多定向或旋轉的奈米片可以諸多配置垂直地置放在彼此之上。
圖1A顯示本揭示內容的技術可提供的示例結構。如圖所示，結構300包含其上具有基鰭結構303的基板301。各基鰭結構303包含在基鰭結構303內以高度方向h堆疊之第一通道材料305、犧牲性材料307、及第二通道材料306之交替的層。基鰭結構303沿基板301的寬度方向w以及沿長度方向1橫向地間隔開。各 基鰭結構303可用以形成一或更多第一環繞式閘極(GAA)電晶體。在圖1A的示例結構中，基鰭結構303各者包含用於形成第一GAA電晶體之通道區域的第一堆疊鰭部310及用於形成第二GAA電晶體之通道區域的第二堆疊鰭部320。第一及第二堆疊鰭部310、320各者皆包含設置在犧牲性材料307的下部與上部間之通道材料305、306的初始體積。犧牲性材料307可將第一堆疊鰭部310與第二堆疊鰭部320分開。第一通道材料305、第二通道材料306及犧牲性材料307可在基鰭結構303的一側處曝露，且彼此具有不同的化學成分。雖然第一及第二堆疊鰭部310、320各者皆顯示包含兩層通道材料305、306，但可僅使用單層。第一堆疊鰭部310可用以提供例如NMOS元件，而第二堆疊鰭部320可用以形成PMOS元件，如下進一步討論。
圖1B顯示用於製造半導體元件之方法的製程流程。如圖所示，製程包含提供其上具有基鰭結構303之半導體基板的步驟351，基鰭結構303包含具有至少一第一通道材料305的第一堆疊鰭部310、具有至少一第二通道材料306的第二堆疊鰭部320、及犧牲性材料307。第一堆疊鰭部310係用於形成第一環繞式閘極(GAA)電晶體的通道，而第二堆疊鰭部320係用於形成第二GAA電晶體的通道。第一堆疊鰭部310包含設置在犧牲性材料307的上部與下部間之一初始體積的第一通道材料305，使得第一通道材料305及犧牲性材料307在第一堆疊鰭部310的一側處曝露。第二堆疊鰭部320包含設置在犧牲性材料307的上部與下部間之一初始體積的第二通道材料306，使得第二通道材料306及犧牲性材料307在第二堆疊鰭部320的一側處曝露。
在步驟353中，將第二通道材料306的初始體積相對於第一通道材料305的初始體積例如藉由等向性蝕刻選擇性地減小一預定量。如此減少可藉由蝕刻「修整」第二通道材料306之初始體積的一部分而執行。預定量的體積減小可在第一堆疊鰭部310內產生例如垂直定向的第一通道。
在步驟355中，第一和第二GAA閘極結構分別在第一通道材料305和第二通道材料306周圍形成。更具體而言，移除犧牲性材料307以「釋放」第一及第二通道材料305、306。GAA電晶體結構接著在所釋放之通道材料的每一者周圍形成。第一及第二GAA結構可電性連接，使得其彼此為互補的。
在一實施例中，對於特定蝕刻劑而言，第一、第二及第三材料可具有不同蝕刻抗性。如圖2A中所描繪，蝕刻之前的鰭堆疊100包含犧牲性材料120(例如Si：B或摻雜的矽)、用於第一型通道110的第一材料(例如SiGe)、及用於第二型通道130的第二材料(例如Si)，其中犧牲性材料120是第三材料。第一型通道110可設置在第二型通道130上方，其中犧牲性材料120將兩通道分開。可有各通道類型的複數通道。更具體而言，可將不同通道材料用於NMOS及PMOS奈米線或奈米片兩者。注意這是非限制性的，且可選擇更多材料及組合。利用具有不同蝕刻抗性之材料，不需覆蓋或阻擋一主動通道型區域，因為蝕刻抗性本身將保護互補性及主體材料免於受到蝕刻(顯著地受蝕刻)。
矽或SiGe線或片可透過高選擇性等向性蝕刻製程藉由互補性材料的釋放而產生。可使用化學氧化物移除(COR)製程或其他氣相蝕刻製程執行具有足夠蝕刻選擇性的蝕刻製程。為了製造供NMOS及PMOS用之多通道材料設計的元件，可使用第三磊晶生長材料。如此材料可選擇為相對於所需NMOS及PMOS通道材料具有高選擇性。此第三材料亦可為磊晶生長材料(諸如Ge)、或SiGe的諸多成分、或甚至可為P摻雜或B摻雜的矽或本文提到的其他磊晶生長材料。
可執行蝕刻製程，其蝕刻鰭堆疊100中的一材料而不蝕刻鰭堆疊100中的其他材料。此蝕刻製程包含等向性蝕刻以在任何方向上均勻地蝕刻。舉例而言，等向性的氣相蝕刻。如此氣相蝕刻相對於在相對應鰭成分(諸如SiGe或摻雜的Si)中使用的其他磊晶生長晶體膜可具有100：1的蝕刻選擇性。鰭堆疊100 係具有交替之具有不同蝕刻抗性之材料層的鰭結構。如上所述，可執行氣相蝕刻、化學氧化物移除蝕刻、原子層蝕刻(ALE)或準ALE蝕刻。因此，由於通道的側壁曝露，所以蝕刻導致橫向蝕刻。此選擇性蝕刻可橫向地修整給定材料的一部分，該給定材料係可藉由所使用的特定蝕刻劑及製程條件(化學化合物、腔室壓力、溫度等)加以蝕刻。圖2B描繪在藉由等向性蝕刻的蝕刻後之示例鰭堆疊191的結果。
在第一蝕刻製程之後，若需要的話，可使用第二蝕刻製程以修整另一或互補性通道材料。修整互補性通道材料可基於元件設計及電路的布局以產生所需的電晶體延遲或滿足電晶體延遲容差。修整互補性通道材料可在給定的處理腔室中藉由改變蝕刻化學品及參數原位執行。所修整的材料量可基於電性要求或規格，以在通道材料之垂直堆疊的配置中平衡NMOS及PMOS區域。針對給定通道材料之蝕刻的量可藉由基於預期的電晶體延遲之計算而決定，該預期的電晶體延遲係基於針對中繼而被調諧之給定元件的局部面積或區域。
圖2C描繪鰭堆疊192的示例結果，其中犧牲性材料120已被移除。在一或二(或更多)通道材料的蝕刻之後，可接著移除犧牲性材料120以露出通道110、130。犧牲性材料120可在露出的部分中被移除，使得奈米線或奈米片在每一端部處受支撐。如此犧牲性材料120的移除亦可在相同的處理腔室(諸如使用氣相蝕刻的腔室/系統)內執行。值得注意的是，圖2C描繪相對於nMOS修整的pMOS通道，但本技術領域之人士可察知pMOS通道比nMOS通道寬，因為電洞遷移率低於電子遷移率。因此，取決於期望的結果，可相對於另一者選擇性地修整任一通道。
如圖2D所描繪，在主體鰭材料的移除之後，處理可繼續以形成環繞式閘極(GAA)通道，諸如藉由沉積高k介電質145、第一型通道功函數金屬150、第二型通道功函數金屬155、及閘極填充金屬160。高k介電質145可為例如 HfO。高k介電質145亦可包含SiO閘極氧化物。第一型通道功函數金屬150可為例如TiN。第二型通道功函數金屬155可為例如TiAlN或TiAlC。閘極填充金屬160可為例如鎢、鈷、或釕。SiO閘極氧化物可在第一型通道110和第二型通道130兩者周圍沉積，高k介電質145可在第一型通道110和第二型通道130兩者周圍沉積，第一型通道功函數金屬150可針對第一型通道110在高k介電質145周圍沉積，第二型通道功函數金屬155可針對第二型通道130在高k介電質145周圍沉積，第一型通道功函數金屬150可在第一型通道110周圍沉積，第二型通道功函數金屬155可在第二型通道130周圍沉積，且第一型通道功函數金屬150可在第一型通道110和第二型通道130兩者周圍沉積，且接著可沉積填充金屬160。
替換閘極可在鰭結構周圍圖案化，且低k間隔件可沿替換閘極的側壁及沿鰭結構沉積。低k間隔件材料可以使得低k間隔件僅與替換閘極的側壁一起保留並自鰭結構移除的方式蝕刻。犧牲性材料120可接著在具有低k間隔件側壁之完整替換閘極間的區域內移除。因此，物理性奈米線或奈米片及可作用為通道材料但稍後可在奈米線形成製程中被釋放的磊晶材料，僅存在於替換閘極之內並突出穿過低k間隔件。
在另一實施例中，鰭之內的填充材料亦可不為通道。如此填充材料可選擇性地凹陷至PMOS及NMOS通道材料兩者。可執行凹陷步驟，使得填充材料充分地凹陷至低k間隔件中。低k間隔件可接著在填充磊晶材料之凹部留下的孔洞周圍再次形成。結果是僅延伸穿過低k間隔件材料的NMOS和PMOS線或奈米片。源極/汲極(S/D)磊晶生長可接著在NMOS和PMOS線或片的端部處依序執行。在各S/D生長於CFET元件之給定高度上的情況下，可在增長並自元件中的更高奈米線或奈米片(亦即離基板中心更遠的奈米線或奈米片)生長S/D磊晶材料之前，使接點或電極圖案化及金屬化。
在已執行所有S/D磊晶生長並形成所有S/D之後，且在形成接點或電極圖案以連接各S/D高度並金屬化之後，可打開替換閘極且可移除替換閘極之內的多晶矽或非晶矽以露出替換閘極區域內仍被鰭襯墊保護的鰭。可移除鰭襯墊，且可相對於NMOS和PMOS通道材料選擇性地蝕刻非NMOS或PMOS通道之一部分的填充磊晶材料。相對應的蝕刻較佳是等向性的，以在填充磊晶材料與通道材料之間具有極高的選擇性。可完成如此CFET處理，其中高k材料沉積在閘極之內及NMOS和PMOS奈米線/奈米片周圍。高k介電沉積之後可接著NMOS和PMOS功函數及閘極金屬的後續沉積。
本文技術亦可包含垂直配置在垂直定向的NMOS Si上方之水平定向的PMOS SiGe，或其相反或部分。如圖3A所描繪，鰭堆疊200包含犧牲性材料220(舉例而言，諸如Si：B之摻雜的矽)、用於第一型通道210的第一材料(例如SiGe)、及用於第二型通道230的第二材料(例如Si)，其中犧牲性材料220是第三材料。與配置在上方的SiGe層相比，鰭堆疊200可包含較厚的矽層。
圖3B描繪鰭堆疊291，其中可執行第一蝕刻步驟，其橫向地修整第二型通道230(Si NMOS通道)，導致變窄之垂直定向的奈米片(奈米片的長軸垂直於基板的工作表面或在xy平面中延伸，但矩形橫截面的長邊在z平面中延伸)。可配置深寬比以防止伴隨橫向修整的奈米片之任何不穩定性。可計算蝕刻持續時間以在第二預定時間量的期間蝕刻，該第二預定時間量可產生用於垂直通道的預定深寬比。
圖3C描繪鰭堆疊292的示例結果，其中犧牲性材料220已被移除。在一或二(或更多)通道材料的蝕刻之後，可接著移除犧牲性材料220以露出通道210、230。犧牲性材料220可在露出的部分中被移除，使得奈米線或奈米片在每一端部處受支撐。如此犧牲性材料220的移除亦可在相同的處理腔室(諸如使用氣相蝕刻的腔室/系統)內執行。在一些應用中，如此定向可改善驅動電流。
如圖3D所描繪，在主體鰭材料的移除之後，處理可繼續以形成環繞式閘極(GAA)通道，諸如藉由沉積高k介電質245、第一型通道功函數金屬250、第二型通道功函數金屬255、及閘極填充金屬260。高k介電質245可為例如HfO。高k介電質245亦可包含SiO閘極氧化物。第一型通道功函數金屬250可為例如TiN。第二型通道功函數金屬255可為例如TiAlN或TiAlC。閘極填充金屬260可為例如鎢、鈷、或釕。SiO閘極氧化物可在第一型通道210和第二型通道230兩者周圍沉積，高k介電質245可在第一型通道210和第二型通道230兩者周圍沉積，第一型通道功函數金屬250可針對第一型通道210在高k介電質245周圍沉積，第二型通道功函數金屬255可針對第二型通道230在高k介電質245周圍沉積，第一型通道功函數金屬250可在第一型通道210周圍沉積，第二型通道功函數金屬255可在第二型通道230周圍沉積，且第一型通道功函數金屬250可在第一型通道210和第二型通道230兩者周圍沉積，且接著可沉積填充金屬260。
在另一實施例中，第一型通道210可相對於第二型通道230垂直地定向。與nMOS相比，在需要用於pMOS之大量奈米線或奈米片的情況下，此結構可為期望的，其中奈米線/奈米片的寬度可能受到限制。
在另一實施例中，圖3E描繪鰭堆疊294的示例結果，其中第一型通道210附接至鰭堆疊294的基部，形成非常高的通道結構。此可藉由第一型通道210材料達到預定高度的磊晶生長、後接犧牲性材料及第二型通道230材料的層之磊晶生長而達成。可沉積遮罩且可執行蝕刻以垂直地向下蝕刻至材料的層中。處理可如圖3D所述繼續進行，其中GAA通道在第二型通道230周圍形成。值得注意的是，此結構的益處在於第一型通道210可為可被借助用以控制應變的鰭結構。
圖4描繪在源極/汲極和接點金屬化後之基板區段400的立體橫截面圖。可看到第一型通道210、犧牲性材料220、及第二型通道230。
圖5描繪在移除犧牲性材料220及其他填充材料後及在閘極金屬化後之基板區段500的立體橫截面圖。值得注意的是，用於接點之金屬的選擇可沿通道引入額外的應變。諸如Ru的金屬可在諸如S/D退火的高熱過程經歷再結晶，其可沿通道施加額外的應變。
在先前的描述中已說明具體細節，諸如處理系統的特殊幾何結構及其中使用的諸多元件與製程的描述。然而應理解，本文技術可在背離這些具體細節的其他實施例中實行，且此等細節係以解釋而非限制為目的。本文揭示的實施例已參考隨附圖式描述。同樣地，為了解釋的目的，已說明特定的數字、材料、及配置以提供完整的理解。儘管如此，實施例可在無如此具體細節的情況下實施。具有實質上相同功能性結構的元件以類似的參考符號表示，且因此可省略任何冗餘的描述。
為了有助於理解諸多實施例，將諸多技術以多個分立操作描述。不應將所述之順序理解成暗示該等操作必定為順序相依。尤其，該等操作不需以敘述的順序執行。所述之操作可以不同於所述實施例的順序執行。在額外的實施例中，可執行諸多額外操作及/或可省略所述之操作。
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Claims (19)

  1. 一種製造半導體元件的方法，包含：提供其上具有基鰭結構的基板，該基鰭結構包含：用於形成第一環繞式閘極(GAA)電晶體之通道的第一堆疊部分，該第一堆疊部分包含第一通道材料，用於形成第二GAA電晶體之通道的第二堆疊部分，該第二堆疊部分包含第二通道材料，及犧牲性部分，其包含犧牲性材料，該犧牲性部分將該第一堆疊部分與該第二堆疊部分分開，使得該第一通道材料、該第二通道材料及該犧牲性材料在該基鰭結構的一側處曝露，其中該第一通道材料、該第二通道材料及該犧牲性材料彼此具有不同的化學成分；藉由將該基鰭結構的該側曝露於等向性蝕刻製程，以選擇性地蝕刻該第一通道材料以及該第二通道材料的其中一者，而沿著寬度方向移除該第一通道材料或該第二通道材料的一部分，經選擇性地蝕刻的通道材料具有比另一通道材料之寬度更窄的寬度，該第一通道材料的寬度係沿著平行於該基板之平面的維度而被量測；移除該犧牲性材料，以使該第一通道材料留在該第一堆疊部分中，並且使該第二通道材料留在該第二堆疊部分中；及分別在該第一通道材料及該第二通道材料周圍形成第一及第二GAA閘極結構。
  2. 如申請專利範圍第1項之製造半導體元件的方法，其中該第一通道材料是Si，該第二通道材料是SiGe，且該犧牲性材料是摻雜的Si。
  3. 如申請專利範圍第2項之製造半導體元件的方法，其中該第一通道材料提供NMOS通道，且該第二通道材料提供PMOS通道。
  4. 如申請專利範圍第1項之製造半導體元件的方法，其中該曝露步驟包含在寬度方向上相對於該第二通道材料及該犧牲性材料選擇性地蝕刻該第一通道材料，以形成垂直定向的第一通道部分。
  5. 如申請專利範圍第4項之製造半導體元件的方法，其中該第一堆疊部分係該第一通道材料的單層，且該第二堆疊部分係該第二通道材料的單層，該第一通道材料的層沿高度方向係比該第二通道材料的層厚。
  6. 如申請專利範圍第4項之製造半導體元件的方法，其中該第一堆疊部分係該第一通道材料的單層，而該第二堆疊部分包含在高度方向上由該犧牲性材料的層彼此分開之該第二通道材料的複數層，該第一通道材料的該單層沿高度方向係比該第二通道材料的任何層厚。
  7. 如申請專利範圍第1項之製造半導體元件的方法，其中該第一堆疊部分包含在高度方向上由該犧牲性材料的層彼此分開之該第一通道材料的複數層，而該第二堆疊部分包含在高度方向上由該犧牲性材料的層彼此分開之該第二通道材料的複數層。
  8. 如申請專利範圍第1項之製造半導體元件的方法，更包含沿該基鰭結構的長度切割該基鰭結構以形成複數單獨的鰭結構，各者具有使該第一通道材料、該第二通道材料及該犧牲性材料之端部曝露的切割端。
  9. 如申請專利範圍第8項之製造半導體元件的方法，更包含在透過該曝露步驟而藉由該犧牲性材料之選擇性蝕刻所形成的凹部中沉積閘極間隔件介電材料。
  10. 如申請專利範圍第1項之製造半導體元件的方法，其中該移除步驟包含相對於該第一通道材料及該第二通道材料選擇性地蝕刻掉所有該犧牲性材料，使得該第一及第二通道材料自該基鰭結構釋放。
  11. 如申請專利範圍第1項之製造半導體元件的方法，其中該形成閘極結構包含：形成圍繞該第一通道材料的第一閘極結構，及形成圍繞該第二通道材料的第二閘極結構。
  12. 如申請專利範圍第11項之製造半導體元件的方法，其中該形成第一閘極結構包含：在該第一通道材料周圍形成NMOS閘極結構，及在該第二通道材料周圍形成PMOS閘極結構。
  13. 如申請專利範圍第12項之製造半導體元件的方法，更包含將該NMOS閘極結構電性連接至該PMOS閘極結構而作為互補性的電晶體。
  14. 一種半導體元件，包含：基板，其具有平坦表面； 第一FET，其設置在該基板上並具有第一通道結構，該第一通道結構具有高度與寬度，該第一通道結構的該高度係沿著垂直於該基板之平面的維度而被量測，且該第一通道結構的該寬度係沿著平行於該基板之該平面的維度而被量測；第二FET，其沿垂直於該基板之該平面的該高度方向垂直地堆疊在該第一FET上，該第二FET具有第二通道結構，該第二通道結構具有高度與寬度，該第二通道結構的該高度係沿著垂直於該基板之該平面的該維度而被量測，且該第二通道結構的該寬度係沿著平行於該基板之該平面的該維度而被量測；第一閘極結構，其環繞該第一通道結構設置；及第二閘極結構，其環繞該第二通道結構設置，其中該第一通道結構的該寬度係窄於該第二通道結構的該寬度，且該第一通道結構的該高度係大於該第一通道結構的該寬度。
  15. 如申請專利範圍第14項之半導體元件，其中該第一通道結構係單一垂直定向的通道。
  16. 如申請專利範圍第14項之半導體元件，其中該第二通道結構包含複數堆疊之水平定向的通道。
  17. 如申請專利範圍第14項之半導體元件，其中該第一通道結構係nFET通道，且該第二通道結構係pFET通道。
  18. 如申請專利範圍第14項之半導體元件，其中該第一通道結構係pFET通道，且該第二通道結構係nFET通道。
  19. 如申請專利範圍第14項之半導體元件，其中該第一通道結構係由Si形成，且該第二通道結構係由SiGe形成。
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