CN111566802B - 半导体器件以及制造半导体器件的方法 - Google Patents

半导体器件以及制造半导体器件的方法 Download PDF

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CN111566802B
CN111566802B CN201880085524.1A CN201880085524A CN111566802B CN 111566802 B CN111566802 B CN 111566802B CN 201880085524 A CN201880085524 A CN 201880085524A CN 111566802 B CN111566802 B CN 111566802B
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channel
channel material
stack
gate
sacrificial
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CN111566802A (zh
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杰弗里·史密斯
苏巴迪普·卡尔
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Tokyo Electron Ltd
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Abstract

一种制造半导体器件的方法，包括：提供衬底，该衬底上具有基础鳍片结构，该基础鳍片结构包括：第一堆叠部，其用于形成第一环绕式栅极(GAA)晶体管的沟道，该第一堆叠部包括第一沟道材料；第二堆叠部，其用于形成第二GAA晶体管的沟道，该第二堆叠部包括第二沟道材料；以及牺牲部，其将第一堆叠部与第二堆叠部分开，其中，第一沟道材料、第二通道材料和牺牲材料具有彼此不同的化学组成；使基础鳍片结构的侧面露出以进行各向同性蚀刻处理，该各向同性蚀刻处理选择性地对第一沟道材料、第二沟道材料和牺牲材料中的一种进行蚀刻；以及分别在第一沟道材料和第二沟道材料周围形成第一GAA栅极结构和第二GAA栅极结构。

Description

半导体器件以及制造半导体器件的方法
相关申请的交叉引用
本公开内容要求于2017年12月4日提交的美国临时申请第62/594350号的权益，该美国临时申请的全部内容通过引用并入本文。
技术领域
本公开内容涉及制造诸如集成电路以及用于集成电路的晶体管和晶体管部件的半导体器件的方法。
背景技术
本文提供的背景描述是为了总体上呈现本公开内容的上下文。就本背景技术部分中描述的工作的程度而言，目前署名的发明人的工作以及在提交时可以不另外被限定作为现有技术的描述的方面既没有明确地也没有隐含地被承认为针对本公开内容的现有技术。
在半导体器件的制造期间，执行各种制造处理，例如成膜沉积处理、蚀刻掩模创建处理、图案化处理、光刻胶显影处理、材料蚀刻和去除处理以及掺杂处理。重复执行这些处理以在衬底上形成期望的半导体器件元件。历来，晶体管被利用微制造形成在一个平面中并且上面形成有布线/金属，并且因此该晶体管被表征为二维(2D)电路或2D制造。缩放工作极大地增加了2D电路中每单位面积的晶体管的数目，但是随着缩放进入单数位纳米半导体器件制造节点，缩放工作正面临更大的挑战。半导体器件制造商已经表达了对三维(3D)半导体器件的需求，在3D半导体器件中，器件、晶体管和标准单元堆叠在彼此之上作为继续缩放的手段。3D半导体器件的制造提出了与新的工艺集成、新颖的硬件和工艺能力、设计、后制造处理、电子设计自动化以及3D制造处理的其他方面相关联的许多新的且独特的挑战。
发明内容
在一个实施方式中，一种制造半导体器件的方法包括：提供衬底，该衬底上具有基础鳍片结构，该基础鳍片结构包括：第一堆叠部，其用于形成第一环绕式栅极(GAA)晶体管的沟道，该第一堆叠部包括第一沟道材料；第二堆叠部，其用于形成第二GAA晶体管的沟道，该第二堆叠部包括第二沟道材料；以及牺牲部，其将设置在第二牺牲材料的上部与下部之间的第一堆叠部与第二堆叠部分开，使得第一沟道材料、第二沟道材料和牺牲材料在基础鳍片结构的侧面处露出，其中，第一沟道材料、第二沟道材料和牺牲材料具有彼此不同的化学组成；使基础鳍片结构的侧面露出以进行各向同性蚀刻处理，该各向同性蚀刻处理相对于第一沟道材料、第二沟道材料和牺牲材料中其他两种选择性地对第一沟道材料、第二沟道材料和牺牲材料中的一种进行蚀刻；以及分别在第一沟道材料和第二沟道材料周围形成第一GAA栅极结构和第二GAA栅极结构。
注意，本发明内容部分没有指定本公开内容或要求保护的发明的每个实施方式和/或增加的新颖方面。相反，本发明内容仅提供了对不同实施方式和对应的新颖点的初步讨论。对于本发明和实施方式的附加细节和/或可能的观点，读者可以参考如下面进一步讨论的本公开内容的具体实施方式部分和对应的附图。
附图说明
将参照以下附图详细描述作为示例提出的本公开内容的各种实施方式，其中，相似的附图标记指代相似的元件，并且在附图中：
图1A示出了根据本公开内容的实施方式的纳米线/纳米片FET结构的轴测图；
图1B示出了根据本公开内容的实施方式的制造半导体器件的方法的处理流程图；
图2A示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中掩模材料保护一组沟道；
图2B示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中，顶部的一组沟道被选择性地蚀刻；
图2C示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中，牺牲材料被去除；
图2D示出了根据本公开内容的实施方式的具有两种不同的沟道材料的环绕式栅极晶体管器件；
图3A示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中，底部沟道被制造成比顶部的一组沟道厚；
图3B示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中，底部沟道被蚀刻以产生竖直沟道；
图3C示出了根据本公开内容的实施方式的具有两种不同的沟道材料的鳍片结构的截面图，其中，沟道被蚀刻以产生竖直沟道并且牺牲材料被去除；
图3D示出了根据本公开内容的实施方式的具有两组不同的沟道的环绕式栅极晶体管器件，其中，沟道之一是竖直沟道；
图3E示出了根据本公开内容的实施方式的具有两组不同的沟道的环绕式栅极晶体管器件，其中，沟道之一是竖直沟道；
图4示出了根据本公开内容的实施方式的在源极/漏极和接触部金属化之后的衬底区段的透视截面图；以及
图5示出了根据本公开内容的实施方式的在去除掺杂的硅(或其他间隔件/填充物)之后并且在栅极金属化之后的衬底区段的透视截面图。
具体实施方式
以下公开内容提供了用于实现所提供的主题的不同特征的许多不同的实施方式或示例。以下描述了部件和布置的特定示例以简化本公开内容。当然，这些仅是示例并且不旨在限制。例如，在随后的描述中，在第二特征上方或第二特征上的第一特征的形成可以包括其中第一特征和第二特征直接接触形成的实施方式，并且还可以包括其中可以在第一特征与第二特征之间形成附加特征的实施方式，使得第一特征和第二特征可以不直接接触。另外，本公开内容可以在各个示例中重复附图标记和/或字母。该重复是出于简单和清楚的目的，并且其本身不指示所讨论的各种实施方式和/或配置之间的关系。此外，为了便于描述，本文可以使用空间相对术语例如“下方”、“以下”、“下部”、“以上”、“上部”等来描述如图所示的一个元件或特征与另一元件或特征的关系。除了图中所描绘的方向之外，空间相对术语旨在涵盖器件在使用或操作中的不同方向。装置可以以其他方式定向(旋转90度或在其他方向处)，并且本文使用的空间相对描述符可以同样地被相应地解释。
出于清楚的目的，已经呈现了如本文描述的不同步骤的讨论顺序。通常，这些步骤可以以任何合适的顺序执行。另外，虽然本文的不同特征、技术、配置等中的每一个可以在本公开内容的不同地方论述，但是旨在可以彼此独立地或彼此组合地执行构思中的每一个。因此，本发明可以以许多不同的方式进行实施和观察。
注意，虽然本文的示例实施方式集中于硅和硅锗，但是这种集中是为了方便而不是限制性的。本文的技术也可以与任何外延生长材料或掺杂型外延生长材料一起使用。这包括Si、P掺杂硅、B掺杂硅、SiGe、掺杂SiGe、Ge以及任何其他掺杂或未掺杂的外延生长的沟道材料。本文的技术可以使用气相蚀刻工艺或化学氧化物去除(COR)工艺来选择性地实现充分的蚀刻以用于成功地进行材料凹陷处理和线/片释放处理。
由于功能缩放不断减小纳米线和/或纳米片的尺寸以实现面积缩放，因此给定器件的驱动电流面临重大挑战。对于鳍式场效应晶体管(FINFET)器件，可以通过选择不同的源极和漏极(S/D)或者甚至沟道材料来将应变(strain)分别施加至pMOS器件和nMOS器件，以提高电子迁移率。对于纳米线/纳米片工艺，通过将不同的材料并入n型金属氧化物半导体(NMOS)沟道和p型金属氧化物半导体(PMOS)沟道中以对线和/或纳米片提供应变，可以提高驱动电流并且可以提高对场效应晶体管器件的控制。当试图制造不同的材料的两个器件时，因为它们在彼此上横向堆叠，因此会出现器件上器件堆叠或者晶体管上晶体管堆叠的挑战，而对于FINFET器件和标准纳米线/纳米片器件，存在可以允许在nMOS沟道与pMOS沟道之间进行独特处理的p/n分隔。对于互补FET(CFET)器件，nMOS器件和pMOS器件直接在彼此上堆叠。此外，对于特定设计，改变不同沟道材料的厚度可以致使不同的电气性能。
对于FET器件，NMOS沟道可以由诸如单晶硅的材料形成，而PMOS沟道可以由诸如SiGe的材料形成。利用其中nMOS沟道和pMOS沟道是由分开了p/n分隔距离的独特FIN结构形成的纳米线和纳米片器件制造的某些方法，NMOS和PMOS相对于对线和释放材料的材料选择可以是二元的，即使所述线和释放材料在NMOS(Si线相对于SiGe释放)与PMOS(SiGe线相对于Si释放)之间是相反的也是如此。在使用外延沉积进行的Si/SiGe堆叠堆积期间，可以在外延沉积序列期间对NMOS目标区域或PMOS目标区域进行蚀刻以提供高度不匹配，以产生针对给定高度的Si或SiGe纳米线或纳米片。在其中沟道从起始FIN结构中的互补材料释放的纳米线/纳米片线释放过程期间，可以在在pMOS FIN上进行纳米线释放过程时阻挡nMOS起始FIN结构，以及可以在nMOS FIN上进行纳米线释放过程时阻挡pMOS起始FIN结构。
在纳米线处理期间，可以将NMOS部分与PMOS部分区别处理。例如，对于NMOS处理，可以将SiGe凹陷至低k栅极间隔件中，以使剩余的硅线或纳米片穿过低k栅极间隔件突出。相反地，对于PMOS处理，可以将硅选择性地凹陷至低k栅极间隔件中，以使SiGe线穿过低k栅极间隔件突出。在替代栅极中的线释放过程期间，NMOS栅极可以使SiGe去除而留下Si线或纳米片。在PMOS栅极中，硅可以被去除以产生期望的SiGe线。
本文的技术对于FET器件而言有效可行，这是因为NMOS和PMOS通常彼此分开，即使两个晶体管都在公共的物理栅极结构内也是如此。对于单独的nMOS物理栅极和pMOS物理栅极的情况，可以通过置于两个物理栅极之间的介电切口的并入容易地将pMOS晶体管与nMOS晶体管物理上隔离。对于nMOS晶体管和pMOS晶体管在同一物理栅极或“公共”栅极内的应用，nMOS晶体管与pMOS晶体管之间的p/n分隔通常可以足够宽足以使得能够对单个nMOS晶体管和pMOS晶体管进行独特的处理。
当NMOS沟道和PMOS沟道以相对于彼此具有不同的横向定向或竖直定向的线或片的形式存在时，对于FET设计，处理也可以是直接的，这是因为NMOS和PMOS将存在于分开的有源区内并且因此如果nFET有源区与pFET有源区之间存在足够的p/n分隔距离，则NMOS和PMOS可以彼此单独处理。
本文的技术帮助实现制造包括逻辑器件的三维半导体器件。在一个实施方式中，一种方法在互补场效应晶体管器件(CFET)中提供了多沟道材料，其中，PMOS或NMOS纳米线和/或纳米片堆叠在其互补对应物上。半导体器件通常在具有器件形成在其上的工作表面的衬底上制造，该衬底例如是单晶硅晶片。通过彼此“交叠”，在垂直于衬底的工作表面的平面中形成PMOS和NMOS纳米线或纳米片。在一个实施方式中，本文的方法提供了包括不同的外延生长的晶体材料的NMOS沟道和PMOS沟道的不同的竖直朝向或横向定向。
本文的技术适用于使用纳米线或纳米片的随机逻辑和非随机逻辑的器件制造。本文存在若干个实施方式、替代方案和优点。实施方式可以包括外延生长的晶体材料的三阶基质或甚至更高阶基质，所述外延生长的晶体材料在其中PMOS沟道和NMOS沟道存在于彼此之上的CFET器件内用作多沟道材料。本文的蚀刻方法提供所需的选择性，用于以各向同性的方式利用充分的蚀刻选择性将对NMOS沟道材料或PMOS沟道材料具有选择性的外延生长材料凹陷至低k介电栅极间隔件中，使得可以顺序地或同时地形成堆叠的线或片。本文的蚀刻方法包括其中在替代栅极内执行PMOS或NMOS线/片释放的蚀刻，其中，填充外延材料以非常高的选择性被各向同性地蚀刻以保留NMOS沟道材料和PMOS沟道材料。
可以执行一种沉积方法，在该沉积方法中，竖直堆叠的线或片可以通过厚的外延生长来形成并且存在于材料基质中，使得该材料基质在其本身的底部和顶部由外延生长的选择性基质中的另一材料作为边界。所述技术包括其中可以将上述厚的外延生长的膜相对于上侧和下侧的材料进行“修整”的方法。可以执行修整使得产生薄的片或线。这样的纳米片可以具有沿水平(xy平面)方向延伸的纵轴和纳米片的矩形截面。对于矩形截面，当矩形的较长侧在xy平面中延伸而较短侧在z平面中延伸时，这是水平定向。当矩形的较长侧在z平面中延伸而较短侧在xy平面中延伸时，这是竖直定向。各种定向或旋转的纳米片可以以各种布置竖直定位在彼此上方。
图1A示出了可以向其提供本公开内容的技术的示例结构。如所看到的，结构300包括衬底301，该衬底301上具有基础鳍片结构303。每个基础鳍片结构303包括沿高度方向h堆叠在基础鳍片303内的第一沟道材料305、牺牲材料307和第二沟道材料306的交替层。基础鳍片结构303沿衬底301的宽度方向w以及沿长度方向l横向间隔开。每个基础鳍片结构303可以用于形成一个或更多个第一环绕式栅极(GAA)晶体管。在图1A的示例结构中，基础鳍片结构303均包括：第一堆叠鳍片部310，用于形成第一GAA晶体管的沟道区；以及第二堆叠鳍片部320，用于形成第二GAA晶体管的沟道区。第一堆叠鳍片部310和第二堆叠鳍片部320各自包括设置在牺牲材料307的下部与上部之间的初始体积的沟道材料305、306。牺牲材料307可以将第一堆叠鳍片部310与第二堆叠鳍片部320分开。第一沟道材料305、第二沟道材料306和牺牲材料307可以在基础鳍片结构303的侧面处露出并且具有彼此不同的化学组成。虽然第一堆叠鳍片部310和第二堆叠鳍片部320均被示出为包括两层沟道材料305、306，但是可以仅使用单层。第一堆叠鳍片部310可以用于例如提供NMOS器件，而第二堆叠鳍片部320可以用于形成PMOS器件，如下面进一步讨论的。
图1B示出了用于制造半导体器件的方法的处理流程图。如所看到的，该处理包括提供在其上具有基础鳍片结构303的半导体衬底的步骤351，该基础鳍片结构303包括具有至少一个第一沟道材料305的第一堆叠鳍片部310、具有至少一个第二沟道材料306的第二堆叠鳍片部320以及牺牲材料307。第一堆叠鳍片部310用于形成第一环绕式栅极(GAA)晶体管的沟道，并且第二堆叠鳍片部320用于形成第二GAA晶体管的沟道。第一堆叠鳍片部310包括设置在牺牲材料307的上部与下部之间的初始体积的第一沟道材料305，使得第一沟道材料305和牺牲材料307在第一堆叠鳍片结构310的侧面处露出。第二堆叠鳍片部320包括设置在牺牲材料307的上部与下部之间的初始体积的第二沟道材料306，使得第二沟道材料306和牺牲材料307在第二堆叠鳍片结构320的侧面处露出。
在步骤353中，通过例如各向同性蚀刻将第二沟道材料306的初始体积相对于第一沟道材料305的初始体积选择性地减小预定量。这种减小可以通过蚀刻“修整”初始体积的第二沟道材料306的一部分来执行。预定量的体积减小可以在第一堆叠鳍片部310中产生例如竖直定向的第一沟道。
在步骤355中，分别在第一沟道材料305和第二沟道材料306周围形成第一GAA栅极结构和第二GAA栅极结构。更具体地，去除牺牲材料307以“释放”第一沟道材料305和第二沟道材料306。然后，在所释放的沟道材料的每一个周围形成GAA晶体管结构。第一GAA结构和第二GAA结构可以电连接，使得它们彼此互补。
在一个实施方式中，第一材料、第二材料和第三材料对于特定蚀刻剂可以具有不同的抗蚀刻性。如图2A所示，蚀刻之前的鳍片堆叠100包括：牺牲材料120，例如Si:B或掺杂的硅；用于第一类型的沟道110的第一材料，例如SiGe；以及用于第二类型的沟道130的第二材料，例如Si，其中，牺牲材料120为第三材料。第一类型的沟道110可以设置在第二类型的沟道130上方，其中，牺牲材料120将两个沟道分开。可以存在每种类型的沟道的多个沟道。更具体地，不同的沟道材料可以用于NMOS纳米线或纳米片和PMOS纳米线或纳米片两者。注意，这是非限制性的并且可以选择更多的材料和组合。利用具有不同抗蚀刻性的材料，不需要覆盖或阻挡一个有源沟道类型区域，这是因为抗蚀刻性本身将保护互补材料和体材料不被蚀刻(不被显著蚀刻)。
硅或SiGe线或片可以借助于通过高选择性各向同性蚀刻工艺释放互补材料来产生。可以使用化学氧化物去除(COR)工艺或其他气相蚀刻工艺来执行具有足够的蚀刻选择性的蚀刻工艺。为了制造设计有用于NMOS和PMOS的多种沟道材料的器件，可以使用第三外延生长材料。可以选择这样的材料以对期望的NMOS沟道材料和PMOS沟道材料具有高选择性。该第三材料也可以是外延生长材料，例如Ge或者SiGe的各种组成，或者甚至可以是P掺杂型或B掺杂型的硅或者本文提到的其他外延生长材料。
可以执行蚀刻鳍片堆叠100中的一种材料而不蚀刻该鳍片堆叠100中的其他材料的蚀刻工艺。该蚀刻工艺包括各向同性蚀刻，以在任何方向上均匀蚀刻。例如，各向同性、气相蚀刻。这种气相蚀刻相对于在对应的鳍片组合物中使用的其他外延生长晶体膜例如SiGe或掺杂的Si可以具有100：1的蚀刻选择性。鳍片堆叠100是具有材料的交替层的鳍片结构，所述材料具有不同的抗蚀刻性。如上所述，可以执行气相蚀刻、化学氧化物去除蚀刻、原子层蚀刻(ALE)或准ALE蚀刻。因此，蚀刻由于沟道的侧壁被暴露而导致横向蚀刻。这种选择性蚀刻可以横向修整给定材料中可以通过特定蚀刻剂或使用的工艺条件(化学化合物、室压力、温度等)蚀刻的一部分。图2B示出了通过各向同性蚀刻进行蚀刻之后的示例鳍片堆叠191的结果。
在第一蚀刻工艺之后，如果需要，可以使用第二蚀刻工艺来修整另一沟道材料或互补沟道材料。修整互补沟道材料可以基于器件设计和电路布局，以产生期望的晶体管延迟或者满足晶体管延迟容限。修整互补沟道材料可以通过更改蚀刻化学品和蚀刻参数在给定的处理室中原位执行。材料经修整的量可以基于电气要求或规格，以在沟道材料的竖直堆叠配置中平衡NMOS区域和PMOS区域。可以基于给定器件中被调节用于继电器的局部面积或局部区域通过基于预期的晶体管延迟的计算来确定针对给定沟道材料的蚀刻的量。
图2C示出了鳍片堆叠192的示例结果，其中牺牲材料120被去除。在对一种或两种(或更多种)沟道材料的蚀刻之后，然后可以去除牺牲材料120以使沟道110、130露出。可以在未被露出的部分中去除牺牲材料120，使得纳米线或纳米片被支撑在每端处。这种牺牲材料120的去除也可以在同一处理室例如使用气相蚀刻的室/系统中执行。值得注意的是，图2C示出了相对于nMOS修整的pMOS沟道，但是本领域技术人员可以理解的是，由于空穴迁移率低于电子迁移率，因此pMOS沟道比nMOS沟道宽。因此，取决于期望的结果，任一沟道可以相对于另一沟道被选择性地修整。
如图2D所示，在去除体鳍片材料之后，处理可以继续以例如通过沉积高k电介质145、第一类型的沟道功函数金属150、第二类型的沟道功函数金属155以及栅极填充金属160来形成环绕式栅极(GAA)沟道。该高k电介质145可以是例如HfO。高k电介质145也可以包括SiO栅极氧化物。第一类型的沟道功函数金属150可以是例如TiN。第二类型的沟道功函数金属155可以是例如TiAlN或TiAlC。栅极填充金属160可以是例如钨、钴或钌。SiO栅极氧化物可以沉积在第一类型的沟道110和第二类型的沟道130两者周围，高k电介质145可以沉积在第一类型的沟道110和第二类型的沟道130两者周围，第一类型的沟道功函数金属150可以沉积在针对第一类型的沟道110的高k电介质145周围，第二类型的沟道功函数金属155可以沉积在针对第二类型的沟道130的高k电介质145周围，第一类型的沟道功函数金属150可以沉积在第一类型的沟道110周围，第二类型的沟道功函数金属155可以沉积在第二类型的沟道130周围，以及第一类型的沟道功函数金属150可以沉积在第一类型的沟道110和第二类型的沟道130两者周围，并且然后，填充金属160可以被沉积。
可以在鳍片结构周围对替代栅极进行图案化，并且可以沿该替代栅极的侧壁以及沿该鳍片结构对低k间隔件进行沉积。该低k间隔件材料可以以下述方式蚀刻：使得低k间隔件仅沿替代栅极的侧壁被保留并且从鳍片结构中去除。然后，可以在具有低k间隔件侧壁的完全替代栅极之间的区域中去除牺牲材料120。因此，物理纳米线或物理纳米片与可以用作沟道材料但是随后可以在纳米线形成过程中释放的外延材料一起仅存在于替代栅极内并且突出穿过低k间隔件。
在另一实施方式中，鳍片内的填充材料也可以不是沟道。这样的填充材料可以选择性地凹陷至PMOS沟道材料和NMOS沟道材料。该凹陷可以被执行成使得填充材料被充分凹陷至低k间隔件中。然后，可以在由填充外延材料的凹陷留下的腔周围重新形成低k间隔件。结果是仅延伸通过低k间隔件材料的NMOS和PMOS线或纳米片。然后，可以顺序地在NMOS线或纳米片的端部和PMOS线或纳米片的端部执行源极/漏极(S/D)外延生长。在每个S/D生长在CFET器件的给定水平上的情况下，在从器件中的更高水平的纳米线或纳米片——即，更远离衬底的中心的纳米线或纳米片——增加或生长S/D外延材料之前，可以对接触部或电极进行图案化和金属化。
在执行所有S/D外延生长并且形成所有S/D之后，并且在形成接触部或电极图案以连接每个S/D水平并且对该接触部或电极图案进行金属化之后，可以对替代栅极进行开口并且可以去除替代栅极内的多晶硅或非晶硅，以使仍由鳍片衬里保护在替代栅极区域中的鳍片露出。可以去除鳍片衬里，并且可以将不是NMOS沟道或PMOS沟道的一部分的填充外延材料选择性地蚀刻至NMOS沟道材料和PMOS沟道材料。对应的蚀刻优选地是各向同性的，以在填充外延材料与沟道材料之间具有极高的选择性。可以完成这样的CFET处理，在该CFET处理中，高k材料沉积在栅极内和NMOS和PMOS纳米线/纳米片周围。在高k介电沉积之后可以是NMOS和PMOS功函数和栅极金属的后续沉积。
本文的技术还可以包括竖直定位在竖直定向NMOS Si上方的水平定向PMOS SiGe，或者竖直定位在水平定向PMOS SiGe上方的竖直定向NMOS Si或者部分竖直定位在竖直定向NMOS Si上方的水平定向PMOS SiGe。如图3A所示，鳍片堆叠200包括：牺牲材料220，例如掺杂的硅例如Si:B；用于第一类型的沟道210的第一材料，例如SiGe；以及用于第二类型的沟道230的第二材料，例如Si，其中，牺牲材料220为第三材料。鳍片堆叠200可以包括与定位在上方的SiGe层相比更厚的硅层。
图3B示出了鳍片堆叠291，其中可以执行横向地修整第二类型的沟道230(Si NMOS沟道)的第一蚀刻步骤，从而致使窄的竖直定向的纳米片(纳米片的长轴垂直于衬底的工作面或在xy平面中延伸，但是矩形截面的长侧在z平面中延伸)。纵横比可以被配置成防止横向修整的纳米片产生任何不稳定性。蚀刻持续时间可以被计算成蚀刻持续可以产生针对竖直沟道的预定纵横比的第二预定时间量。
图3C示出了鳍片堆叠292的示例结果，其中牺牲材料220被去除。在对一种或两种(或更多种)沟道材料的蚀刻之后，然后可以去除牺牲材料220以使沟道210、230露出。可以在未被露出的部分中去除牺牲材料220，使得纳米线或纳米片被支撑在每端处。这种牺牲材料220的去除也可以在同一处理室例如使用气相蚀刻的室/系统中执行。在某些应用中，这种定向可以提高驱动电流。
如图3D所示，在去除体鳍片材料之后，处理可以继续以例如通过沉积高k电介质245、第一类型的沟道功函数金属250、第二类型的沟道功函数金属255以及栅极填充金属260来形成环绕式栅极(GAA)沟道。高k电介质245可以是例如HfO。高k电介质245也可以包括SiO栅极氧化物。第一类型的沟道功函数金属250可以是例如TiN。第二类型的沟道功函数金属255可以是例如TiAlN或TiAlC。栅极填充金属260可以是例如钨、钴或钌。SiO栅极氧化物可以沉积在第一类型的沟道210和第二类型的沟道230两者周围，高k电介质245可以沉积在第一类型的沟道210和第二类型的沟道230两者周围，第一类型的沟道功函数金属250可以沉积在针对第一类型的沟道210的高k电介质245周围，第二类型的沟道功函数金属255可以沉积在针对第二类型的沟道230的高k电介质245周围，第一类型的沟道功函数金属250可以沉积在第一类型的沟道210周围，第二类型的沟道功函数金属255可以沉积在第二类型的沟道230周围，以及第一类型的沟道功函数金属250可以沉积在第一类型的沟道210和第二类型的沟道230两者周围，并且然后，填充金属260可以被沉积。
在另一实施方式中，第一类型的沟道210可以相对于第二类型的沟道230竖直定向。与nMOS相比，在期望用于pMOS的大量纳米线或纳米片的情况下这样的结构可能是期望的，其中纳米线/纳米片的宽度可能受到限制。
在另一实施方式中，图3E示出了鳍片堆叠294的示例结果，其中第一类型的沟道210附接至鳍片堆叠294的基底，从而形成非常高的沟道结构。这可以是通过第一类型的沟道210材料至预定高度的外延生长、随后是牺牲材料和第二类型的沟道材料230的层的外延生长来实现的。可以沉积掩模并且可以执行蚀刻以竖直向下蚀刻至材料层中。处理可以如图3D所述进行，其中GAA沟道形成在第二类型的沟道230周围。值得注意的是，这种结构的益处是第一类型的沟道210可以是可以被利用以控制应变的鳍片结构。
图4示出了在源极/漏极和接触部金属化之后的衬底区段400的透视截面图。可以看到第一类型的沟道210、牺牲材料220和第二类型的沟道230。
图5示出了在去除牺牲材料220和其他填充材料之后并且在栅极金属化之后的衬底区段500的透视截面图。值得注意的是，对用于接触部的金属的选择可以沿沟道引入附加应变。诸如Ru的金属可以在诸如S/D退火的高温处理时经历重结晶，这可能会造成沿沟道的附加应变。
在前面的描述中，已经阐述了具体细节，例如处理系统的特定几何形状以及对其中使用的各种部件和处理的描述。然而，应当理解，本文的技术可以在脱离这些具体细节的其他实施方式中实践，并且这样的细节是为了说明而不是限制的目的。已经参照附图描述了本文公开的实施方式。类似地，出于说明的目的，已经阐述了具体的数字、材料和配置，以提供透彻的理解。然而，可以在没有这样的具体细节的情况下实践实施方式。具有大致相同的功能构造的部件由相似的附图标记表示，因此可以省略任何多余的描述。
已经将各种技术描述为多个离散操作，以帮助理解各种实施方式。描述的顺序不应被解释为意味着这些操作必须依赖于该顺序。实际上，这些操作不需要按照呈现的顺序执行。可以以与所描述的实施方式不同的顺序来执行所描述的操作。在附加实施方式中，可以执行各种附加操作和/或可以省略所描述的操作。

Claims (17)

1.一种制造半导体器件的方法，包括：
提供衬底，所述衬底上具有基础鳍片结构，所述基础鳍片结构包括：
第一堆叠部，其用于形成第一环绕式栅极(GAA)晶体管的沟道，所述第一堆叠部包括第一沟道材料，
第二堆叠部，其用于形成第二GAA晶体管的沟道，所述第二堆叠部包括第二沟道材料，以及
牺牲部，其包括牺牲材料，所述牺牲部沿垂直于所述衬底的平面的高度方向竖直地将所述第一堆叠部与所述第二堆叠部分开，使得所述第一沟道材料、所述第二沟道材料和所述牺牲材料在所述基础鳍片结构的侧面处露出，其中，所述第一沟道材料、所述第二沟道材料和所述牺牲材料具有彼此不同的化学组成；
使所述基础鳍片结构的侧面露出以进行各向同性蚀刻处理，所述各向同性蚀刻处理选择性地对所述第一沟道材料和所述第二沟道材料中的一种进行蚀刻，其中，所述蚀刻包括沿宽度方向相对于所述第二沟道材料和所述牺牲材料选择性地对所述第一沟道材料进行蚀刻以形成竖直定向的第一沟道部；
去除所述牺牲材料，使得所述第一沟道材料保留在所述第一堆叠部中并且所述第二沟道材料保留在所述第二堆叠部中；以及
分别在所述第一沟道材料和所述第二沟道材料周围形成第一GAA栅极结构和第二GAA栅极结构。
2.根据权利要求1所述的方法，其中，所述第一沟道材料为Si，所述第二沟道材料为SiGe，以及所述牺牲材料为掺杂的Si。
3.根据权利要求2所述的方法，其中，所述第一沟道材料提供NMOS沟道，以及所述第二沟道材料提供PMOS沟道。
4.根据权利要求1所述的方法，其中，所述第一沟道部是所述第一沟道材料的单层，以及第二沟道部是所述第二沟道材料的单层，第一沟道材料的层沿所述高度方向比第二沟道材料的层厚。
5.根据权利要求1所述的方法，其中，所述第一沟道部是所述第一沟道材料的单层，以及所述第二沟道部包括所述第二沟道材料的多个层，所述第二沟道材料的多个层由所述牺牲材料的层沿所述高度方向将彼此分开，所述第一沟道材料的单层沿所述高度方向比所述第二沟道材料的任意层厚。
6.根据权利要求1所述的方法，其中，所述第一堆叠部包括所述第一沟道材料的多个层，所述第一沟道材料的多个层由所述牺牲材料的层沿所述高度方向将彼此分开，以及所述第二堆叠部包括所述第二沟道材料的多个层，所述第二沟道材料的多个层由所述牺牲材料的层沿所述高度方向将彼此分开。
7.根据权利要求1所述的方法，还包括沿所述鳍片结构的长度对所述鳍片结构进行切割以形成多个分开的鳍片结构，每个鳍片结构具有使所述第一沟道材料、所述第二沟道材料和所述牺牲材料的端部露出的切割端部。
8.根据权利要求7所述的方法，还包括在凹部中沉积栅极间隔件介电材料。
9.根据权利要求1所述的方法，其中，所述去除包括相对于所述第一沟道材料和所述第二沟道材料选择性地蚀刻掉所有牺牲材料，使得所述第一沟道材料和所述第二沟道材料从所述鳍片结构释放。
10.根据权利要求1所述的方法，其中，所述形成栅极结构包括：
围绕所述第一沟道部形成第一栅极结构，以及
围绕所述第二沟道部形成第二栅极结构。
11.根据权利要求10所述的方法，其中，所述形成第一栅极结构包括：
在所述第一沟道部周围形成NMOS栅极结构，以及
在所述第二沟道部周围形成PMOS栅极结构。
12.根据权利要求11所述的方法，还包括将所述NMOS栅极结构电连接至所述PMOS栅极结构作为互补晶体管。
13.一种半导体器件，包括：
衬底，其具有平面表面；
第一FET，其设置在所述衬底上并且具有第一沟道结构，所述第一沟道结构具有高度和宽度，所述第一沟道结构的高度沿垂直于所述衬底的平面的维度测量，以及所述第一沟道结构的宽度沿平行于所述衬底的平面的维度测量；
第二FET，其沿垂直于所述衬底的平面的高度方向竖直地堆叠在所述第一FET上，所述第二FET具有第二沟道结构，所述第二沟道结构具有高度和宽度，所述第二沟道结构的高度沿垂直于所述衬底的平面的维度测量，以及所述第二沟道结构的宽度沿平行于所述衬底的平面的维度测量；
第一栅极结构，其完全设置在所述第一沟道结构周围；以及
第二栅极结构，其完全设置在所述第二沟道结构周围，其中，
所述第一沟道结构的宽度窄于所述第二沟道结构的宽度，
所述第一沟道结构的高度大于所述第一沟道结构的宽度，以及
所述第一沟道结构为单竖直定向沟道。
14.根据权利要求13所述的半导体器件，其中，所述第二沟道结构包括多个堆叠的水平定向沟道。
15.根据权利要求13所述的半导体器件，其中，所述第一沟道为nFET沟道以及所述第二沟道为pFET沟道。
16.根据权利要求13所述的半导体器件，其中，所述第一沟道为pFET沟道以及所述第二沟道为nFET沟道。
17.根据权利要求13所述的半导体器件，其中，所述第一沟道结构由Si形成以及所述第二沟道结构由SiGe形成。
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