CN104798204A - 具有富锗有源层与掺杂的过渡层的半导体器件 - Google Patents

具有富锗有源层与掺杂的过渡层的半导体器件 Download PDF

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CN104798204A
CN104798204A CN201380059464.3A CN201380059464A CN104798204A CN 104798204 A CN104798204 A CN 104798204A CN 201380059464 A CN201380059464 A CN 201380059464A CN 104798204 A CN104798204 A CN 104798204A
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layer
sige
transition zone
doping
semiconductor device
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CN104798204B (zh
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W·拉赫马迪
V·H·勒
R·皮拉里塞泰
J·S·卡治安
M·C·弗伦奇
A·A·布德雷维赫
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Intel Corp
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Intel Corp
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Abstract

本发明描述了由富Ge器件层制成的半导体器件堆叠体和器件。富Ge器件层设置在衬底上方，并且p型掺杂的Ge蚀刻抑制层(例如，p型SiGe)设置于其间，以在比器件层更富含Si的牺牲半导体层的去除期间抑制富Ge器件层的蚀刻。Ge在诸如氢氧化物水溶液化学物质的湿法蚀刻剂中的溶解速率可能随着掩埋p型掺杂半导体层被引入到半导体膜堆叠体中而显著减小，从而改进了蚀刻剂对富Ge器件层的选择性。

Description

具有富锗有源层与掺杂的过渡层的半导体器件
技术领域
本发明的实施例涉及半导体器件领域，并且具体而言，涉及具有锗(Ge)有源层的半导体器件。
背景技术
过去几十年中，集成电路中的特征的缩放已经实现了半导体芯片上的功能单元密度的增大。例如，缩小晶体管尺寸允许在芯片上包含更大数量的存储器器件，从而制备出具有增大的容量的产品。
在集成电路器件的场效应晶体管(FET)的制造中，除了硅以外的半导体晶体材料会是有利的。一个这种材料的示例是Ge，其相对于硅提供了许多可能的有利特征，例如但不限于高电荷载流子(空穴)迁移率、带隙偏移、不同晶格常数以及与硅构成合金以形成SiGe的半导体二元合金的能力。
在现代晶体管设计中使用Ge的一个问题是现今针对这些年大幅缩放的硅FET所获得的极精细特征(例如，22nm及以下)现在难以在Ge中获得，常常使得可能的基于材料的性能在以未大幅缩放的形式被实施时被冲抵。缩放的困难与Ge的材料性质有关，并且更具体地是蚀刻SiGe中的困难，SiGe常常被用作Ge有源层(例如，晶体管沟道层)与下层硅衬底材料之间的中间层，并且相对于Ge具有足够的选择性，以便在不侵蚀精细印刷的Ge有源层特征的情况下去除SiGe。
因此实现高SiGe:Ge选择性蚀刻的材料堆叠体架构和蚀刻技术是有利的。
附图说明
图1A示出了根据本发明的实施例的包括设置在δ掺杂的p型过渡层之上的锗器件层的半导体层堆叠体的截面图；
图1B示出了根据本发明的实施例的包括δ掺杂的p型过渡层的半导体层堆叠体的掺杂剂浓度沿深度分布的曲线图；
图2A和2B示出了根据本发明的实施例的图2A中所描绘的半导体层堆叠体的局部生长的截面图；
图3A和3B示出了根据本发明的另一个实施例的采用图1A的半导体堆叠体的平面半导体器件的制备中的截面图；
图4A-4C示出了根据本发明的实施例的表示制备采用图1A的半导体堆叠体的非平面半导体器件的方法中的各种操作的角视图；
图5A示出了根据本发明的实施例的采用图1A的半导体堆叠体的纳米线或纳米带半导体器件的等距截面图；
图5B示出了根据本发明的实施例的图5A的基于纳米线的半导体结构的截面沟道视图；
图5C示出了根据本发明的实施例的图5A的基于纳米线的半导体结构的截面图；
图6A-6D示出了根据本发明的实施例的表示制备纳米线半导体器件的方法中的各种操作的等距截面图，所述纳米线半导体器件在工艺中的至少一点处具有设置在p掺杂的过渡层之上的锗器件层；以及
图7示出了根据本发明的一种实施方式的计算设备。
具体实施方式
描述了具有设置在掺杂半导体过渡层之上的富Ge有源层的半导体器件。在以下描述中，阐述了许多细节，然而，对于本领域技术人员而言显而易见的是，在没有这些具体细节的情况下也可以实践本发明。在一些实例中，公知的方法和设备以框图的形式而不是以细节的形式示出，以避免使本发明难以理解。在整个说明书中，对“实施例”的引用表示结合实施例所描述的特定特征、结构、功能或特性包括在本发明的至少一个实施例中。因此，在整个说明书中的各处出现的短语“在实施例中”不一定指代本发明的同一个实施例。此外，特定特征、结构、功能或特性可以采用任何适合的方式组合在一个或多个实施例中。例如，第一实施例可以与第二实施例组合，只要未指定这两个实施例是互斥的。
术语“耦合”和“连接”及其衍生词在本文中可以用于描述部件之间的结构关系。应该理解，这些术语并不是要作为彼此的同义词。相反，在特定实施例中，“连接”可以用于指示两个或更多元件彼此直接物理接触或电接触。“耦合”可以用于指示两个或更多元件彼此直接或间接地(其间具有其它中间元件)物理接触或电接触，和/或指示两个或更多元件彼此配合或相互作用(例如，如在因果关系中)。
如本文中使用的术语“在…之上”、“在…之下”、“在....之间”和“在…上”指代一个材料层或部件相对于其它层或部件的相对位置。例如，设置在一个层之上(上方)或之下(下方)的另一个层可以与该层直接接触，或可以具有一个或多个中间层。此外，设置在两个层之间的一个层可以与这两个层直接接触，或可以具有一个或多个中间层。相比之下，第二层“上”的第一层与该第二层直接接触。相似地，除非另外明确规定，否则设置在两个相邻特征之间的一个特征可以与相邻特征直接接触，或可以具有一个或多个中间特征。
本文中描述的一个或多个实施例采用硅上锗(Ge上Si)衬底器件架构，其进一步采用设置在富Ge器件层与Si衬底之间的过渡层，该过渡层被掺杂以提高富Ge器件层对被用来去除器件堆叠体的由比器件层中的Ge少的Ge组成的其它半导体层的蚀刻剂的阻力。
在实施例中，p型掺杂的半导体过渡层设置在富Ge器件层与Si衬底之间。这种布置可以以基于锗的晶体管的形式用作平面器件、基于鳍状物或三栅极的器件、以及环绕栅极器件(例如，纳米线器件)。更具体地，一个或多个实施例针对执行从Ge/SiGe、Ge/Si、SiGe/SiGe或SiGe/Si多层堆叠体中释放矩形含Ge纳米线或纳米带。
本文中描述的一个或多个实施例利用p型δ掺杂的掩埋半导体层来增强上覆富Ge器件层对用于从半导体器件堆叠体中去除诸如具有相对较低Ge含量的一个或多个SiGe(或纯Si)层(即，比器件层更富含Si)之类的其它材料的特定湿法蚀刻剂的阻力，由此提高对纯Ge器件层或更富含Ge的SiGe器件层的蚀刻工艺选择性。在实施例中，已经发现p型掺杂的掩埋层的存在提高了富Ge器件层对Ge器件层底切和/或释放工艺期间(例如，对于栅极全包围器件或纳米线/纳米带器件)所采用的SiGe的湿法蚀刻剂的阻力，由此保留了精细的富Ge纳米线几何形状。
发明人已经发现对于对暴露的Ge层(或相对富含Ge的SiGe层)中的表面原子的氧化状态敏感的特定湿法蚀刻剂，Ge的溶解可能随着掩埋p型掺杂半导体层被引入半导体薄膜堆叠体中而急剧下降。尽管不受理论约束，但(多个)富Ge器件层的提高的蚀刻阻力当前至少部分归因于富Ge器件层与掩埋p型掺杂层之间的电耦合，并且富Ge器件层内的电荷和电子状态由p型掺杂掩埋层中的电荷和电子状态来调制，由此改变了影响的Ge溶解的电过程。在暴露于蚀刻剂的富Ge器件层与掩埋p型掺杂层之间的材料层未掺杂的情况下(即，本征掺杂浓度)，p型掺杂层可以在器件层之下向下移(例如，50-100nm或更大)，并且例如在被暴露于SiGe的湿法蚀刻剂时仍然抑制上覆富Ge半导体器件层的蚀刻。
在一个或多个实施例中，p型δ掺杂的掩埋层设置在半导体器件堆叠体的也可以是δ掺杂层的n型亚沟道泄漏抑制层上方。在p型掺杂层设置在n型掺杂泄漏抑制层之上的情况下，掺杂材料的厚片可以形成掺杂偶极子。与由掺杂偶极子产生的导带不连续性相关联的整流特性在所观察到的Ge蚀刻抑制中也起到一定作用。在富Ge器件层与掩埋p型掺杂层之间的材料层未掺杂(例如本征)的情况下，可以利用δ掺杂的p型掺杂层来实现Ge蚀刻抑制，δ掺杂的p型掺杂层的掺杂剂浓度确保移动电荷被下层n型掺杂泄漏抑制层完全耗尽，以使p型掺杂层的存在不会有害地增大FET器件的源极与漏极之间的亚沟道泄漏。在实施例中，p型δ掺杂的掩埋层在热处理期间(例如，在SiGe相对于Ge的选择性蚀刻之后)可以经历迁移/扩散并且延伸到大于15nm，但仍不能完全补偿泄漏抑制层中的n型掺杂剂，实现了制备期间的Ge蚀刻抑制以及完成的FET器件中的泄漏的抑制。
图1A示出了根据本发明的实施例的包括设置在δ掺杂的过渡层之上的Ge器件层的半导体层堆叠体100的截面图。如图所示，半导体层堆叠体100包括生长在硅(Si)衬底104(例如，作为硅晶片的一部分)上方的基于锗(Ge)的器件层堆叠体108(例如压缩应力锗层)。
衬底104可以由能够承受制造并且能够用作用于堆叠体100中的半导体层的晶体生长的种子层的任何半导体材料组成。在实施例中，衬底104是体衬底，例如通常用于半导体工业中的P型硅衬底。在实施例中，衬底104由掺杂有电荷载流子的晶体硅、硅/锗和锗层组成，电荷载流子例如但不限于磷、砷、硼或其组合。在一个实施例中，衬底104中的硅原子的浓度大于97％，或者替代地，掺杂剂原子的浓度小于1％。在另一个实施例中，衬底104由生长在不同晶体衬底顶上的外延层组成，例如生长在硼掺杂的体硅单晶衬底顶上的硅外延层。衬底104还可以包括设置在体晶体衬底与外延层之间的绝缘层以例如形成绝缘体上硅衬底。在实施例中，绝缘层由例如但不限于二氧化硅、氮化硅、氮氧化硅或高k电介质层的材料组成。替代地，衬底104可以由III-V族材料组成。在实施例中，衬底104由例如但不限于如下材料的III-V材料组成：氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓、磷化铟镓、或其组合。在另一个实施例中，衬底104由III-V材料和电荷-载流子掺杂剂杂质原子组成，电荷-载流子掺杂剂杂质原子例如但不限于碳、硅、锗、氧、硫、硒或碲。
富Ge器件层堆叠体108可以包括一个或多个Ge器件层，图1A中仅示出了第一富Ge器件层108A。在示例性实施例中，富Ge器件层108A的厚度在5-15nm的范围内并且由实质上纯Ge组成(即可以存在一些本征级别的杂质)。设置在Si衬底104与富Ge器件层堆叠体108之间的是硅锗(SiGe)缓冲层堆叠体106(例如，还包括Si0.7Ge0.3的约0.5-1μm的第一层106A和Si0.3Ge0.7的约0.3-1μm的第二层106B)，以适应Ge与Si之间的热和/或晶格失配。替代地，缓冲层堆叠体106可以包括具有梯度型Ge组分(例如，从30％到70％)的SiGe、或者具有不同Ge浓度的SiGe的多个层、或者这些各种类型的缓冲层结构的任何组合。在示例性实施例中，缓冲层堆叠体106紧挨着或者直接设置在Si衬底204之上或上，并且过渡层堆叠体107还紧挨着设置在缓冲层堆叠体106上方或上面，并且同样设置在Si衬底104与器件层堆叠体108之间。
过渡层堆叠体107包括n型掺杂SiGe层107A(例如，松散磷掺杂Si0.3Ge0.7层)。在示例性实施例中，n型掺杂SiGe层107A具有5-20nm的厚度、以及处于1e17-1e19原子/cm3范围内并且有利地为至少1e18cm3的掺杂剂浓度。由于磷和诸如砷的其它n型掺杂剂在SiGe和Ge中快速扩散，所以n型掺杂SiGe层107A从Ge器件层堆叠体108向下移，以减少进入Ge器件层堆叠体108中的n型掺杂剂。例如，n型掺杂SiGe层107A可以位于Ge器件层108之下25-100nm，例如被由松散的本征Si0.3Ge0.7组成的半导体层107C分隔开。替代地，为了进一步改善在器件层108处于“截止”或非导通状态时的短沟道效应和/或泄漏，半导体层107C可以是(或者除了本征Si0.3Ge0.7的厚度以外还包括)作为增强的扩散阻挡层的具有相对低浓度锗的未掺杂Si或SiGe层(例如，<7％的Ge)。因此半导体层107A的总厚度可以差别很大。
过渡层107还包括p型掺杂SiGe层107B(例如，松散的Si0.3Ge0.7层)。在示例性实施例中，p型掺杂SiGe层107B是表层电荷的近似2-D厚片的δ掺杂的层。在这种实施例中，p型掺杂SiGe层107B具有5-15nm的厚度，可以通过过渡层堆叠体107的外延生长期间的原位掺杂来获得。更大的厚度也是可以的，但受到约束，以避免完全补偿n型掺杂层107A。在示例性实施例中，p型掺杂SiGe层107B具有处于5e17-1e19cm3之间的掺杂，有利地为至少1e18cm3。在示例性实施例中，p型掺杂剂种类是硼，但可以预期其它p型掺杂剂种类来执行类似功能。
图1B示出了根据本发明的实施例的包括诸如层107B的δ掺杂的p型SiGe过渡层的半导体层堆叠体的掺杂剂浓度沿深度分布的曲线图，δ掺杂的p型SiGe过渡层设置在诸如SiGe层107A的n型掺杂泄漏抑制层之上。所示掺杂剂浓度沿深度分布图表示与“退火”状态相反的半导体堆叠体的“生长”状态。如图1B所示，硼掺杂的SiGe过渡层在被标记为“107B”的约15nm跨度之上具有超过2e18cm-3的硼浓度以及接近至少1e18cm-3的δ掺杂。横跨被标记为“107A”的达到约1e18cm-3的磷掺杂深度对应于SiGe过渡层n型掺杂泄漏抑制层。如图1B所示的，磷掺杂层107A具有比硼掺杂层107B大的厚度并且比硼掺杂层107B(即，非δ掺杂的)更渐变。
在实施例中，p型SiGe过渡层与下层n型SiGe过渡层通过对SiGe层进行非有意掺杂(例如，本征掺杂)来间隔开。这种间隔层在图1A中被标记为107A’并且具有最小厚度(例如2-5nm)，其取决于生长速率动力学和生长室在n型与p型掺杂剂之间切换的迅速性。间隔层107A’是SiGe(例如，Si0.3Ge0.7)，它是在n型掺杂剂终止之后并且在引入p型掺杂剂之前生长的。图1B中示出了针对一个实施例的间隔层107A’的有效掺杂，其中硼和磷掺杂水平低于5e17cm-3。在实施例中，间隔层107A’具有2-5nm的厚度。对于处于该范围的上限的实施例，层107A、107A’和107B可以被表征为p-i-nδ掺杂结构，其中至少p型层是δ掺杂层。
取决于实施例，半导体堆叠体100可以是设置在衬底的整个区域之上的“整体”膜堆叠体(例如，图1A中的衬底104表示整个晶片)，或者是设置在衬底的仅特定部分之上的“局部”膜堆叠体(例如，图1A中的衬底104表示晶片的小部分)。在任一实施例中，半导体堆叠体100可以利用已知的适合于SiGe材料的外延技术形成，所述技术例如但不限于CVD和分子束外延(MBE)。如本文所使用的，“外延”层与种子表面配准(例如，由于种子表面的结晶性而具有优选晶体取向)。图2A和2B示出了一个局部生长实施例的截面图，其中图1A中描绘的半导体层堆叠体是利用长宽比俘获(aspect ratio trapping)(ART)的益处而生长的。
如图2A所示，隔离电介质具有侧壁250，其限定了具有暴露在沟槽底部的半导体种子表面的沟槽260。如图2B所示，晶体半导体的局部和选择性外延生长在设置于衬底204(例如，具有针对衬底104所述的性质)上的SiGe缓冲层206A(例如，具有针对层106A所述的性质)之上形成SiGe缓冲层206B(例如，具有针对层106A所述的性质)。同样设置在沟槽260中的是过渡层207A、207B和207C(例如，具有分别针对层107A、207B和107C所述的性质)、以及具有中间牺牲层209A和209B的器件层208A和208B。在示例性实施例中，牺牲层209A和209B均是SiGe层并且均可以具有相同成分。在有利的实施例中，牺牲层209A和209B中的Ge浓度低于过渡层中的Ge浓度(例如，<70％的Ge)，以具有相对于过渡层207C的期望的应变水平(例如，1-1.5％)。在一个实施例中，器件层208A和208B实质上均是纯Ge。在另一个实施例中，器件层208A和208B均具有比可以是SiGe合金或硅的牺牲层209A和209B更富含Ge的SiGe成分。
图3A和3B示出了采用半导体堆叠体100的平面半导体器件实施例的截面图。首先参考图3B，半导体器件300包括设置在衬底304上方的栅极堆叠体305。富Ge器件层308A设置在衬底304上方、栅极堆叠体305下方。通常，半导体器件300可以是包含栅极、沟道区和一对源极/漏极区的任何半导体器件，例如但不限于MOS-FET。在示例性实施例中，器件300是PMOS FET，其用作CMOS集成电路内的互补晶体管类型的其中之一。
在示例性实施例中，富Ge器件层308A实质上是1-2％压缩应变的纯Ge。SiGe过渡层307C设置在衬底304上方、锗有源层308A之下。n型结泄漏抑制层307A设置在衬底304上方，并且p型Ge蚀刻抑制层307B设置在过渡层307C与结泄漏抑制层307A之间，如堆叠体100的上下文中所述。在示例性PMOS实施例中，凸起的源极和漏极区322被沉积或生长了重掺杂的p型(例如，硼)并且设置在结泄漏抑制层307A上方，位于栅极堆叠体305的任一侧上。源极/漏极区322可以形成具有或不具有n型结泄漏抑制层307A的p+/n结(例如，源极/漏极区322设置在过渡层307C的上部上)。
在图3A所示的实施例中，栅极堆叠体305直接设置在Ge有源层308A上，锗器件层308A直接设置在未掺杂的SiGe过渡层307C上，过渡层307C直接设置在p型过渡层307B上，p型过渡层307B直接设置在结泄漏抑制层307A上(其间仅具有例如107A’的SiGe间隔体)。
栅极堆叠体305可以包括直接设置在栅极电介质层305A上的栅极电极305B，如图3A所示。在实施例中，栅极电极305B由金属栅极组成并且栅极电介质层305A由高K材料组成。例如，在一个实施例中，栅极电介质层305A由例如但不限于如下材料的材料组成：氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸钪铅、和铌酸铅锌或其组合。此外，栅极电介质层305A的一部分可以包括由富Ge器件层308A的顶部几层形成的原生氧化物层。在实施例中，栅极电介质层305A由顶部高k部分和由半导体材料的氧化物组成的下部组成。在一个实施例中，栅极电介质层305A由氧化铪的顶部部分和二氧化硅或氮氧化硅的底部部分组成。
在实施例中，栅极电极305B由金属层组成，所述金属层例如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍、或导电金属氧化物。在特定实施例中，栅极电极305B由形成在金属功函数设定层上方的非功函数设定填充材料组成。在实施例中，栅极电极305B由P型材料组成。栅极堆叠体305还可以包括电介质间隔体318，如图3A所示。
如图3B所示，源极和漏极区322是“嵌入”或“凸起”的替换源极和漏极区。图3A还示出了器件300的制备期间的截面图。参考图3A，在示例性实施例中，去除了富Ge器件层308A的部分以及顶部过渡层307C的部分、以及甚至p型过渡层307B的部分，以在栅极堆叠体305的任一侧上提供凹陷区320。凹陷区320可以由去除器件层308A的部分等的任何适合的技术形成，例如干法蚀刻或湿法蚀刻工艺。在一个实施例中，利用对富Ge器件层308A的氧化状态敏感的湿法蚀刻形成凹陷区320的至少一部分，该湿法蚀刻，湿法蚀刻例如但不限于如氢氧化铵(NH4OH)、氢氧化钾(KOH)、氢氧化四甲基铵(TMAH)或其它氢氧化四烷铵的氢氧化物水溶液化学物质。在一个实施例中，区域320的第一凹陷需要使用NF3、HBr、SF6或Cl2来进行干法等离子体蚀刻，以限定富Ge器件层308A，而区域320的第二凹陷需要使用氢氧化物水溶液化学物质来进行SiGe过渡层307C的湿法蚀刻。p型过渡层307B的存在对于凹陷区320的形成是有利的，例如允许富Ge器件层308A的第一蚀刻，之后是顶部过渡层307C的对富Ge器件层308A(例如是纯Ge)具有高度选择性(接近无限)的SiGe蚀刻。像这样，可以极为准确地形成源极、漏极区的接近器件沟道的末端的尖端，以允许FET的栅极长度(Lg)的缩放。在一个实施例中，栅极堆叠体305引导凹陷区320的形成(即，自对准的凹陷区320)。在一个实施例中，凹陷区320形成有圆角，如图3B所示。然而，在另一个实施例中，凹陷区320形成有刻面角。在实施例中，n型泄漏抑制层307A用作凹陷区320的形成期间的蚀刻停止。再次参考图3B，一对嵌入的源极、漏极区322外延或非外延地形成在凹陷区320中。在实施例中，源极、漏极区322是单轴压缩应力富Ge器件层308并且由具有大于锗的晶格常数的材料组成，所述材料例如是具有大于锗的晶格常数的III-V材料。
如上所述，本发明的实施例可以应用于非平面MOS-FET。例如，诸如三栅极器件的具有三维架构的器件可以得益于包括掩埋p型过渡层的半导体器件堆叠体。图4A-4C示出了根据本发明的实施例的表示制备采用图1A的半导体堆叠体的非平面半导体器件的方法中的各种操作的角视图。
通常，非平面FET实施例可以通过使鳍状物形成在具有极精细的横向尺寸(例如，<22nm)的富Ge器件层中而得益于掩埋p型Ge蚀刻抑制层。在形成富Ge鳍状物后，可以利用针对富Ge鳍状物结构的实质上无限的选择性来蚀刻SiGe的包围和/或下层区，从而可以利用沿富Ge结构形成的化学上明显的界面来很好地控制沟道长度、和/或源极/漏极尖端、和/或亚沟道特征尺寸。
参考图4A，半导体器件400包括设置在衬底404上方的栅极堆叠体405。三维富Ge器件主体408A设置在衬底404上方并且在栅极堆叠体405下方。隔离区420设置在衬底404上方，并且三维器件主体408A从其延伸(器件主体与隔离区420共面也是可能的)。顶部过渡层407C设置在衬底404上方、三维富锗器件主体408A下方。Ge蚀刻抑制层407B设置在顶部过渡层407C下方并且具有在器件堆叠体100(图1)的层107B的上下文中在本文中其它位置所描述的性质中的至少一些。层407B设置在结泄漏抑制层407C上方，结泄漏抑制层407C设置在缓冲层406和衬底404上方。器件400中的全部半导体层的材料成分和尺寸与针对半导体器件300所述的那些相同或相似，因为两个器件实施例都采用半导体堆叠体100。
在一个实施例中，利用对富Ge器件层408A的氧化状态敏感的湿法蚀刻来形成隔离区420的至少一部分和/或由隔离区420包围的非平面半导体器件堆叠体，所述湿法蚀刻例如但不限于本文中其它位置所述的氢氧化物水溶液化学物质(TMAH等)。在一个实施例中，用于形成隔离区420的半导体器件堆叠体(例如，堆叠体100)的第一蚀刻需要例如但不限于NF3、HBr、SF6或Cl2的干法等离子体蚀刻。例如，通过干法蚀刻暴露的半导体堆叠体的干法蚀刻侧壁的第二蚀刻需要使用氢氧化物水溶液化学物质进行的SiGe过渡层307C的湿法蚀刻。替代地或另外，隔离区420相对于非平面半导体主体的凹陷可以包括对富Ge器件层408A的氧化状态敏感的湿法蚀刻，例如但不限于本文中其它位置所描述的氢氧化物水溶液化学物质(TMAH等)。在任一情况下，p型过渡层307B的存在实现了对富Ge器件层308A(例如是纯Ge)具有高度选择性(接近于无限)的顶部过渡层307C的SiGe蚀刻。
器件主体408A的未设置在栅极堆叠体405(和周围的电介质间隔体418)之下的部分是掺杂的源极和漏极区。根据本发明的实施例，隔离区420凹陷到三维富Ge(例如，纯Ge)器件主体408A和顶部过渡层407C(例如，Si0.3Ge0.7)的界面，如图4A所示。然而，其它实施例可以包括将隔离区420的高度设定为高于和低于该特定界面。
在实施例中，通过掺杂(例如p型)三维锗有源主体406的未被栅极堆叠体405覆盖的部分来形成源极和漏极区。过渡层407C的部分在源极和漏极区中也可以p型掺杂的，并且p型掺杂剂一直延伸到p型层407B中，以形成p+/n二极管，并且n型泄漏抑制层407A位于非平面器件主体的相对末端。然而，在另一个实施例中，源极和漏极区是嵌入的源极和漏极区。例如，图4B和4C示出了根据本发明的另一个实施例的具有带有下层扩散阻挡层的富Ge器件层的另一个半导体器件的制备中的截面图。
参考图4B，去除三维富Ge主体408A的部分、以及可能的过渡层407C和p型过渡层407B的部分，以在栅极堆叠体405的任一侧上提供凹陷区422。凹陷区422可以由诸如干法蚀刻或湿法蚀刻工艺的去除三维富Ge器件主体408A的部分等的任何适合的技术形成。在一个实施例中，利用诸如本文中其它位置所描述的氢氧化物水溶液化学物质(TMAH等)的对富Ge器件层408A的氧化状态敏感的湿法蚀刻来形成凹陷区422的至少一部分。在一个实施例中，区域422的第一凹陷需要使用NF3、HBr、SF6或Cl2进行干法等离子体蚀刻来限定富Ge器件层408A，而区域422的第二凹陷需要使用NH4OH或TMAH或类似物质来进行湿法蚀刻。p型过渡层407B的存在对于凹陷区422的形成是有利的，例如允许富Ge器件层408A的第一蚀刻之后是对富Ge器件层408A(例如是纯Ge)具有高度选择性(接近无限)的过渡层407C的SiGe蚀刻。像这样，可以极为准确地形成源极区、漏极区的尖端，允许FET的栅极长度(Lg)的缩放。在一个实施例中，栅极堆叠体405引导凹陷区422的形成，以形成自对准的凹陷区422。在实施例中，n型泄漏抑制层407A用作凹陷区422的形成期间的蚀刻停止。
参考图4C，在凹陷区422中外延或非外延地形成一对凸起的源极区、漏极区424。在实施例中，源极区、漏极区424是单轴压缩应力的富Ge器件层408A，并且由具有大于锗的晶格常数的材料组成，例如由具有大于锗的晶格常数的III-V材料组成。
图5A示出了根据本发明的实施例的采用图1A的半导体堆叠体的纳米线或纳米带半导体器件的等距截面图。图5B示出了根据本发明的实施例的图5A的基于纳米线的半导体结构的截面沟道视图。图5C示出了根据本发明的实施例的图5A的基于纳米线的半导体结构的截面图。
首先参考图5A，半导体器件500包括设置在衬底504上方的一个或多个垂直对齐或堆叠的锗纳米线(508组)。本文的实施例包括单线器件或多线器件。作为示例，出于说明的目的而示出了具有纳米线508A、508B的基于两个纳米线的器件。为便于描述，将纳米线508A用作示例，其中描述仅集中于组508中的纳米线的其中之一。要理解，在描述了一个纳米线的属性的情况下，基于多个纳米线的实施例可以具有与纳米线中的每个纳米线相同的属性。
富Ge(例如，纯Ge)纳米线508中的每一个都包括设置在纳米线中的沟道区506。沟道区506具有长度(L)。参考图5B，沟道区还具有与长度(L)垂直的周界。参考图5A和5B，栅极堆叠体505包围沟道区506中的每一个的整个周界。栅极堆叠体505包括栅极电极以及设置在沟道区506与栅极电极(未单独示出)之间的栅极电介质层。沟道区506是分立的，因为它被栅极堆叠体505完全包围，而没有与富Ge纳米线508相隔的诸如下层衬底材料(例如，参考堆叠体100的过渡层107C)或其它牺牲沟道制备材料之类的任何中间材料。因此，在具有多个纳米线508的实施例中，纳米线的沟道区506也是相对于彼此分立的，如图5B所示。结泄漏抑制层507A设置在衬底504上方、一个或多个锗纳米线508下方。栅极堆叠体505设置在n型泄漏抑制层507A之上，并且可以设置在SiGe过渡层507C上，如图所示。尽管未描绘，但是在实施例中，缓冲层可以直接设置在衬底504与结泄漏抑制层507A之间，大体上如在器件堆叠体100的环境下所述的。
再次参考图5A，纳米线508中的每一个还包括设置在沟道区506的任一侧上的纳米线中的源极区和漏极区510和512。如图所示，源极区和漏极区510/512设置在SiGe过渡层507C上。在实施例中，源极区和漏极区510/512是替换的源极区和漏极区，例如，纳米线的至少一部分被去除并被替换为源极/漏极材料区。然而，在另一个实施例中，源极区和漏极区510/512由仅掺杂(例如，由硼注入等)的一个或多个锗纳米线508的部分组成。
一对接触部514(图5A中的虚线)设置在源极区/漏极区510/512之上。在实施例中，半导体器件500还包括一对间隔体516(图5A中的虚线)。间隔体516设置在栅极堆叠体505与接触部对514之间。如上所述，在至少几个实施例中，沟道区和源极/漏极区被制成分立的。然而，并不是纳米线508的所有区域都必需是分立的。例如，参考图5C，纳米线508A-508B在间隔体516下的位置处不是分立的。在一个实施例中，纳米线508A-508B的堆叠体具有位于它们之间的中间牺牲半导体材料(509B)和位于它们下面的中间牺牲半导体材料(509A)，其可以是SiGe(例如，具有比过渡层107C低的Ge浓度)或硅。在一个实施例中，底部纳米线508A仍与过渡层507C的一部分接触，例如，用于如下所述的制备中。
在实施例中，一个或多个富Ge纳米线508实质上由锗组成，过渡层507C是Si0.3Ge0.7，p型Ge蚀刻抑制层507B是p型掺杂的Si0.3Ge0.7，并且结泄漏抑制层507A是n型掺杂的Si0.3Ge0.7，如本文的其它位置针对器件堆叠体100所述的。在实施例中，一个或多个Ge纳米线508是压缩压力的(例如，相对于过渡层507C的1-2％)。
尽管上述器件500是用于例如PMOS器件的单个器件的，但是CMOS架构也可以被形成为包括设置在相同衬底上或之上的基于NMOS纳米线的器件和基于PMOS纳米线的器件。在实施例中，纳米线508的尺寸可以被调整为z维度和y维度大体上相同的线，或者z维度和y维度的其中之一大于另一个的带。纳米线508可以具有方形、圆形或刻面(例如在与z和y轴非正交的一些角度下)。材料组成和尺寸可以与针对半导体堆叠体100和器件300或400所述的相同或相似。
在另一个方面，提供了制备纳米线半导体结构的方法。例如，图6A-6D示出了根据本发明的实施例的表示制备纳米线半导体器件的方法中的各种操作的三维截面图，所述纳米线半导体器件在工艺中的至少一点处具有带有下层SiGe过渡层和p型掺杂的Ge蚀刻抑制层的富Ge器件层。
参考图6A，鳍状物型结构612形成在衬底604上方。鳍状物包括富Ge器件层608A’和608B’、以及两个中间富硅材料层609A’和609B’，例如硅或Si含量高于器件层608A’和608B’的硅锗层。鳍状物停止在过渡层607C上，尽管在其它实施例中，鳍状物型结构612可以向下延伸以包括过渡层607C的图案化部分。尽管未示出，但是在实施例中，缓冲层直接设置在衬底604与结泄漏抑制层607C之间。
图6B示出了具有设置于其上的三个牺牲栅极结构614A、614B和614C的鳍状物型结构612。在一个这种实施例中，三个牺牲栅极614A、614B和614C由牺牲栅极氧化物层616和牺牲多晶硅栅极层618组成，它们例如是均厚沉积的并利用本领域中常规的等离子体蚀刻工艺来进行图案化。
在图案化以形成三个牺牲栅极614A、614B和614C之后，可以在三个牺牲栅极614A、614B和614C的侧壁上形成间隔体，并且在图6B所示的鳍状物型结构612的区域620中执行掺杂(例如，尖端和/或源极和漏极型掺杂)，并且可以形成层间电介质层以覆盖并且然后再次暴露三个牺牲栅极614A、614B和614C。然后可以抛光层间电介质层以暴露三个牺牲栅极614A、614B和614C，它们用于替换栅极或后栅工艺。参考图6C，三个牺牲栅极614A、614B和614C以及间隔体622和层间电介质层624被暴露。
然后例如可以在本领域中常规的针对所选择的材料的替换栅极或后栅极工艺流程中去除牺牲栅极614A、614B和614C，以暴露鳍状物型结构612的沟道部分。参考图6D，去除牺牲栅极614A、614B和614C，以提供沟槽626，并且因此露出纳米线的沟道部分。去除中间牺牲层的由沟槽626暴露的部分以留下富Ge器件层608A’和608B’的分立的部分，以形成纳米线608A和608B。在图6D中，为清楚起见而示出了牺牲材料609A，但是其通常会与设置在608A与608B之间的牺牲层同时被去除。
在实施例中，利用不会蚀刻富Ge器件层608A’和608B’的湿法蚀刻来选择性地蚀刻富硅牺牲层609A和609B，以释放或底切器件层608A’和608B’的没有被其它结构(例如，间隔体622)固定的长度。在一个实施例中，湿法蚀刻对富Ge器件层608A’和608B’的氧化状态敏感。蚀刻化学物质例如但不限于氢氧化物水溶液化学物质，包括NH4OH、KOH和TMAH，例如可以用于选择性蚀刻牺牲层609A和609B。p型过渡层607B的存在对于改进SiGe蚀刻相对于富Ge器件层608A’和608B’的选择性是有利的。在器件层608A’和608B’是示例性的纯Ge的实施例中，蚀刻选择性对于纳米线而言接近无限，以使得可以沿着与器件层608A’和608B’的化学清晰的界面来去除牺牲层609A和609B(即，不蚀刻器件层的任何部分)。
在替代的实施例中，尽管未示出，还可以例如在去除牺牲层609A和609B之前、之后或同时去除过渡层607C和607B。同样，可以完全或仅部分去除扩散阻挡层，例如在间隔体下留下剩余部分，或者替代地可以完整保留。随后可以完成器件制备。在一个实施例中，包围的栅极电极形成在锗纳米线604和608周围并且在泄漏抑制层507A之上，如以上结合图5A所述。
在图6D中所示的处理阶段，可以执行沟道布置或调整。例如，在一个实施例中，可以使用氧化和蚀刻工艺等来减薄富Ge器件层608A’和608B’的分立部分。因此，由富Ge层608A’和608B’形成的最初的线可以在开始较厚，并且被减薄到适合于纳米线器件中的沟道区的尺寸，这与器件的源极区和漏极区的尺寸调整无关。
在如图6D所示的分立沟道区的形成之后，可以执行高-k栅极电介质和金属栅极处理，并且可以添加源极接触部和漏极接触部。可以形成接触部以代替图6D中剩余的层间电介质层624部分。此外，一种或多种热处理可以对半导体层进行退火，以使p型掺杂层607B和n型掺杂层607A可以一起扩散，即使是在p型和n型掺杂剂没有在如图1B中所示的掺杂剂分布图中形成单独的峰值的点。然而n型掺杂层607A没有完全被p型掺杂层607B补偿，并且由于可以在SiGe牺牲层的选择性蚀刻之后很好地执行退火，所以仍可以实现p型掺杂层607A的功能。
图7示出了根据本发明的一种实施方式的计算设备700。计算设备700容纳板702。板702可以包括许多部件，这些部件包括但不限于处理器704和至少一个通信芯片706。处理器704物理和电耦合到板702。在一些实施方式中，至少一个通信芯片706也物理和电耦合到板702。在其它实施方式中，通信芯片706是处理器704的一部分。
取决于其应用，计算设备700可以包括其它部件，所述其它部件可以或可以不与板702物理和电耦合。这些其它部件包括但不限于：易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、加密处理器、芯片集、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如，硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。
通信芯片706可以实现用于来往于计算设备700的数据传输的无线通信。术语“无线”及其衍生词可以用于描述电路、设备、系统、方法、技术、通信信道等，其可以通过使用调制的电磁辐射而经由非固态介质传送数据。术语并不暗示相关联的设备不包含任何线路，尽管在一些实施例中相关联的设备可能不包含任何线路。通信芯片706可以实施多种无线标准或协议中的任何一种，所述多种无线标准或协议包括但不限于Wi-Fi(IEEE802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及其衍生物、以及被指定为3G，4G，5G和更高代的任何其它无线协议。计算设备700可以包括多个通信芯片706。例如，第一通信芯片706可以专用于较短范围的无线通信，例如，Wi-Fi和蓝牙，并且第二通信芯片706可以专用于较长范围的无线通信，例如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备700的处理器704包括封装在处理器704内的集成电路管芯。在本发明的一些实施例中，处理器的集成电路管芯包括一个或多个器件，例如根据本文中其它位置所述的实施例构建的MOS-FET。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将这些电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的一部分
通信芯片706也包括封装在通信芯片706内的集成电路管芯。根据本发明的另一个实施例，通信芯片的集成电路管芯包括一个或多个器件，例如具有根据本文其它位置所述的实施例的特征和/或据此制备的MOS-FET。
在其它实施方式中，容纳在计算设备700中的另一个部件可以包含集成电路管芯，其包括一个或多个器件，例如具有根据本文其它位置所述的实施例的特征和/或据此制备的MOS-FET。
在实施例中，计算设备700可以是膝上型电脑、上网本、笔记本电脑、超极本、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字录像机。
要理解，以上描述旨在进行说明而非进行限制。此外，本领域技术人员在阅读并理解了以上描述后，许多其它实施例将是显而易见的。尽管已经参考特定示例性实施例描述了本发明，但是将认识到，本发明并不限于所描述的实施例，而是可以利用处于所附权利要求书的精神和范围内的修改和变化来实践本发明。因此本发明的范围应该参考所附权利要求以及为这种权利要求赋予权利的等同物的完整范围来确定。

Claims (20)

1.一种半导体器件堆叠体，包括：
设置在硅(Si)衬底上方的富锗(Ge)器件层；
SiGe过渡层，其设置在所述衬底上方、并且设置在所述器件层下方；
p型δ掺杂的SiGe层，其设置在所述衬底上方、并且设置在所述过渡层下方；
n型SiGe层，其设置在所述衬底上方、并且设置在所述p型δ掺杂的SiGe层下方；以及
一个或多个SiGe缓冲层，其设置在所述衬底上方、并且设置在所述n型SiGe层下方。
2.根据权利要求1所述的半导体器件堆叠体，其中，所述器件层是由中间牺牲半导体层分隔开的多个器件层的其中之一，并且第一器件层直接设置在第一牺牲层上，所述第一牺牲层直接设置在所述过渡层上，所述过渡层直接设置在所述p型δ掺杂的SiGe层上，并且所述p型δ掺杂的SiGe层与所述n型SiGe层由SiGe间隔体层分隔开。
3.根据权利要求2所述的半导体器件堆叠体，其中，所述牺牲层具有比所述器件层低的Ge浓度；并且
其中，所述过渡层、所述p型δ掺杂的SiGe层、所述SiGe间隔体层和所述n型SiGe层都具有相同的硅和锗含量。
4.根据权利要求3所述的半导体器件堆叠体，其中，所述过渡层的厚度在25到100nm之间，所述p型δ掺杂的SiGe层的厚度在5到15nm之间，所述SiGe间隔体层的厚度在2到5nm之间，并且所述n型SiGe层的厚度在5到20nm之间。
5.根据权利要求4所述的半导体器件堆叠体，其中，所述过渡层是本征的，其中，所述p型δ掺杂的SiGe层具有至少1e18cm-3的硼掺杂剂浓度，并且其中，所述n型SiGe层具有至少1e18cm-3的磷掺杂剂浓度。
6.根据权利要求4所述的半导体器件堆叠体，其中，所述器件层实质上由锗组成，是未掺杂的，并且每个层具有处于5到15nm之间的厚度，并且其中，所述牺牲半导体层由SiGe组成，并且每个层具有处于5到30nm之间的厚度。
7.根据权利要求1所述的半导体器件堆叠体，其中，至少所述器件层和所述过渡层嵌入在相邻隔离区内，所述相邻隔离区同样设置在所述衬底上。
8.一种半导体器件，包括：
栅极堆叠体，其包括设置在根据权利要求1所述的半导体器件堆叠体之上的栅极电介质和栅极电极，其中，所述栅极电介质与器件层直接接触；以及
设置在所述栅极堆叠体的相对侧上的源极区和漏极区。
9.根据权利要求8所述的半导体器件，其中，所述器件层包括非平面主体，所述非平面主体具有从设置在所述衬底上方并且与器件堆叠体相邻的电介质隔离区延伸的两个相对侧壁，并且其中，所述栅极堆叠体设置在所述侧壁上。
10.一种半导体器件，包括：
在硅(Si)衬底之上垂直对齐的多个富锗(Ge)纳米线；
设置在所述多个纳米线与所述衬底之间的SiGe过渡层；
设置在所述SiGe过渡层下方的p型δ掺杂的SiGe层；
设置在所述p型δ掺杂的SiGe层与所述衬底之间的n型掺杂的SiGe层；
栅极堆叠体，其设置在所述多个纳米线之上并且完全包围所述多个纳米线中的每一个的长度；
间隔体，其被设置成与所述栅极堆叠体相邻；以及
源极区/漏极区，其被设置成与所述栅极堆叠体的相对侧上的所述间隔体相邻、与所述多个纳米线接触。
11.根据权利要求10所述的半导体器件，其中，所述多个纳米线被中间牺牲半导体层沿着被所述间隔体覆盖的所述纳米线的长度垂直分隔开，并且第一纳米线直接设置在第一牺牲半导体层上，所述第一牺牲半导体层直接设置在所述过渡层上，所述过渡层直接设置在所述p型δ掺杂的SiGe层上，并且所述p型δ掺杂的SiGe层与所述n型SiGe层由SiGe间隔体层分隔开。
12.根据权利要求11所述的半导体器件，其中，所述富锗(Ge)纳米线实质上由Ge组成，其中，所述牺牲半导体层包含硅。
13.根据权利要求12所述的半导体器件，其中，所述过渡层的厚度在25到100nm之间，所述p型δ掺杂的SiGe层的厚度在5到15nm之间，所述SiGe间隔体层的厚度在2到5nm之间，并且所述n型SiGe层的厚度在5到20nm之间。
14.根据权利要求13所述的半导体器件，其中，所述过渡层是本征的，其中，所述p型δ掺杂的SiGe层具有至少1e18cm-3的硼掺杂剂浓度，并且其中，所述n型SiGe层具有至少1e18cm-3的磷掺杂剂浓度。
15.根据权利要求13所述的半导体器件，其中，沿着由所述栅极堆叠体包围的长度的纳米线是未掺杂的，并且每一个具有处于5到15nm之间的厚度，并且其中，所述牺牲层均具有处于5到30nm之间的厚度。
16.根据权利要求10所述的半导体器件，其中，所述栅极堆叠体直接设置在所述过渡层上。
17.一种制备纳米线半导体器件的方法，所述方法包括：
接收半导体器件堆叠体，所述半导体器件堆叠体包括：
设置在牺牲半导体层上的富锗(Ge)器件层，所述牺牲半导体层比所述器件层包括更多的硅(Si)；
p型δ掺杂的SiGe层，其掩埋在所述牺牲半导体层下方；
利用湿法蚀刻剂对所述器件层有选择性地蚀刻所述牺牲半导体层的至少部分厚度，以底切所述器件层并且形成纳米线的分立的沟道区；以及
形成完全包围所述纳米线的所述分立的沟道区的栅极堆叠体。
18.根据权利要求17所述的方法，其中，所述湿法蚀刻剂从由以下化学物质组成的组中选择：
氢氧化铵、氢氧化钾和氢氧化四甲基铵(TMAH)。
19.根据权利要求19所述的方法，其中，所述湿法蚀刻剂在所述器件层与所述牺牲半导体层之间形成化学清晰的界面。
20.根据权利要求17所述的方法，其中，在不将所述p型δ掺杂的SiGe层暴露于所述湿法蚀刻剂的情况下执行所述蚀刻。
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