CN106611787A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN106611787A
CN106611787A CN201510700127.9A CN201510700127A CN106611787A CN 106611787 A CN106611787 A CN 106611787A CN 201510700127 A CN201510700127 A CN 201510700127A CN 106611787 A CN106611787 A CN 106611787A
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epitaxial layer
semi
conducting material
concentration
layer
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黄世贤
陈建宏
吴俊元
陈坤新
吴典逸
杨玉如
江怀慈
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/941,674 priority patent/US10497797B2/en
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构，包含有一半导体基底，以及至少一形成于该半导体基底上的鳍片结构。该半导体基底包含有一第一半导体材料。该鳍片结构包含有一第一外延层与一形成于该第一外延层与该半导体基底之间的第二外延层，而该第一外延层包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数。该第二外延层包含有该第一半导体材料与该第二半导体材料，且该第二外延层包含有导电掺杂质。

Description

半导体结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，尤其是涉及一种半导体鳍片结构及其制作方法。
背景技术
外延(epitaxial)结构广泛地用于半导体制作工艺中，举例来说，现有技术常利用选择性外延成长(selective epitaxial growth，以下简称为SEG)技术于一单晶基板内形成一晶格排列与基板相同的外延结构，例如硅锗(silicongermanium，以下简称为SiGe)外延结构。利用SiGe外延结构的晶格常数(lattice constant)大于硅基板晶格的特点，SiGe外延结构可产生应力，并用于改善MOS晶体管的性能。
然而，外延结构的采用固然可有效提升元件效能，但外延结构的制作大大地增加了半导体制作工艺的复杂度以及制作工艺控制的困难度。举例来说，在SiGe外延结构中，可增加锗浓度来提升应力，然而较厚的SiGe外延结构或SiGe外延结构中较高的锗浓度会在外延结构内产生差排(dislocation)，而差排的产生会导致外延结构提供的应力变低，因此更增加了具有外延结构的半导体元件在设计与制作上的难度。
由此可知，外延结构的存在虽可有效增进元件效能，但随着半导体制作工艺与产品的复杂度不断提升，业界仍不断地面对挑战。
发明内容
因此，本发明的一目的在于提供一种半导体结构及其制作方法，用以克服外延结构生成时可能发生的差排缺陷，且最终提升半导体元件的性能。
为达上述目的，本发明提供一种半导体结构，该半导体结构包含有一半导体基底，以及至少一形成于该半导体基底上的鳍片(fin)结构。该半导体基底包含有一第一半导体材料。该鳍片结构包含有一第一外延层与一形成于该第一外延层与该半导体基底之间的第二外延层，而该第一外延层包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数。该第二外延层包含有该第一半导体材料与该第二半导体材料，且该第二半导体材料包含有导电掺杂质(conductivedopant)。
本发明另提供一种半导体结构的制作方法，该制作方法包含有以下步骤：首先提供一半导体基底，该半导体基底包含有一第一半导体材料。此外，该半导体基底上形成有一介电层，且该介电层内形成有至少一凹槽。接下来，在该凹槽内形成一第二外延层，该第二外延层包含有该第一半导体材料与一第二半导体材料，该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数，且该第二外延层包含有导电掺杂质。在形成该第二外延层之后，在该第二外延层上形成一第一外延层，该第一外延层包含该第一半导体材料与该第二半导体材料，且该第一外延层为一未掺杂(undoped)外延层。之后，移除部分该介电层，以在该半导体基底上形成一鳍片结构。
根据本发明所提供的半导体结构及其制作方法，在形成作为主要应力供应者的第一外延层之前，至少形成一第二外延层，且第二外延层包含有导电掺杂质。更重要的是，第二外延层所包含的导电掺杂质与所欲制作的晶体管元件具有互补(complementary)的导电型态。是以，第二外延层可作为一抗凿穿(anti punch through，APT)层。简单地说，根据本发明所提供的半导体结构及其制作方法，最终形成的晶体管元件除可通过第一外延层提供的应力提升性能之外，更可通过第二外延层的设置有效地防止凿穿效应的发生，故可更加确保晶体管元件的性能。
附图说明
图1至图8为本发明所提供的半导体结构的制方法的一优选实施例的示意图，其中：
图2为本发明所提供的半导体结构的制方法的一变化型的示意图；以及
图4为本发明所提供的半导体结构的制方法的另一变化型的示意图。
主要元件符号说明
100 半导体基底
102 介电结构
102S 介电结构表面
104、104’ 凹槽
106、110、120、130 外延层
112、122 热处理
140 鳍片结构
150 栅极层
152 栅极介电层
154 栅极导电层
D 凹槽深度
WF 凹槽宽度
T1、T2、T3 外延层厚度
HFin 鳍片高度
具体实施方式
请参阅图1至图8，图1至图8为本发明所提供的半导体结构的制作方法的一优选实施例的示意图。如图1所示，本优选实施例所提供的半导体结构的制作方法首先提供一半导体基底100。半导体基底100包含有一第一半导体材料，第一半导体材料可以是硅、锗、III-V族化合物(compound)、或者是II-VI族化合物。在本优选实施例中，第一半导体材料优选为硅，然而不限于此。另外，在本优选实施例中，半导体基底100可以是一块硅(bulk)基底，且可具有(100)晶面(crystal plane)。接下来，可在半导体基底100上形成一介电结构102，介电结构102的制作方式可采用浅沟隔离(shallow trenchisolation，以下简称为STI)的制作方法。简单地说，首先在基底100上依序形成一垫氧化层(图未示)与一硬掩模层(图未示)，随后图案化垫氧化层与硬掩模层。图案化的垫氧化层与硬掩模层可用以定义鳍片结构的位置与宽度，但不限于此。接下来，利用合适的蚀刻制作工艺通过此一图案化的垫氧化层与硬掩模层蚀刻半导体基底100，而在半导体基底100内形成多个凹槽(图未示)。随后，在该多个浅沟内填入绝缘材料。
接下来，进行一平坦化制作工艺，用以移除多余的绝缘材料与图案化的硬掩模层与垫氧化层，而在半导体基底100上形成多个STI，而该多个STI即为本优选实施例中所述的介电结构102。接下来，进行一干蚀刻制作工艺，用以移除STI 102之间的半导体基底100，而于STI之间，即介电结构102内形成至少一凹槽104。在本优选实施例中，凹槽104的底部可如图1所示，与介电结构102的底部共平面。另外，如图1所示，凹槽104具有一宽度WF以及一深度D，凹槽104的宽度WF可用以定义一鳍片结构的宽度，而在本优选实施例中凹槽104的深度D可以例如是100纳米(nanometer，nm)至300nm，但不限于此。
另外请参阅图2，图2为本发明所提供的半导体结构的制作方法的一变化型的示意图。在本变化型中，可如前所述，在半导体基底100上形成一前述的介电结构102，随后通过合适的蚀刻制作工艺，例如一干蚀刻制作工艺，蚀刻介电结构102内的半导体基底100，而在介电结构102内形成至少一凹槽104’。更重要的是，在本变化型中，蚀刻制作工艺可过度蚀刻(over-etching)暴露于介电结构102底部的半导体基底100，是以凹槽104’的底部如图2所示，低于介电结构102的底部。
请参阅图3。在形成凹槽104或104’之后，在凹槽104内形成一外延层110。外延层110可通过SEG方法形成，但不限于此。外延层110包含有前述的第一半导体材料以及一第二半导体材料，在本优选实施例中，第二半导体材料为锗。外延层110的第二半导体材料包含有一第三浓度(即锗浓度)，且第三浓度介于0％-50％。详细地说，外延层110中的第三浓度可由下而上由0％逐渐提升至50％。或者，外延层110中的第三浓度可预定为30％，但此预定浓度可依据不同产品的需求于制作工艺中调整。另外需注意的是，外延层110为一未掺杂(undoped)外延层。也就是说，外延层110内并未包含任何导电掺杂质(conductive dopant)，因此外延层110为本质硅锗(intrinsic SiGe)层。另外，外延层110具有一厚度T3，且厚度T3为凹槽104的深度D的三分之一至二分之一。举例来说，当凹槽104的深度D为100nm时，外延层110的厚度T3为30nm-50nm，但不限于此。
请继续参阅图3。在形成外延层110之后，可直接进行一热处理112，用以降低外延层110内的缺陷(defect)。值得注意的是，在热处理112中，并未有任何气体的加入。
请参阅图4，图4为本发明所提供的半导体结构的制作方法的另一变化型的示意图。在本变化型中，在形成凹槽104之后，可先于凹槽104内形成一薄外延层106，其可利用SEG制作工艺形成，但亦不限于此。值得注意的是，外延层106仅包含第一半导体材料，在本优选实施例中即为硅。如图4所示，在形成外延层106之后，在外延层106上形成外延层110，且外延层106与外延层110可同位(in-situ)形成，但不限于此。在此需注意的是，由于SEG制作工艺中，外延具有沿着原本基材晶格方向生长的特性，因此在本变化型中，可于形成外延层110之前，先通过SEG制作工艺于凹槽104内形成一材料与基底100完全相同的外延层106。是以，外延层106可作为一良好的外延生长种子表面，使得后续形成包含有SiGe的外延层110时，更有利于其生成。
请参阅图5。在形成外延层110之后，在外延层110上直接再形成一外延层120。外延层120可通过SEG方法形成，且外延层120与外延层110可同位形成，但不限于此。外延层120包含有前述的第一半导体材料以及第二半导体材料，即包含SiGe。在外延层120中的第二半导体材料包含有一第二浓度(即锗浓度)，且第二浓度等于或大于前述的第三浓度。另外，外延层120具有一厚度T2，且厚度T2为凹槽104的深度D的十分之一。举例来说，当凹槽104的深度D为100nm时，外延层120的厚度T2为10nm，但不限于此。值得注意的是，外延层120为一包含有导电掺杂质的膜层。此外，该多个导电掺杂质可通过任何合适的制作工艺掺杂进入外延层120，例如共注入(co-implant)制作工艺，但不限于此。更重要的是，外延层120所包含的导电掺杂质与所欲形成的半导体结构的功用相关。详细地说，当最终形成的半导体结构用作一n型晶体管的组成元件时，外延层120所包含的导电掺杂质为p型掺杂质，例如包含硼(B)。而当最终形成的半导体结构用作一p型晶体管的组成元件时，导电掺杂质为n型掺杂质，例如包含磷(P)或砷(As)。也就是说，外延层120为一与最终将获得的半导体元件的导电型态互补(complementary)的膜层。另外，在本优选实施例中，外延层120中的导电掺杂质的浓度小于1E19/cm3，优选介于5E18/cm3～1E19/cm3，但不限于此。
请继续参阅图5。在形成外延层120之后，可直接进行一热处理122，使得掺杂进入外延层120的导电掺杂质得以扩散。值得注意的是，在热处理122中，可加入氢气或氮气。
请参阅图6。在形成外延层120之后，在外延层120上直接再形成一外延层130。外延层130可通过SEG方法形成，且外延层110、外延层120与外延层130可同位形成，但不限于此。外延层130包含有一厚度T1，且厚度T1为凹槽104的深度的三分之一至二分之一。由此可知，外延层120的厚度T2小于外延层110的厚度T3以及外延层130的厚度T1。更重要的是，外延层130如图6所示，填满凹槽104。外延层130包含有前述的第一半导体材料以及第二半导体材料，即包含SiGe。外延层130中的第二半导体材料包含有一第一浓度(即锗浓度)，且第一浓度等于或大于前述的第二浓度。举例来说，外延层130的第一浓度可介于30％～70％，但不限于此。在本发明的一变化型中，外延层130的第二半导体材料的第一浓度甚至可达100％。另外须注意的是，外延层130为一未掺杂(undoped)的膜层。也就是说，外延层130内并未包含任何导电掺杂质，因此外延层130亦为一本质硅锗层。
请参阅图7。在完成所有外延层的制作后，进行一回蚀刻(etching back)制作工艺，用以移除部分介电结构102，使得部分外延层130突出于介电结构102的表面。至此，在半导体基底100上，以及介电材料102之内完成至少一鳍片结构140的制作。详细地说，鳍片结构140包含有未掺杂的外延层110、具有导电掺杂质的外延层120、以及未掺杂的外延层130。当然，如前所述，在本发明所提供的变化型中，鳍片结构140的未掺杂外延层110与基底102之间，可更包含一未掺杂且材料与基底102完全相同的外延层106。如图7所示，在本优选实施例中，鳍片结构140突出于介电结构102的表面102S，且具有一突出高度。一般说来，此一突出高度定义为鳍片高度HFin，在本优选实施例中，鳍片高度HFin介于20nm～50nm，但不限于此。
请参阅图8。接下来，在半导体基底100上，尤其是介电结构102与鳍片结构140上依序形成一栅极介电层152与一栅极导电层154，并通过图案化方法图案化栅极介电层152与栅极导电层154，而于鳍片结构140上形成一栅极层150。如图8所示，栅极层150的延伸方向与鳍片结构140的延伸方向垂直，且栅极层150覆盖部分鳍片结构140的顶部与侧壁。栅极介电层152可包含现有介电材料如氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)等介电材料。而在本优选实施例中，栅极介电层152更可包含高介电常数(high-K)材料，例如氧化铪(HfO)、硅酸铪(HfSiO)或、铝、锆、镧等金属的金属氧化物或金属硅酸盐(metal silicates)等，但不限于此。另外，当本优选实施例的栅极介电层152采用high-K材料时，本发明可与金属栅极(metal gate)制作工艺整合，以提供足以匹配high-K栅极介电层的控制电极。据此，栅极导电层154可配合金属栅极的前栅极(gate-first)制作工艺或后栅极(gate-last)制作工艺采用不同的材料。举例来说，当本优选实施例与前栅极制作工艺整合时，栅极导电层154可包含金属如钽(Ta)、钛(Ti)、钌(Ru)、钼(Mo)、或上述金属的合金如铝钛(TiAl)、金属氮化物如氮化钽(TaN)、氮化钛(TiN)、氮化钼(MoN)等、金属碳化物如碳化钽(TaC)等。且该多个金属的选用以所欲获得的多栅极晶体管元件的导电形式为原则，即以满足n型或p型晶体管所需功函数要求的金属为选用原则。另外，栅极导电层154可为单层结构或复合层(multi-layered)结构。而当本优选实施例与后栅极制作工艺整合时，栅极导电层154作为一虚置栅极(dummy gate)，其可包含半导体材料如多晶硅等。随后，可进行制作鳍式场效晶体管(fin field effect transistor，以下简称为FinFET)元件所需的后续步骤。值得注意的是，由于栅极导电层154的导电型态与所欲形成的晶体管的导电型态相同，因此栅极导电层154的导电型态与外延层120的导电型态互补。
请再次参阅图8。根据本优选实施例所提供的半导体结构，其在半导体基底100上形成一鳍片结构140，且鳍片结构140包含有未掺杂的外延层110、未掺杂的外延层130、以及设置于未掺杂的外延层110与130之间的外延层120，且外延层120包含有导电掺杂质。外延层130作为FinFET元件中通道区域形成之处，因此外延层130中第二半导体材料(本优选实施例为锗)的第一浓度为目标浓度。如前所述，第一浓度可以是30％～70％，甚至是100％，且第一浓度可以是由下而上逐渐增加至目标浓度，但不限于此。换句话说，本优选实施例提供一硅锗通道或锗通道。设置于外延层130与外延层110之间的外延层120中，第二半导体材料的第二浓度等于或小于外延层130中第二半导体材料的第一浓度。更重要的是，外延层120包含有与FinFET元件的导电型态互补的导电掺杂质，是以设置于外延层130(即通道区域形成处)下方的外延层120可作为一抗凿穿层，用以避免FinFET元件在操作时发生凿穿效应。而设置于半导体基底100与外延层120/130之间的外延层110中，第二半导体材料的第三浓度小于外延层120/130中第二半导体材料的第二/第一浓度。也就是说，外延层110中的第二半导体材料的第三浓度介于外延层120/130与半导体基底100之间。因此，外延层110可作为一应变松弛缓冲(strain relaxed buffer，SRB)层。是以，在生成晶格系数不同于半导体基底100的鳍片结构140时，因晶格不匹配(mismatch)而产生的差排缺陷可被限制在此一膜层中。并且，外延层110可提供后续生成的外延层120/130一良好的生长界面，使得后续作为抗凿穿层的外延层120以及作为通道区域形成处的外延层130得以良好且无缺陷的生成。
综上所述，根据本发明所提供的半导体结构及其制作方法，在形成作为主要应力供应者的外延层之前，至少形成包含有导电掺杂质的外延层，且此外延层包含的导电掺杂质与所欲制作的晶体管元件具有互补的导电型态，以作为一抗凿穿层。另外，更通过形成于上述二外延层与半导体基底之间，作为应力松弛缓冲层的另一外延层约束并限制排差缺陷，故可使后续生成的外延层具有无缺陷且良好的成长结果。简单地说，根据本发明所提供的半导体结构及其制作方法，最终形成的晶体管元件除可通过外延层提供的应力提升性能之外，更可通过具有导电掺杂质的外延层有效地防止凿穿效应的发生，并通过未掺杂外延层提供应力松弛缓冲的介面，故可更加提升最终获得的晶体管元件的性能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (22)

1.一种半导体结构，包含有：
半导体基底，包含有一第一半导体材料；以及
至少一鳍片结构(fin)，形成于该半导体基底上，且该鳍片结构包含有：
第一外延层，包含有该第一半导体材料与一第二半导体材料，该第二半导体材料的一晶格常数(lattice constant)不同于该第一半导体材料的一晶格常数；以及
第二外延层，形成于该第一外延层与该半导体基底之间，该第二外延层包含有该第一半导体材料与该第二半导体材料，且该第二外延层包含有导电掺杂质(conductive dopant)。
2.如权利要求1所述的半导体结构，其中该第一外延层内的该第二半导体材料包含有一第一浓度，该第二外延层内的该第二半导体材料包含有一第二浓度，且该第二浓度等于或小于该第一浓度。
3.如权利要求1所述的半导体结构，还包含栅极层，形成于该鳍片结构上，且该栅极层包含第一导电型态。
4.如权利要求3所述的半导体结构，其中该第二外延层内的该导电掺杂质包含有第二导电型态，且该第二导电型态与该第一导电型态彼此互补。
5.如权利要求4所述的半导体结构，其中该第一导电型态为n型，而该导电掺杂质包含硼(B)。
6.如权利要求4所述的半导体结构，其中该第一导电型态为p型，而该岛电掺杂质包含磷(P)或砷(As)。
7.如权利要求1所述的半导体结构，其中该第二外延层内的该导电掺杂质包含有一浓度，且该浓度小于1E19/cm3。
8.如权利要求1所述的半导体结构，其中该鳍片结构还包含第三外延层，该第三外延层包含有该第一半导体材料与该第二半导体材料，且该第二外延层设置于该第一外延层与该第三外延层之间。
9.如权利要求8所述的半导体结构，其中该第一外延层的该第二半导体材料包含一第一浓度，该第二外延层的该第二半导体材料包含一第二浓度，该第三外延层的该第二半导体材料包含一第三浓度，该第二浓度等于或大于该第三浓度，且该第一浓度等于或大于该第二浓度。
10.如权利要求8所述的半导体结构，其中该第二外延层的一厚度小于该第一外延层的一厚度与该第三外延层的一厚度。
11.一种半导体结构的制作方法，包含有：
提供一半导体基底，包含有一第一半导体材料，该半导体基底上形成有一介电结构，且该介电结构内形成有至少一凹槽；
在该凹槽内形成一第二外延层，该第二外延层包含有该第一半导体材料与一第二半导体材料，该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数，且该第二外延层包含有导电掺杂质；
在该第二外延层上形成一第一外延层，该第一外延层包含该第一半导体材料与该第二半导体材料，且该第一外延层为一未掺杂(undoped)外延层；以及
移除部分该介电层，以在该半导体基底上形成一鳍片结构。
12.如权利要求11所述的制作方法，其中该凹槽的底部与该介电结构的底部共平面或低于该介电结构的底部。
13.如权利要求11所述的制作方法，还包含于形成该第二外延层之前形成一第三外延层，该第三外延层为一未掺杂外延层，且该第三外延层包含有该第一半导体材料与该第二半导体材料。
14.如权利要求13所述的制作方法，其中该第一外延层的该第二半导体材料包含有一第一浓度，该第二外延层的该第二半导体材料包含有一第二浓度，该第三外延层的该第二半导体材料包含有一第三浓度。
15.如权利要求13所述的制作方法，其中该第二浓度等于或大于该第三浓度，该第一浓度等于或大于第二浓度。
16.如权利要求13所述的制作方法，其中该凹槽包含有一深度，该第一外延层包含有一第一厚度，且该第一厚度为该凹槽的深度的三分之一至二分之一，该第二外延层包含有一第二厚度，且该第二厚度为该凹槽的深度的十分之一，该第三外延层包含有一第三厚度，且该第三厚度为该凹槽的深度的三分之一至二分之一。
17.如权利要求13所述的制作方法，还包含进行一热处理，进行于形成该第三外延层之后与形成该第二外延层之前。
18.如权利要求13所述的制作方法，还包含于该凹槽内形成一第四外延层，进行于形成该第三外延层之前或形成该第二外延层之前，且该第四外延层包含该第一半导体材料。
19.如权利要求13所述的制作方法，其中该第一外延层、该第二外延层与该第三外延层同位(in-situ)形成。
20.如权利要求11所述的制作方法，还包含于形成该第二外延层之后，进行一热处理。
21.如权利要求11所述的制作方法，还包含于该鳍片结构上形成一栅极层，该栅极层包含有一第一导电型态。
22.如权利要求21所述的制作方法，其中第二外延层的该导电掺杂质包含有一第二导电型态，且该第二导电型态与该第一导电型态彼此互补。
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