US20140353767A1 - Method for the formation of fin structures for finfet devices - Google Patents

Method for the formation of fin structures for finfet devices Download PDF

Info

Publication number
US20140353767A1
US20140353767A1 US13/906,505 US201313906505A US2014353767A1 US 20140353767 A1 US20140353767 A1 US 20140353767A1 US 201313906505 A US201313906505 A US 201313906505A US 2014353767 A1 US2014353767 A1 US 2014353767A1
Authority
US
United States
Prior art keywords
semiconductor material
region
dielectric
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/906,505
Inventor
Qing Liu
Nicolas Loubet
Shom Ponoth
Prasanna Khare
Balasubramanian Pranatharthiharan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
International Business Machines Corp
Original Assignee
STMicroelectronics lnc USA
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA, International Business Machines Corp filed Critical STMicroelectronics lnc USA
Priority to US13/906,505 priority Critical patent/US20140353767A1/en
Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KHARE, PRASANNA, LIU, QING, LOUBET, NICOLAS
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PONOTH, SHOM, PRANATHARTHIHARAN, BALASUBRAMANIAN
Publication of US20140353767A1 publication Critical patent/US20140353767A1/en
Priority to US14/802,407 priority patent/US9437504B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Description

    TECHNICAL FIELD
  • The present invention relates to integrated circuits and, in particular, to a process for the formation of fin structures for use in FinFET-type integrated circuit devices.
    • BACKGROUND
  • The prior art teaches the formation of integrated circuits which utilize one or more FinFET type field effect transistors. The FinFET transistor comprises a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material. The source and drain regions of the transistor are formed in the elongated section on either side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions which are separated from each other by an intermediate gate portion of the transistor gate spanning with a perpendicular orientation over the multiple elongated sections.
  • A FinFET transistor is created from at least one thin portion (referred to as the “fin”) of semiconductor material defining the elongated section which is used to form the channel of the transistor and also its source and drain zones. This fin is typically defined by a mask that is formed on top of a monocrystalline silicon substrate at the position of the fin. The substrate material is then directionally etched where there is no mask, to a determined depth, such that the elongated section defining the fin remains under the mask and is composed of the substrate material.
  • In one prior art implementation, the fin of semiconductor material which is thus obtained, and which comprises the channel of the final transistor, is not electrically insulated from the active portion of the circuit substrate, which itself is also of crystalline semiconductor material. Such a FinFET device suffers from three distinct types of leakage current. A first type of leakage current can circulate between the source and drain of the finFET transistor, via the active portion of the substrate situated below the channel. This first leakage current, internal to each transistor, is not controlled by the potential applied to the transistor gate. A second type of leakage current arises because the channel of the finFET transistor is also in electrical contact with the channels of other transistors of the same conductivity type via the substrate. The second leakage current flows between transistors in the form of an inter-transistor leakage current. A third type of leakage current appears between the channel of each finFET transistor and a lower part of the substrate in response to the substrate being connected to a reference potential.
  • There is a need in the art for a bulk FinFET configuration which suppresses junction leakage between the source and drain.
  • As CMOS process technology continues to scale towards smaller and smaller dimensions, further improvement in transistor performance is needed. Those skilled in the art recognize that the use of silicon-germanium (SiGe) materials for transistor fabrication provide for a significant boost in transistor performance, especially with respect to p-channel field effect transistor devices. Indeed, the art is moving towards the use of SiGe for p-channel devices of many different types. Specific to the use of FinFET devices, those skilled in art recognize a need to form the fin of the p-channel device from a SiGe material in order to reach improved transistor performance levels over prior art Si material only devices.
    • SUMMARY
  • In an embodiment, a method comprises: on a substrate formed of a first semiconductor material and having a first region and a second region, depositing an overlying sacrificial layer formed of a second semiconductor material; forming for the first region a region of first semiconductor material over the sacrificial layer; forming for the second region a region of second semiconductor material over the sacrificial layer; patterning the region of first semiconductor material to define at least one first fin of a FinFET transistor of a first conductivity type; patterning the region of second semiconductor material to define at least one second fin of a FinFET transistor of a second conductivity type; covering each of the first and second fins with a cap and sidewall spacer; selectively removing the sacrificial layer formed of the second semiconductor material to form an opening below each of the first and second fins, each first and second fin being supported by said sidewall spacer; and filling the opening below each of the first and second fins with a dielectric material so as to isolate the first and second fins from the substrate.
  • In an embodiment, an apparatus comprises: a substrate formed of a first semiconductor material and having a first region and a second region; in the first region, a first dielectric pedestal with a trench on opposite sides of the first dielectric pedestal; in the second region, a second dielectric pedestal with a trench on opposite sides of the second dielectric pedestal; in the first region, a first fin of a FinFET transistor of a first conductivity type formed of a first semiconductor material over the first dielectric pedestal and insulated from the substrate by the first dielectric pedestal; and in the second region, a second fin of a FinFET transistor of a second conductivity type formed of a second semiconductor material over the second dielectric pedestal and insulated from the substrate by the second dielectric pedestal.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
  • FIGS. 1-18 illustrate process steps in the formation of fins for a FinFET device on a bulk substrate.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • Reference is now made to FIGS. 1-18 which illustrate the process steps in the formation of fins for a FinFET device on a bulk substrate.
  • FIG. 1 shows a conventional bulk silicon substrate wafer 10.
  • Using an epitaxial process tool, an epitaxial growth process as known in the art is performed to grow a silicon-germanium (SiGe) layer 12 on a silicon substrate 14 of the bulk silicon substrate wafer 10. The thickness of the silicon-germanium (SiGe) layer 12 is about 10 nm to 30 nm. The silicon-germanium (SiGe) layer 12 is a sacrificial layer to be replaced by an insulative dielectric material as will be described in more detail below. Without removing the substrate wafer 10 from the epitaxial process tool, an epitaxial growth process as known in the art is then performed to grow a silicon-carbide (SiC) layer 16 on the silicon-germanium (SiGe) layer 12. The thickness of the silicon-carbide (SiC) layer 16 is about 10 nm to 20 nm. Without removing the substrate wafer 10 from the epitaxial process tool, an epitaxial growth process as known in the art is then performed to grow a silicon (Si) layer 18 on the silicon-carbide (SiC) layer 16. The thickness of the silicon (Si) layer 18 is about 30 nm to 40 nm. The structure resulting from the foregoing epitaxial growth processes is shown in FIG. 2. The stippling in FIG. 2 is provided to differentiate SiGe material from Si material. The silicon-germanium (SiGe) layer 12, silicon-carbide (SiC) layer 16 and silicon (Si) layer 18 may be doped as needed for the integrated circuit application.
  • FIG. 3 shows the deposit of a silicon nitride (SiN) layer 20 over the silicon (Si) layer 18.
  • A lithographic process as known in the art is then used to form an opening 22 in the silicon nitride (SiN) layer 20 which extends down to reach at least the top surface of the silicon (Si) layer 18. The result of the lithographic process is shown in FIG. 4. The opening 22 is associated with a region 24 of the substrate wafer 10 reserved for the formation of p-channel FinFET devices. The region 26 of the substrate wafer 10 is conversely reserved for the formation of n-channel FinFET devices. Thus, the process described and illustrated primarily concerns the formation of CMOS type integrated circuits, although it will be understood that this is not the only application of the described process. In plan view, the opening 22 may take on any desired shape governed by the size and number of p-channel devices to be formed within the region 24.
  • Using an epitaxial process tool, a high pressure directional etch process (such as an RIE process) as known in the art is then performed to remove a portion 28 of the silicon (Si) layer 18 within the region 24 down to the silicon-carbide (SiC) layer 16. In an embodiment, the directional etch may comprise a high pressure HCl etch. The result of the directional etch process is shown in FIG. 5.
  • Without removing the substrate 10 from the epitaxial process tool used for the etch of FIG. 5, an epitaxial growth process as known in the art is then performed to grow a silicon-germanium (SiGe) layer 30 on top of the silicon-carbide (SiC) layer 16 in region 24 to fill the portion 28 of the silicon (Si) layer 18 that was previously removed. The result of the epitaxial growth process is shown in FIG. 6. The stippling in FIG. 6 is provided to differentiate SiGe material from Si material. The thickness of the silicon-germanium (SiGe) layer 30 in region 24 is preferably at least the thickness of the silicon (Si) layer 18 in the adjacent region 26. The silicon nitride (SiN) layer 20 is then removed.
  • A lithographic process as known in the art is then used to define the fins 150 for the FinFET devices. A lithographic mask of silicon nitride (SiN) 32 is applied over the top surface of the silicon-germanium (SiGe) layer 30 in region 24 and the silicon (Si) layer 18 in region 26. The mask is patterned to leave SiN mask material at the desired locations of the fins 150. An etching operation is then performed to open apertures 152 in the silicon-germanium (SiGe) layer 30 in region 24 and in the silicon (Si) layer 18 in region 26 on either side of each fin 150. The apertures 152 further extend through the silicon-carbide (SiC) layer 16 and reach partially into the silicon-germanium (SiGe) layer 12. In a preferred implementation, a portion 34 of the (sacrificial) silicon-germanium (SiGe) layer 12 remains at the bottom of each aperture 152. The result of the etching process is shown in FIG. 7. The fins 150 include fins 150 p for use in forming p-channel transistors in the region 24 and fins 150 n for use in forming n-channel transistors in the region 26. The etching process used to form the fins 150 may, for example, comprise a Cl2 or HBr etch as known in the art and may be performed in multiple etch steps (such as a first etch through to the silicon-carbide (SiC) layer 16 followed by a second etch through the silicon-carbide (SiC) layer 16 and into the silicon-germanium (SiGe) layer 12). Even more particularly, the etching process may utilize a sidewall image transfer (SIT) process such as that described, for example, in U.S. Pat. No. 8,298,954, the disclosure of which is incorporated by reference.
  • Silicon nitride (SiN) is then deposited over the fins 150. The deposited silicon nitride (SiN) is then etched (for example, using an RIE process) to remove the silicon nitride (SiN) at the portion 34 of the (sacrificial) silicon-germanium (SiGe) layer 12 between the fins 150 and thus define trenches 40 between adjacent fins 150. The result of the silicon nitride (SiN) deposit and etch process is shown in FIG. 8. Each fin 150 is now covered by silicon nitride (SiN) in the form of a thick silicon nitride (SiN) cap 36 and thin silicon nitride (SiN) sidewall spacers 38. The thin silicon nitride (SiN) sidewall spacers 38 have a thickness of 3 nm to 10 nm.
  • The trenches 40 are then filled with silicon dioxide (SiO2) 44 and a planarization process (for example, chemical-mechanical polishing (CMP)), is used to flatten the top of the wafer. The polishing process is configured to stop at the silicon nitride (SiN) cap 36. The result of the silicon dioxide (SiO2) deposit and polish process is shown in FIG. 9.
  • Reference is now made to FIG. 10 which illustrates a top view showing the relationship between a gate (PC) pattern and the fins 150. A PC mask in accordance with the PC pattern of FIG. 10 is applied to the wafer of FIG. 9 and an anisotropic etch of the silicon dioxide (SiO2) 44 deposit is performed through the PC mask to open trenches 48 through the silicon dioxide (SiO2) 44 deposit to reach the portion 34 of the silicon-germanium (SiGe) layer 12 which remained at the bottom of each aperture 152 (see, FIG. 7). The anisotropic etch is continued to extend through the silicon-germanium (SiGe) layer 12 and reach partially into the silicon substrate 14. As a result, trenches 48 are formed on opposite sides a pedestal portion 49 defined in the silicon substrate 14.
  • The result of the anisotropic etch is shown in FIG. 11, which illustrates a cross-section taken along lines A-A of FIG. 10. FIG. 9 illustrates the cross-section taken along lines B-B of FIG. 10.
  • A conformal silicon nitride (SiN) deposit is then made within each open trench 48 to cover exposed side surfaces of each fin 150 and the exposed silicon substrate 14 at the bottom of each open trench 48. The result of this deposit is to extend (reference 38′) the thin silicon nitride (SiN) sidewall spacers 38 over the portions of the silicon-germanium (SiGe) layer 12 and silicon substrate 14 exposed by the anisotropic etch performed in connection with FIGS. 10 and 11 to produce open trenches 48. The thin silicon nitride (SiN) sidewall spacers 38 have a thickness of 6 nm to 12 nm and the extensions 38′ have a thickness of 3 nm to 8 nm. The trenches 48 are then filled with silicon dioxide (SiO2) 54 and a planarization process (for example, chemical-mechanical polishing (CMP)), is used to flatten the top of the wafer. The polishing process is configured to stop at the silicon nitride (SiN) cap 36. The result of the conformal silicon nitride (SiN) deposit, silicon dioxide (SiO2) deposit and polish process is shown in FIG. 12 (cross-section again taken along lines A-A of FIG. 10). FIG. 9 illustrates the cross-section taken along lines B-B of FIG. 10.
  • The previously deposited silicon dioxide (SiO2) fills (references 44 and 54) are then recessed to a depth sufficient to expose the silicon-germanium (SiGe) layer 12 at locations away from the trenches 48 which were filled by silicon dioxide (SiO2) 54 (see, FIG. 11). In other words, the silicon-germanium (SiGe) layer 12 is exposed at those locations which were not covered by the thin silicon nitride (SiN) sidewall spacers 38 or extensions 38′. The process to recess is an etching process, for example of a standard dry etch type, to etch SiO2. The etch is a blanket removal. The etchant may comprise SiCoNi which has a uniform etch speed across different (dense or loose) areas.
  • The result of the process to recess the silicon dioxide (SiO2) 44 and 54 is shown in FIG. 13 (cross-section again taken along lines A-A of FIG. 10) and FIG. 14 (cross-section taken this time along lines B-B of FIG. 10). FIG. 14 shows the locations 56 where the process to recess the silicon dioxide (SiO2) 44 and 54 has exposed the underlying silicon-germanium (SiGe) layer 12. Additionally, it will be noted that process to recess the silicon dioxide (SiO2) 44 and 54 does not affect the silicon nitride (SiN) deposits and thus the fins 150 are protected in both FIG. 13 and FIG. 14 by the thin silicon nitride (SiN) sidewall spacers 38 and extensions 38′. The extensions 38′ in FIG. 13 further cover the silicon-germanium (SiGe) layer 12 and silicon (Si) substrate 14.
  • An etch process as known in the art is then performed to selectively remove the sacrificial material of the silicon-germanium (SiGe) layer 12 through the locations 56 where the silicon-germanium (SiGe) layer 12 is exposed. In an embodiment, the etch may comprise an HCl dry etch which is selective to remove SiGe and leave the adjacent Si structures in place. The result of the selective etch process is shown in FIGS. 15 and 16 (which correspond to FIGS. 13 and 14, respectively). As a result of the removal of the sacrificial silicon-germanium (SiGe) layer 12, apertures 60 are formed at the locations previously occupied by the sacrificial silicon-germanium (SiGe) layer 12. Notwithstanding the presence of apertures 60 at and under each fin 150, it will be recognized that each fin 150 continues to be structurally supported by the thin silicon nitride (SiN) sidewall spacers 38 and extensions 38′.
  • The silicon-carbide (SiC) material underneath the silicon-germanium (SiGe) layer 30 in region 24 serves to protect the silicon-germanium (SiGe) portion of the fins 150 p from being etched away along with the sacrificial material of the silicon-germanium (SiGe) layer 12.
  • The apertures 60 under and around each fin 150 and the trenches 62 between fins 150 (FIGS. 15 and 16) are then filled with a dielectric material such as silicon dioxide (SiO2) 64 and a planarization process (for example, chemical-mechanical polishing (CMP)), is used to flatten the top of the wafer. The polishing process is configured to stop at the silicon nitride (SiN) cap 36. The result of the silicon dioxide (SiO2) fill and polish process is shown in FIG. 17.
  • The silicon dioxide (SiO2) 64 fill between the fins 150 is then recessed to a depth no lower than the bottom of the silicon-carbide (SiC) layer 16. The thick silicon nitride (SiN) cap 36 the thin silicon nitride (SiN) sidewall spacers 38 on top of and adjacent to each of the fins 150 are also removed. The result of the recess and removal process is shown in FIG. 18 wherein individual fins 150 are formed. The fins include fins 150 p made of silicon-germanium from silicon-germanium (SiGe) layer 30 (in region 24) on top of silicon-carbide from silicon-carbide (SiC) layer 16 and insulated from the bulk silicon substrate 14 by the dielectric material (silicon dioxide (SiO2) 64) that was filled in place of the sacrificial silicon-germanium material of the layer 12. The fins further include fins 150 n made of silicon from silicon (Si) layer 18 (in region 26) on top of silicon-carbide from silicon-carbide (SiC) layer 16 and insulated from the bulk silicon substrate 14 by the dielectric material (silicon dioxide (SiO2) 64) that was filled in place of the sacrificial silicon-germanium material of the layer 12. The dielectric material under each fin 150 forms a dielectric pedestal region 68 supporting the fin and insulating the fin from the bulk substrate.
  • Conventional semiconductor processing as known in the art may then continue from the fins 150 defined as shown in FIG. 18 to finish fabrication of FinFET devices utilizing the fins 150.
  • The process for fin 150 formation disclosed herein possesses a number of advantages over prior art processes for bulk substrate supported FinFET devices including: a) fin height is determined by an epitaxial growth process which results in more uniformly dimensioned fins in comparison to conventional bulk processing which may rely, for example, on a SiO2 recess to define the fin dimensions; b) the fin 150 n for the n-channel FinFET devices is formed of silicon (from silicon (Si) layer 18) and the fin 150 p for the p-channel FinFET is formed of silicon-germanium (from the silicon-germanium (SiGe) layer 30) which promotes better transistor performance with respect to both conductivity type transistors; c) the source/drain regions of the fins 150 are isolated from the bulk silicon substrate 14 by dielectric material (from the silicon dioxide (SiO2) 64 material used to fill the apertures 60 left by the removal of the sacrificial silicon-germanium (SiGe) layer 12) so as to suppress junction leakage; d) the process technique is well suited for use in aggressively scaled CMOS fabrication techniques at and below the 10 nm process node; and e) the process technique is compatible with both gate first and gate last integration processing for FinFET devices.
  • Although this process is somewhat complex, the process provides a valuable means to produce an Si n-channel FinFET and SiGe p-channel FinFET from a bulk wafer. Bulk wafer fabrication is attractive because of a lower price point. The steps of the method are common to semiconductor fabrication and can be applied with limited cost.
  • The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims (22)

1. A method, comprising:
on a substrate formed of a first semiconductor material and having a first region and a second region, depositing an overlying sacrificial layer formed of a second semiconductor material;
forming for the first region a region of first semiconductor material over the sacrificial layer;
forming for the second region a region of second semiconductor material over the sacrificial layer;
patterning the region of first semiconductor material to define at least one first fin of a FinFET transistor of a first conductivity type;
patterning the region of second semiconductor material to define at least one second fin of a FinFET transistor of a second conductivity type;
covering each of the first and second fins with a cap and sidewall spacer;
selectively removing the sacrificial layer formed of the second semiconductor material to form an opening below each of the first and second fins, each first and second fin being supported by said sidewall spacer; and
filling the opening below each of the first and second fins with a dielectric material so as to isolate the first and second fins from the substrate.
2. The method of claim 1, wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium.
3. The method of claim 2, wherein the FinFET transistor of the first conductivity type formed of the first semiconductor material is an n-channel device and wherein the FinFET transistor of the second conductivity type formed of the second semiconductor material is a p-channel device.
4. The method of claim 1, wherein the substrate is a bulk semiconductor substrate.
5. The method of claim 1, further comprising depositing an intermediate semiconductor material layer between the overlying sacrificial layer and each of the region of first semiconductor material and region of second semiconductor material.
6. The method of claim 5, wherein the intermediate semiconductor material layer is a silicon-carbide layer.
7. The method of claim 5, wherein each first fin comprises first semiconductor material over intermediate semiconductor material over said dielectric material, and each second fin comprises second semiconductor material over intermediate semiconductor material over said dielectric material.
8. The method of claim 1, further comprising removing the cap and sidewall spacer to expose each of said first and second fins.
9. The method of claim 1, wherein selectively removing the sacrificial layer formed of the second semiconductor material further forms openings adjacent each of the first and second fins, and wherein filling further comprises filling the adjacent openings with the dielectric material to separate said fins from each other.
10. The method of claim 1, further comprising defining a trench in the substrate between adjacent fins, and wherein filling further comprises filling the trench with the dielectric material.
11. The method of claim 10, wherein selectively removing the sacrificial layer formed of the second semiconductor material further forms openings adjacent each of the first and second fins, said trench in communication with said adjacent openings, and wherein filling further comprises filling the adjacent openings and trenches with the dielectric material.
12. The method of claim 11, wherein covering further comprises lining each of the trenches with said sidewall spacer.
13. An apparatus, comprising:
a substrate formed of a first semiconductor material and having a first region and a second region;
in the first region, a first dielectric pedestal with a trench on opposite sides of the first dielectric pedestal;
in the second region, a second dielectric pedestal with a trench on opposite sides of the second dielectric pedestal;
in the first region, a first fin of a FinFET transistor of a first conductivity type formed of a first semiconductor material over the first dielectric pedestal and insulated from the substrate by the first dielectric pedestal; and
in the second region, a second fin of a FinFET transistor of a second conductivity type formed of a second semiconductor material over the second dielectric pedestal and insulated from the substrate by the second dielectric pedestal.
14. The apparatus of claim 13, wherein said trenches on opposite sides of the first and second dielectric pedestals further extend into said substrate to define corresponding substrate pedestal regions supporting the dielectric pedestals.
15. The apparatus of claim 14, further comprising a dielectric material at least partially filling each of the trenches on opposite sides of the first and second dielectric pedestals and at least partially filling each of the trenches between the substrate pedestal regions.
16. The apparatus of claim 15, further comprising a liner in said trenches between the substrate pedestal regions and the at least partially filling dielectric material.
17. The apparatus of claim 13, further comprising a dielectric material at least partially filling each of the trenches on opposite sides of the first and second dielectric pedestals and a liner in said trenches between the dielectric pedestals and the at least partially filling dielectric material.
18. The apparatus of claim 13, wherein the substrate is a bulk semiconductor substrate.
19. The apparatus of claim 13, further comprising an intermediate semiconductor material between each of the first and second dielectric pedestals and the first semiconductor material of the first fin and second semiconductor material of the second fin, respectively.
20. The apparatus of claim 19, wherein the intermediate semiconductor material is silicon-carbide.
21. The apparatus of claim 13 wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium.
22. The apparatus of claim 21, wherein the FinFET transistor of the first conductivity type formed of the first semiconductor material is an n-channel device and wherein the FinFET transistor of the second conductivity type formed of the second semiconductor material is a p-channel device.
US13/906,505 2013-05-31 2013-05-31 Method for the formation of fin structures for finfet devices Abandoned US20140353767A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/906,505 US20140353767A1 (en) 2013-05-31 2013-05-31 Method for the formation of fin structures for finfet devices
US14/802,407 US9437504B2 (en) 2013-05-31 2015-07-17 Method for the formation of fin structures for FinFET devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/906,505 US20140353767A1 (en) 2013-05-31 2013-05-31 Method for the formation of fin structures for finfet devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/802,407 Division US9437504B2 (en) 2013-05-31 2015-07-17 Method for the formation of fin structures for FinFET devices

Publications (1)

Publication Number Publication Date
US20140353767A1 true US20140353767A1 (en) 2014-12-04

Family

ID=51984191

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/906,505 Abandoned US20140353767A1 (en) 2013-05-31 2013-05-31 Method for the formation of fin structures for finfet devices
US14/802,407 Active US9437504B2 (en) 2013-05-31 2015-07-17 Method for the formation of fin structures for FinFET devices

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/802,407 Active US9437504B2 (en) 2013-05-31 2015-07-17 Method for the formation of fin structures for FinFET devices

Country Status (1)

Country Link
US (2) US20140353767A1 (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140117419A1 (en) * 2012-10-30 2014-05-01 Globalfoundries Inc. Fin etch and fin replacement for finfet integration
US20150028454A1 (en) * 2013-07-24 2015-01-29 International Business Machines Corporation Finfet structures having silicon germanium and silicon channels
US20150200128A1 (en) * 2014-01-15 2015-07-16 International Business Machines Corporation Methods of forming isolated germanium-containing fins for a finfet semiconductor device
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US9293373B1 (en) * 2015-05-26 2016-03-22 International Business Machines Corporation Method for fabricating CMOS finFETs with dual channel material
US9318392B1 (en) * 2015-06-18 2016-04-19 International Business Machines Corporation Method to form SOI fins on a bulk substrate with suspended anchoring
US9324617B1 (en) 2015-05-18 2016-04-26 Globalfoundries Inc. Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
US9324717B2 (en) * 2013-12-28 2016-04-26 Texas Instruments Incorporated High mobility transistors
US9362361B1 (en) * 2015-05-18 2016-06-07 Globalfoundries Inc. Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
US20160225676A1 (en) * 2015-01-29 2016-08-04 Globalfoundries Inc. Methods of forming fin isolation regions under tensile-strained fins on finfet semiconductor devices
US9418900B1 (en) * 2015-07-15 2016-08-16 International Business Machines Corporation Silicon germanium and silicon fins on oxide from bulk wafer
US20160276348A1 (en) * 2014-04-07 2016-09-22 International Business Machines Corporation Finfet including tunable fin height and tunable fin width ratio
US20160365420A1 (en) * 2015-06-11 2016-12-15 International Business Machines Corporation Self-aligned channel-only semiconductor-on-insulator field effect transistor
US9524969B1 (en) 2015-07-29 2016-12-20 International Business Machines Corporation Integrated circuit having strained fins on bulk substrate
US20160379867A1 (en) * 2014-12-31 2016-12-29 International Business Machines Corporation Silicon germanium-on-insulator finfet
US20170053944A1 (en) * 2014-10-21 2017-02-23 United Microelectronics Corp. Fin-shaped structure
US9614040B1 (en) 2016-02-02 2017-04-04 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
US9620503B1 (en) * 2015-11-16 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US20170117414A1 (en) * 2015-10-26 2017-04-27 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US9773871B2 (en) * 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9799765B1 (en) * 2016-06-29 2017-10-24 International Business Machines Corporation Formation of a bottom source-drain for vertical field-effect transistors
US9818825B2 (en) 2015-10-27 2017-11-14 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9929159B2 (en) * 2016-02-25 2018-03-27 Globalfoundries Inc. Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
DE102016204596B4 (en) 2015-03-31 2018-07-26 International Business Machines Corporation Method of making FinFETs with variable fin height
US20190131177A1 (en) * 2017-10-26 2019-05-02 Globalfoundries Inc. Field-effect transistors with fins having independently-dimensioned sections
US10347752B2 (en) * 2015-08-20 2019-07-09 International Business Machines Corporation Semiconductor structures having increased channel strain using fin release in gate regions
US10366930B1 (en) * 2018-06-11 2019-07-30 Globalfoundries Inc. Self-aligned gate cut isolation
US20200119182A1 (en) * 2015-11-06 2020-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Finfet isolation structure
CN111834299A (en) * 2019-04-16 2020-10-27 中芯国际集成电路制造(上海)有限公司 Double fin structure and forming method thereof
US20210098459A1 (en) * 2017-08-31 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid Scheme for Improved Performance for P-type and N-type FinFETs

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941355B1 (en) * 2017-01-11 2018-04-10 International Business Machines Corporation Co-integration of elastic and plastic relaxation on the same wafer
US10403742B2 (en) 2017-09-22 2019-09-03 Globalfoundries Inc. Field-effect transistors with fins formed by a damascene-like process
WO2019132891A1 (en) * 2017-12-27 2019-07-04 Intel Corporation Transistors with high density channel semiconductor over dielectric material

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090101995A1 (en) * 2006-11-14 2009-04-23 International Business Machines Corporation PROCESS FOR FABRICATION OF FINFETs
US20110227165A1 (en) * 2009-11-09 2011-09-22 International Business Machines Corporation High-k/metal gate cmos finfet with improved pfet threshold voltage
US20130234204A1 (en) * 2012-03-06 2013-09-12 Samsung Electronics Co., Ltd. Fin field effect transistors including multiple lattice constants and methods of fabricating the same
US20130256835A1 (en) * 2012-03-30 2013-10-03 International Business Machines Corporation Non-planar capacitor and method of forming the non-planar capacitor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298954B1 (en) 2011-05-06 2012-10-30 International Business Machines Corporation Sidewall image transfer process employing a cap material layer for a metal nitride layer
KR101849688B1 (en) * 2011-12-20 2018-04-18 인텔 코포레이션 Semiconductor structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090101995A1 (en) * 2006-11-14 2009-04-23 International Business Machines Corporation PROCESS FOR FABRICATION OF FINFETs
US20110227165A1 (en) * 2009-11-09 2011-09-22 International Business Machines Corporation High-k/metal gate cmos finfet with improved pfet threshold voltage
US20130234204A1 (en) * 2012-03-06 2013-09-12 Samsung Electronics Co., Ltd. Fin field effect transistors including multiple lattice constants and methods of fabricating the same
US20130256835A1 (en) * 2012-03-30 2013-10-03 International Business Machines Corporation Non-planar capacitor and method of forming the non-planar capacitor

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9054212B2 (en) * 2012-10-30 2015-06-09 Globalfoundries Inc. Fin etch and Fin replacement for FinFET integration
US20140117419A1 (en) * 2012-10-30 2014-05-01 Globalfoundries Inc. Fin etch and fin replacement for finfet integration
US20150028454A1 (en) * 2013-07-24 2015-01-29 International Business Machines Corporation Finfet structures having silicon germanium and silicon channels
US9093533B2 (en) * 2013-07-24 2015-07-28 International Business Machines Corporation FinFET structures having silicon germanium and silicon channels
US20150214117A1 (en) * 2013-07-24 2015-07-30 International Business Machines Corporation Finfet structures having silicon germanium and silicon channels
US9589848B2 (en) * 2013-07-24 2017-03-07 Globalfoundries Inc. FinFET structures having silicon germanium and silicon channels
US9324717B2 (en) * 2013-12-28 2016-04-26 Texas Instruments Incorporated High mobility transistors
US9805986B2 (en) 2013-12-28 2017-10-31 Texas Instruments Incorporated High mobility transistors
US20150200128A1 (en) * 2014-01-15 2015-07-16 International Business Machines Corporation Methods of forming isolated germanium-containing fins for a finfet semiconductor device
US9117875B2 (en) * 2014-01-15 2015-08-25 Globalfoundries Inc. Methods of forming isolated germanium-containing fins for a FinFET semiconductor device
US20160276348A1 (en) * 2014-04-07 2016-09-22 International Business Machines Corporation Finfet including tunable fin height and tunable fin width ratio
US10276573B2 (en) * 2014-04-07 2019-04-30 International Business Machines Corporation FinFET including tunable fin height and tunable fin width ratio
US10622357B2 (en) 2014-04-07 2020-04-14 International Business Machines Corporation FinFET including tunable fin height and tunable fin width ratio
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US10103175B2 (en) * 2014-10-21 2018-10-16 United Microelectronics Corp. Fin-shaped structure
US20170053944A1 (en) * 2014-10-21 2017-02-23 United Microelectronics Corp. Fin-shaped structure
US9899253B2 (en) * 2014-12-31 2018-02-20 International Business Machines Corporation Fabrication of silicon germanium-on-insulator finFET
US20160379867A1 (en) * 2014-12-31 2016-12-29 International Business Machines Corporation Silicon germanium-on-insulator finfet
US20160225676A1 (en) * 2015-01-29 2016-08-04 Globalfoundries Inc. Methods of forming fin isolation regions under tensile-strained fins on finfet semiconductor devices
US10026659B2 (en) * 2015-01-29 2018-07-17 Globalfoundries Inc. Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices
DE102016204596B4 (en) 2015-03-31 2018-07-26 International Business Machines Corporation Method of making FinFETs with variable fin height
US9324617B1 (en) 2015-05-18 2016-04-26 Globalfoundries Inc. Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
US9362361B1 (en) * 2015-05-18 2016-06-07 Globalfoundries Inc. Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
US9293373B1 (en) * 2015-05-26 2016-03-22 International Business Machines Corporation Method for fabricating CMOS finFETs with dual channel material
US11088264B2 (en) 2015-06-11 2021-08-10 International Business Machines Corporation Self-aligned channel-only semiconductor-on-insulator field effect transistor
US20160365420A1 (en) * 2015-06-11 2016-12-15 International Business Machines Corporation Self-aligned channel-only semiconductor-on-insulator field effect transistor
US9935178B2 (en) * 2015-06-11 2018-04-03 International Business Machines Corporation Self-aligned channel-only semiconductor-on-insulator field effect transistor
US9704950B2 (en) 2015-06-18 2017-07-11 International Business Machines Corporation Method to form SOI fins on a bulk substrate with suspended anchoring
US9318392B1 (en) * 2015-06-18 2016-04-19 International Business Machines Corporation Method to form SOI fins on a bulk substrate with suspended anchoring
US9418900B1 (en) * 2015-07-15 2016-08-16 International Business Machines Corporation Silicon germanium and silicon fins on oxide from bulk wafer
US9627267B2 (en) * 2015-07-29 2017-04-18 International Business Machines Corporation Integrated circuit having strained fins on bulk substrate and method to fabricate same
US9524969B1 (en) 2015-07-29 2016-12-20 International Business Machines Corporation Integrated circuit having strained fins on bulk substrate
US20190237561A1 (en) * 2015-08-20 2019-08-01 International Business Machines Corporation Semiconductor structures having increased channel strain using fin release in gate regions
US10886385B2 (en) * 2015-08-20 2021-01-05 International Business Machines Corporation Semiconductor structures having increased channel strain using fin release in gate regions
US10347752B2 (en) * 2015-08-20 2019-07-09 International Business Machines Corporation Semiconductor structures having increased channel strain using fin release in gate regions
US20170117414A1 (en) * 2015-10-26 2017-04-27 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US10497797B2 (en) * 2015-10-26 2019-12-03 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US9818825B2 (en) 2015-10-27 2017-11-14 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US11637204B2 (en) 2015-11-06 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET isolation structure
US10861977B2 (en) * 2015-11-06 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET isolation structure
US20200119182A1 (en) * 2015-11-06 2020-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Finfet isolation structure
US9620503B1 (en) * 2015-11-16 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9773871B2 (en) * 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9614040B1 (en) 2016-02-02 2017-04-04 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
US10283601B2 (en) 2016-02-02 2019-05-07 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
US10600878B2 (en) 2016-02-02 2020-03-24 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
US10497703B2 (en) * 2016-02-25 2019-12-03 Globalfoundries Inc. Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
US20180175037A1 (en) * 2016-02-25 2018-06-21 Globalfoundries Inc. Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
US9929159B2 (en) * 2016-02-25 2018-03-27 Globalfoundries Inc. Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
US10553716B2 (en) 2016-06-29 2020-02-04 International Business Machines Corporation Formation of a bottom source-drain for vertical field-effect transistors
US9799765B1 (en) * 2016-06-29 2017-10-24 International Business Machines Corporation Formation of a bottom source-drain for vertical field-effect transistors
US20210098459A1 (en) * 2017-08-31 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid Scheme for Improved Performance for P-type and N-type FinFETs
US11495598B2 (en) * 2017-08-31 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid scheme for improved performance for P-type and N-type FinFETs
US12074167B2 (en) * 2017-08-31 2024-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid scheme for improved performance for P-type and N-type FinFETs
US10325811B2 (en) * 2017-10-26 2019-06-18 Globalfoundries Inc. Field-effect transistors with fins having independently-dimensioned sections
US20190131177A1 (en) * 2017-10-26 2019-05-02 Globalfoundries Inc. Field-effect transistors with fins having independently-dimensioned sections
US10366930B1 (en) * 2018-06-11 2019-07-30 Globalfoundries Inc. Self-aligned gate cut isolation
TWI707430B (en) * 2018-06-11 2020-10-11 美商格芯（美國）集成電路科技有限公司 Self-aligned gate cut isolation
CN111834299A (en) * 2019-04-16 2020-10-27 中芯国际集成电路制造(上海)有限公司 Double fin structure and forming method thereof

Also Published As

Publication number Publication date
US9437504B2 (en) 2016-09-06
US20150325487A1 (en) 2015-11-12

Similar Documents

Publication Publication Date Title
US9437504B2 (en) Method for the formation of fin structures for FinFET devices
CN103915501B (en) Finfet With Dielectric Isolation By Silicon-on-nothing And Method Of Fabrication
US9231051B2 (en) Methods of forming spacers on FinFETs and other semiconductor devices
US9331178B2 (en) Method for manufacturing non-planar field effect transistor having a semiconductor fin
US7265005B2 (en) Structure and method for dual-gate FET with SOI substrate
KR101333897B1 (en) Structure and method for fabricating fin devices
US9190497B2 (en) Method for fabricating semiconductor device with loop-shaped fin
US9461174B2 (en) Method for the formation of silicon and silicon-germanium fin structures for FinFET devices
US20140315371A1 (en) Methods of forming isolation regions for bulk finfet semiconductor devices
US9524908B2 (en) Methods of removing portions of fins by preforming a selectively etchable material in the substrate
US10199392B2 (en) FinFET device having a partially dielectric isolated fin structure
US9601381B2 (en) Method for the formation of a finFET device with epitaxially grown source-drain regions having a reduced leakage path
TW201830492A (en) Methods of forming bottom and top source/drain regions on a vertical transistor device
TW201909282A (en) Semiconductor device and method of forming the same
US8927406B2 (en) Dual damascene metal gate
TW201735131A (en) Method of forming fin structure
KR100618904B1 (en) Semiconductor device having finfet and method of forming the same
TW201806158A (en) FinFET device on silicon on insulator and method of forming the same
US9099570B2 (en) Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices
US10008496B1 (en) Method for forming semiconductor device having continuous fin diffusion break
CN110931545A (en) Semiconductor device with a plurality of transistors
TWI707403B (en) Semiconductor device and method for fabricating the same
EP3718962B1 (en) A method for forming a vertical nanowire or nanosheet field-effect transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: STMICROELECTRONICS, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, QING;LOUBET, NICOLAS;KHARE, PRASANNA;REEL/FRAME:030520/0687

Effective date: 20130528

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PONOTH, SHOM;PRANATHARTHIHARAN, BALASUBRAMANIAN;SIGNING DATES FROM 20130526 TO 20130529;REEL/FRAME:030520/0721

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION