CN107154404B - 具有非松弛应变通道的场效应晶体管 - Google Patents

具有非松弛应变通道的场效应晶体管 Download PDF

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CN107154404B
CN107154404B CN201710122879.0A CN201710122879A CN107154404B CN 107154404 B CN107154404 B CN 107154404B CN 201710122879 A CN201710122879 A CN 201710122879A CN 107154404 B CN107154404 B CN 107154404B
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CN107154404A (zh
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K·A·努米
C·奥尔托兰
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GlobalFoundries US Inc
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Abstract

本发明涉及具有非松弛应变通道的场效应晶体管，其用于场效应晶体管的装置结构及使用硅绝缘体衬底的装置层形成此类装置结构的方法。在装置层中形成通道及隔离区。位于栅极结构下方的通道于装置层上形成并在应变下由半导体材料所构成。装置层的一部分位于隔离区与通道之间。装置层的此部分处于比通道的半导体材料中的应变更小的应变下。

Description

具有非松弛应变通道的场效应晶体管
技术领域
本发明大体上是关于集成电路，并且特别的是，关于具有应变通道的场效应晶体管用的装置结构及形成此类装置结构的方法。
背景技术
在微处理器、静态随机存取内存、以及其它类型的数字集成电路中，使用互补式金属氧化物半导体(CMOS)技术。大体上，CMOS技术凭靠互补及对称的p型与n型场效应晶体管(nFET与pFET)对以实施逻辑功能。平面型场效应晶体管包括主动半导体区、界定于主动半导体区中的源极与漏极、以与栅极电极。对栅极电极施加超过特性阈值电压的控制电压时，反转或空乏层通过产生的电场在介于源极与漏极之间的主动半导体区中所界定的通道中形成，而且源极与漏极之间出现载子流动以产生装置输出电流。
上覆半导体绝缘体(SOI)衬底可在CMOS技术中有所帮助。与使用主体硅晶圆建置的场效应晶体管相比较，上覆半导体绝缘体衬底允许以显著更高速度操作，同时改善电隔离并减少电损耗。场效应晶体管的效能可透过使用薄型主动半导体层来改善，其允许场效应晶体管在全空乏状态下操作，对栅极电极施加标准控制电压时，空乏层于此全空乏状态下延展至埋置型氧化物层。
在某些技术节点中，可将不同通道材料用于n型场效应晶体管装置及p型场效应晶体管装置。举例而言，若通道由与硅不同的半导体材料所组成，则可增强p型场效应晶体管的装置效能。举例而言，p型场效应晶体管的通道可由硅锗(SiGe)所组成，其特征在于比硅的空穴迁移率更大的更高空穴载子迁移率。
半导体制作中将浅沟槽隔离(shallow trench isolation；STI)用于隔离邻接的场效应晶体管。浅沟槽隔离是通过蚀刻局限主动半导体区的沟槽并以诸如二氧化硅的电绝缘体填充沟槽所形成。在某些环境下，浅沟槽隔离可能使p型场效应晶体管的SiGe通道中存在的应变令人不希望地松弛。
需要具有应变通道的场效应晶体管用的改良型装置结构及形成此类装置结构的方法。
发明内容
在本发明的一具体实施例中，提供一种用于使用硅绝缘体衬底(silicon-on-insulator substrate)的装置层形成装置结构的方法。在装置层中形成通道及隔离区。位于栅极结构下方的通道于装置层上形成并在应变下由半导体材料所构成。装置层的一部分位于隔离区与通道之间。装置层的此部分处于比通道的半导体材料中的应变更小的应变下。
在本发明的一具体实施例中，提供一种使用硅绝缘体衬底的装置层形成的装置结构。装置结构包括位在该装置层上的栅极结构、位在该装置层中的通道、以及位在该装置层中的隔离区。通道位于该栅极结构中，并且该通道由半导体材料在应变下所构成。装置层的一部分位于隔离区与通道之间。装置层的此部分处于比通道的半导体材料中的应变更小的应变下。
附图说明
附图是合并于本说明书的一部分并构成该部分，绘示本发明的各项具体实施例，并且连同上述对本发明的一般性说明、及下文对具体实施例提供的详细说明，目的是为了阐释本发明的具体实施例。
图1至图5是衬底的一部分的截面图，其根据本发明的一具体实施例绘示形成装置结构的制作程序的接连阶段。
图6是示意性俯视图，其中为求清楚说明而展示栅极堆叠、装置层的已处理部分、沟槽隔离区、以及在该已处理部分中提供应变保存性的装置层的部分。
主要组件符号说明
10 上覆半导体绝缘体(SOI)衬底
12 装置层
14 埋置型氧化物(BOX)层
16 处理晶圆
18 硬掩模层
20 开口
22 外延半导体层
23 氧化残留物
24 已处理部分
25、40、42 部分
26 蚀刻掩模
28、30、32、34 沟槽
36、38 侧壁
44、46、48、70 隔离区
50、52 装置区
51、53 场效应晶体管
54、55 栅极结构
56 非导电性间隔物
60、62、64、66 源极/漏极区
68 通道
72 纵轴
d1 尺寸
d2 长度。
具体实施方式
请参阅图1，并且根据本发明的一具体实施例，上覆半导体绝缘体(SOI)衬底10包括装置层12、由硅的氧化物(例如：SiO2)所构成形式为埋置型氧化物(buried oxide；BOX)层14的埋置型介电层、以及处理晶圆(handle wafer)16。装置层12通过中介BOX层14而与处理晶圆16分开，并且比处理晶圆16薄很多。在一项具体实施例中，装置层12可具备可用于制造全空乏SOI装置(fully-depleted SOI device；FDSOI)的极薄上覆半导体绝缘体(extremely thin semiconductor on insulator；ETSOI)衬底的特性而极薄(即2nm至15nm的厚度)。装置层12与处理晶圆16可由诸如单晶硅的单晶半导体材料所构成。BOX层14具有沿着接口与处理晶圆16直接接触的表面、及沿着接口与装置层12直接接触的另一表面，而且这些表面通过延展至SOI衬底10的边沿的BOX层14的厚度来分开。装置层12通过BOX层14与处理晶圆16电隔离。
硬掩模层18位于装置层12的顶端表面上。硬掩模层18可由介电材料所组成，诸如通过化学气相沉积所沉积的氮化硅(Si3N4)。选择构成硬掩模层18的介电材料以提供相对于构成装置层12的半导体材料的蚀刻选择性。使用蚀刻掩模及蚀刻程序图案化硬掩模层18以形成开口20，其穿过硬掩模层18延展至装置层12的顶端表面。
在硬掩模层18中的开口20内侧的一部分装置层12上、以及在装置层12的顶端表面上形成外延(epitaxial)半导体层22。在一具体实施例中，外延半导体层22可含有锗，并且特别的是，可由化学气相沉积(CVD)所沉积并具有范围自2％至50％的锗浓度(即锗含量与锗及硅含量的比率)的硅锗(SiGe)所构成。外延半导体层22可使用外延生长程序来形成。外延生长是一种藉以在装置层12的单晶半导体材料上沉积外延半导体层22的单晶半导体材料的程序，而且其中装置层12的单晶材料的晶向及晶体结构于外延半导体层22的半导体材料中重现。外延半导体层22可通过选择性外延生长程序来形成，其中成分半导体材料就半导体表面上的外延生长而集结，但未就起自绝缘体表面(诸如硬掩模层18的顶端表面)的外延生长而集结。
请参阅图2，其中相似的参考组件符号是指图1中及后续制作阶段时相似的特征，热程序用于令锗原子自外延半导体层22(图1)传送(例如：扩散)到名义上与开口20的区域重合的装置层12的一部分24内。装置层12的已处理部分24自装置层12的顶端表面延展至BOX层14，并且与BOX层14直接接触。换句话说，装置层12的整个厚度通过热程序在与外延半导体层22接触的区段上方局部改质而形成与装置层12的围绕的未处理区段具有不同组成的已处理部分。有差异的组成在装置层12的已处理部分24内付与应变，其在一项具体实施例中可以是压缩应变。
在一具体实施例中，热程序可包含热缩合作用(thermal condensation)，其涉及湿式热氧化程序或干式热氧化程序。在氧化作用期间，锗原子随着外延半导体层22起于其顶端表面朝与装置层12的部分24介接处跨布其厚度氧化而不可逆地自外延半导体层22传送到装置层12内。就其它因素而言，热缩合作用基于各具有钻石晶格结构的锗及硅、以及介于锗与硅之间关于氧的不同化学亲和性。
在一具体实施例中，热缩合作用可在含有至少一种含氧气体的氧化环境中通过干式氧化程序来进行(例如：在范围例如自850℃至1250℃的衬底温度下使用氧当作氧化气体的干式氧化作用)。热程序可涉及热氧化作用(thermal oxidation)与退火的交替周期。硬掩模层18具不透氧性，防止装置层12的受包覆部分起氧化作用。热缩合作用的最终结果是，外延半导体层22转换成空无锗的氧化残留物23，并且接收锗的装置层12的已处理部分24转换成保留初始半导体材料的单晶状态的锗充实半导体材料，装置层12由此初始半导体材料所组成。BOX层14拒绝锗的扩散，使得偏离外延半导体层22的锗完全位于装置层12的已处理部分24中。
就其它因素，装置层12的已处理部分24中的锗浓度取决于装置层12的厚度与组成、以及外延半导体层22的锗含量及厚度。在一具体实施例中，装置层12的已处理部分24初始可由硅所组成，并且可通过热程序转换成所具锗浓度范围自2％至50％的硅锗。装置层12的已处理部分24可通过将锗引进其组成来增加厚度。在氧化作用之后，可使用非氧化性气氛(例如：干氮)中的附加热退火，在导致均质化但不造成应变松弛的条件下，使装置层12的已处理部分24中的锗分布均质化。
装置层12的已处理部分24可因为其引进锗所诱发的晶体结构改变而将压缩应变加入。锗原子位于构成具有已改质组成的装置层12的半导体材料的晶体结构中的晶格位置，并且具有比例如硅原子更大的原子尺寸。大体上，硅锗比硅具有稍微更大的晶格常数。与装置层12的围绕的未处理部分接触时，强迫已处理部分24的晶格结构符合装置层12的围绕的半导体材料的晶格结构，其中产生引入装置层12的已处理部分24的压缩应变。增加已处理部分24的锗含量会使所加入压缩应变的量增加。
热程序之后，因热程序而空无锗的组成的外延半导体层22的氧化残留物23，举例而言，可使用稀氢氟酸(dilute hydrofluoric acid；HF)例如通过蚀刻来选择性移除。随后，硬掩模层18可举例而言，使用化学机械研磨(CMP)或化学蚀刻自装置层12的顶端表面移除。藉此曝露装置层12的顶端表面以进行进一步处理。
请参阅图3，其中相似的参考组件符号是指图2中及后续制作阶段时相似的特征，蚀刻掩模26形成于装置层12的顶端表面上。蚀刻掩模26可由诸如有机光阻的一层光敏材料所构成，该光敏材料可予以通过旋转涂布程序涂敷成流体、预烘培、曝露至透过光掩模投射的光、曝光后烘焙，然后利用化学显影剂显影。蚀刻掩模26的图案化界定与后续沟槽的位置重合的开口，该等沟槽用于形成隔离区并且藉此就不同类型的场效应晶体管界定装置区。
沟槽28、30、32可通过干蚀刻程序在构成装置层12的半导体材料中形成，并且位于蚀刻掩模26中开口的各别位置。沟槽28、30、32深达BOX层14的顶端表面。换句话说，沟槽28、30、32伸透装置层12的整个厚度连至BOX层14的顶端表面。
蚀刻掩模26的一部分25具有比装置层12的已处理部分24的长度d2更大的尺寸d1，并且相对于装置层12的已处理部分24对准，使得形成沟槽28、30、32时，装置层12的已处理部分24受保护并保留。蚀刻掩模26的部分25的尺寸d1大于早先用以形成装置层12的已处理部分24的硬掩模层18中开口20的对应尺寸。
沟槽28的侧壁36与蚀刻掩模26的部分25的侧壁对准。沟槽30的侧壁38与蚀刻掩模26的部分25的对立侧壁对准。沟槽28、30两者隔开，使得装置层12的一部分40位于沟槽34的侧壁36与装置层12的已处理部分24之间，并且装置层12的一部分42位于沟槽28的侧壁38与装置层12的已处理部分24之间。装置层12的部分40、42与装置层12的已处理部24并列(且共同延展)。装置层12的部分40、42作用在于促进保存形成沟槽28、30、32之后加入装置层12的已处理部分24的压缩应变。
请参阅图4，其中相似的参考组件符号是指图3中及后续制作阶段时相似的特征，可通过沉积电绝缘体填充沟槽，然后使用例如化学机械研磨相对于装置层12的顶端表面平坦化电绝缘体，在沟槽28、30、32中形成隔离区44、46、48。包含隔离区44、46、48的电绝缘体可以是通过化学气相沉积所沉积的硅的氧化物(例如：二氧化硅)。在一具体实施例中，包含隔离区44、46、48的电绝缘体可以是利用臭氧与四乙基正硅酸盐(TEOS)当作反应剂气体进行次大气压化学气相沉积所沉积的高外观比程序(high-aspect-ratio process；HARP)氧化物膜。
装置区50界定于隔离区44与隔离区46之间，并且包括装置层12的部分40、42及装置层12的已处理部分24。装置层12的部分40、42分别与隔离区44、46并列(且共同延展)、与装置层12的已处理部分24并列(且共同延展)、以及可以无应变。装置区50可用于建构p型场效应晶体管。
装置区52是通过位于隔离区46与隔离区48之间的装置层12的一部分所界定。装置区52可用于建构n型场效应晶体管。
请参阅图5及6，其中相似的参考组件符号是指第4图中及后续制作阶段时相似的特征，场效应晶体管51、53可在前段(front end of line；FEOL)处理期间，通过互补式金属氧化物半导体(CMOS)程序，使用各别装置区50、52(图4)来制作。场效应晶体管51、53分别包括由栅极介电质与栅极电极所组成的栅极结构54、55。栅极电极可由金属、硅化物、多结晶硅(多晶硅)、或这些材料的组合，通过物理气相沉积(PVD)、化学气相等沉积所构成。栅极介电质可由诸如二氧化硅、氮氧化硅、例如氧化铪或氮氧化铪的高k介电材料等介电或绝缘材料，通过化学气相沉积、原子层沉积(ALD)等沉积所构成。栅极介电质与栅极电极可使用光刻及蚀刻程序通过图案化其成分材料的层堆叠来形成。非导电性间隔物56可在栅极结构54、55的侧壁上形成。
场效应晶体管51包括位于其栅极结构54侧翼的隆起的源极/漏极区60、62，而场效应晶体管53同样地包括位于其栅极结构54侧翼的隆起的源极/漏极区64、66。外延生长程序可用于沉积诸如硅、硅锗(SiGe)、或碳掺杂硅的半导体材料以形成隆起的源极/漏极区60、62、64、66，并且可在沉积期间包括原位掺杂以付与导电性类型。如图所示，源极/漏极区60、62、64、66可具有突起形状，或可替代地具有钉扎型形状。栅极结构54、55的作用可在于自对准隆起的源极/漏极区60、62、64、66的外延半导体材料。隆起的源极/漏极区60、62的半导体材料可包含选自于周期表第III族的p型掺质(例如：硼(B))，其有效付与p型导电性。隆起的源极/漏极区64、66的半导体材料可包含出自周期表第V族的n型掺质(例如：磷(P)或砷(As))，其有效付与n型导电性。“源极/漏极区”一词于本文中使用时，意为可作用为场效应晶体管51、53的源极或漏极的半导体材料的掺杂区。
场效应晶体管53的通道68(位于其隆起的源极/漏极区64、66之间且位于其栅极结构54下方)由出自装置层12的半导体材料所构成。场效应晶体管51的通道(位于其隆起的源极/漏极区60、62之间且位于其栅极结构54下方)由装置层12的已处理部分24的半导体材料所构成。
栅极结构54以给定电压偏压时，对通道施加电场以在其通道变为导通的“接通(ON)”状态与“断开(OFF)”状态之间切换场效应晶体管51。在“接通”状态中，电荷载子(charge carriers_在通道中从充当场效应晶体管51的源极的源极/漏极区60、62其中一者流动至充当场效应晶体管51的漏极的源极/漏极区60、62其中另一者。在“断开”状态中，通道可视为全空乏，因为场效应晶体管51的通道部分的整个高度实质没有电荷载子，若装置层12的厚度极薄则可特别观测到此现象。类似考虑适用于场效应晶体管53。
包含场效应晶体管51的通道的装置层12的已处理部分24的锗充实组成可起改善场效应晶体管51的效能的作用，其特征可为p型场效应晶体管。特别的是，装置层12的已处理部分24的锗增强型组成强化操作期间的空穴载子迁移率。因为装置层12的已处理部分24于装置层12的整个厚度自栅极结构64的底端表面延展至BOX层14的顶端表面，全空乏通道的整体可加入增强载子迁移率的应变。
隔离区44、46及含有隔离区44、46的沟槽28、30的位置通过蚀刻掩模26中的开口来初始选择及实施，使得隔离区44、46的形成未与装置层12的已处理部分24交会。所以，加入界定场效应晶体管51的通道的装置层12的已处理部分24并顺着横切于栅极结构64的纵轴72的方向的应变并未松弛，意为空穴载子迁移率的增强性并未因形成隔离区44、46而降低。将装置层12的已处理部分24与隔离区44、46及内有隔离区44、46驻留的沟槽28、30分开的装置层12的部分40、42促进保存其通过热程序(例如：缩合作用)形成时加入装置层12的已处理部分24的压缩应变。
场效应晶体管51的通道中保留的压缩应变于场效应晶体管51的通道长度受到引导，其横切于栅极结构64的纵轴72(即穿过栅极结构64的中心延展的线条)。在与栅极结构64的纵轴平行的宽度维度中，隔离区70与装置层12的已处理部分24相连并毗连(即触及或接触)。用于形成这些隔离区70的沟槽穿透装置层12的已处理部分24。结果是，平行于栅极结构64的长轴而受到引导的压缩应变的分量得以松弛，以使得装置层12的已处理部分24顺着横切于此纵轴的方向受到单轴应变，并未受到双轴应变。
在场效应晶体管51为n型场效应晶体管的一替代具体实施例中，装置层12的已处理部分24可置放于拉伸应力下，其提升n型场效应晶体管的通道中的电子载子迁移率。为达此目的，可选择外延半导体层22的组成以提供热处理后受到拉伸应变的已处理部分24(通道)。举例而言，外延半导体层22可由掺有碳的硅(Si:C)所组成，诸如碳(C)的比硅更小的原子可自外延半导体层22转移到装置层12的已处理部分24内。
本方法如以上所述，系用于制作集成电路芯片。产生的集成电路芯片可由制作商以空白晶圆形式(例如：作为具有多个未封装芯片的单一晶圆)、当作裸晶粒、或以封装形式来配送。在后例中，芯片嵌装于单芯片封装(例如：塑料载体，有导线黏贴至主板或其它更高层阶载体)中、或多芯片封装(例如：具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。无论如何，芯片可与其它芯片、离散电路组件、及/或其它信号处理装置整合，作为中间产品或或最终产品的部分。
本文中对“垂直”、“水平”等用语的参照属于举例，并非限制，用来建立参考架构。“水平”一词于本文中使用时，定义为与半导体衬底的习知平面平行的平面，与其实际三维空间方位无关。“垂直”与“正交”等词是指垂直于水平的方向，如刚才的定义。“横向”一词是指水平平面内的维度。诸如“上面”及“下面”等词用于指出组件或结构彼此的相对位置，与相对高度截然不同。
一特征可连至或与另一组件进行“连接”或“耦合”，其可直接连接或耦合至其它组件，或取而代之，可存在一或多个中介组件。如无中介组件，一特征可“直接连接”或“直接耦合”至另一组件。如有至少一个中介组件，一特征可“间接连接”或“间接耦合”至另一组件。
本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对于所属技术领域中具有通常知识者将会显而易知，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让所属技术领域中具有通常知识者能够理解本文中所揭示的具体实施例而选择。

Claims (20)

1.一种使用硅绝缘体衬底的装置层形成的装置结构，该装置结构包含：
位在该装置层上的栅极结构；
位在该装置层中的通道，该通道位于该栅极结构下方，并且该通道由半导体材料在第一应变下所构成；以及
位在该装置层中的第一隔离区，
其中，该装置层的第一部分位于该第一隔离区与该通道之间，该通道于该装置层的整个厚度自该栅极结构延展至该硅绝缘体衬底的埋置型氧化物层，并且该装置层的该第一部分处于比该通道的该半导体材料中的该第一应变更小的第二应变下。
2.如权利要求1所述的装置结构，其中，该装置层的该第一部分与该通道并列，并且该装置层的该第一部分与该第一隔离区并列。
3.如权利要求1所述的装置结构，其更包含：
位在该装置层中的第二隔离区；以及
该装置层的第二部分，位于该第二隔离区与该通道之间，
其中，该装置层的该第二部分处于比该通道的该半导体材料中的该第一应变更小的第三应变下。
4.如权利要求1所述的装置结构，其中，该装置层的该部分由半导体材料所组成，该通道的该半导体材料与该装置层的该部分的该半导体材料具有不同的组成，并且该通道的该半导体材料自该装置层的顶端表面延展至该埋置型氧化物层。
5.如权利要求4所述的装置结构，其中，该装置层具有范围自2nm至15nm的厚度。
6.如权利要求4所述的装置结构，其中，该通道的该半导体材料由硅锗所构成，而该装置层的该第一部分的该半导体材料由硅所构成。
7.如权利要求1所述的装置结构，其中，该栅极结构具有横切于该栅极结构的纵轴的长度，并且该通道的该半导体材料中的该第一应变是在平行于该长度的该通道中受到引导。
8.如权利要求7所述的装置结构，其中，该通道具有平行于该栅极结构的该纵轴的宽度，并且更包含：
位在该装置层中的第二隔离区，该第二隔离区配置成顺着该宽度的方向接触该通道。
9.如权利要求1所述的装置结构，其更包含：
与该通道耦合的源极；以及
与该通道耦合的漏极，
其中，该通道的该半导体材料中的该第一应变于该源极与该漏极之间受到引导。
10.如权利要求1所述的装置结构，其中，该装置层的该第一部分无应变，并且该通道的该半导体材料中的该第一应变是压缩应变。
11.一种使用硅绝缘体衬底的装置层形成装置结构的方法，该方法包含：
形成位在该装置层中的通道；
形成位在该装置层中的第一隔离区，使得该装置层的第一部分介于该第一隔离区与该通道之间；以及
形成位在该装置层上的栅极结构；
其中，该通道位于该栅极结构下方并且是在第一应变下由半导体材料所构成，该通道于该装置层的整个厚度自该栅极结构延展至该硅绝缘体衬底的埋置型氧化物层，并且该装置层的该第一部分处于比该通道的该半导体材料中的该第一应变更小的第二应变下。
12.如权利要求11所述的方法，其中，形成位在该装置层中的该通道包含：
形成具有延展至该装置层的开口的硬掩模；
在该开口内侧的该装置层上沉积外延半导体层；以及
将一组件的原子自该外延半导体层传送到该装置层内，
其中，该外延半导体层与该装置层具有不同组成。
13.如权利要求12所述的方法，其中，该外延半导体层的该组成包含硅锗，而将该组件的该原子自该外延半导体层传送到该装置层的该部分内包含：
进行热程序以将锗原子自该外延半导体层传送到该装置层内。
14.如权利要求13所述的方法，其中，该热程序是热缩合作用，其中，该外延半导体层的该硅锗随着该锗自该外延半导体层传送到该装置层内而通过热氧化作用转换成硅的氧化物。
15.如权利要求11所述的方法，其更包含：
形成位在该装置层中的第二隔离区，使得该装置层的第二部分位于该第二隔离区与该通道之间，
其中，该装置层的该第二部分处于比该通道的该半导体材料中的该第一应变更小的第三应变下。
16.如权利要求11所述的方法，其中，该装置层的该部分由半导体材料所组成，该通道的该半导体材料与该装置层的该部分的该半导体材料具有不同的组成，并且该通道的该半导体材料自该装置层的顶端表面延展至该埋置型氧化物层。
17.如权利要求11所述的方法，其中，该栅极结构具有横切于该栅极结构的纵轴的长度，并且该通道的该半导体材料中的该第一应变是在平行于该长度的该通道中受到引导。
18.如权利要求17所述的方法，其中，该通道具有平行于该栅极结构的该纵轴的宽度，并且更包含：
形成位在该装置层中的第二隔离区，
其中，该第二隔离区配置成顺着该宽度的方向接触该通道。
19.如权利要求11所述的方法，其更包含：
形成与该通道耦合的源极；以及
形成与该通道耦合的漏极，
其中，该通道的该半导体材料中的该第一应变于该源极与该漏极之间受到引导。
20.如权利要求11所述的方法，其中，该装置层的该第一部分无应变，并且该通道的该半导体材料中的该第一应变是压缩应变。
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