TWI637509B - 使用絕緣體上覆矽基板的裝置層的裝置結構及其形成方法 - Google Patents

使用絕緣體上覆矽基板的裝置層的裝置結構及其形成方法 Download PDF

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TWI637509B
TWI637509B TW106105912A TW106105912A TWI637509B TW I637509 B TWI637509 B TW I637509B TW 106105912 A TW106105912 A TW 106105912A TW 106105912 A TW106105912 A TW 106105912A TW I637509 B TWI637509 B TW I637509B
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semiconductor material
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卡瑞恩Ａ 奈米
克拉德 歐特拉德
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格羅方德半導體公司
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Abstract

本發明關於用於場效電晶體的裝置結構及使用絕緣體上覆矽基板的裝置層形成此類裝置結構的方法。在裝置層中形成通道及隔離區。位於閘極結構下方的通道於裝置層上形成並在應變下由半導體材料所構成。裝置層的一部分位於第一隔離區與通道之間。裝置層的此部分處於比通道的半導體材料中的應變更小的應變下。

Description

使用絕緣體上覆矽基板的裝置層的裝置結構及其形成方法
本發明大體上是關於積體電路，並且特別的是，關於具有應變通道的場效電晶體用的裝置結構及形成此類裝置結構的方法。
在微處理器、靜態隨機存取記憶體、以及其它類型的數位積體電路中，使用互補式金屬氧化物半導體(CMOS)技術。大體上，CMOS技術憑靠互補及對稱的p型與n型場效電晶體(nFET與pFET)對以實施邏輯功能。平面型場效電晶體包括主動半導體區、界定於主動半導體區中的源極與汲極、以與閘極電極。對閘極電極施加超過特性臨界電壓的控制電壓時，反轉或空乏層通過產生的電場在介於源極與汲極之間的主動半導體區中所界定的通道中形成，而且源極與汲極之間出現載子流動以產生裝置輸出電流。
絕緣體上覆半導體(semiconductor-on-insulator；SOI)基板可在CMOS技術中有所幫助。與使用主體矽晶圓建置的場效電晶體相比較，絕緣體上覆半導體基 板允許以顯著更高速度操作，同時改善電隔離並減少電損耗。場效電晶體的效能可透過使用薄型主動半導體層來改善，其允許場效電晶體在全空乏狀態下操作，對閘極電極施加標準控制電壓時，空乏層於此全空乏狀態下延展至埋置型氧化物層。
在某些技術節點中，可將不同通道材料用於n型場效電晶體裝置及p型場效電晶體裝置。舉例而言，若通道由與矽不同的半導體材料所組成，則可增強p型場效電晶體的裝置效能。舉例而言，p型場效電晶體的通道可由矽鍺(SiGe)所組成，其特徵在於比矽的電洞遷移率更大的更高電洞載子遷移率。
半導體製作中將淺溝槽隔離(shallow trench isolation；STI)用於隔離鄰接的場效電晶體。淺溝槽隔離是通過蝕刻局限主動半導體區的溝槽，並以諸如二氧化矽的電絕緣體填充溝槽所形成。在某些環境下，淺溝槽隔離可能使p型場效電晶體的SiGe通道中存在的應變令人不希望地鬆弛。
需要具有應變通道的場效電晶體用的改良型裝置結構及形成此類裝置結構的方法。
在本發明的一具體實施例中，提供一種用於使用絕緣體上覆矽基板(silicon-on-insulator substrate)的裝置層形成裝置結構的方法。在裝置層中形成通道及隔離區。位於閘極結構下方的通道於裝置層上形成並在應變下 由半導體材料所構成。裝置層的一部分位於隔離區與通道之間。裝置層的此部分處於比通道的半導體材料中的應變更小的應變下。
在本發明的一具體實施例中，提供一種使用絕緣體上覆矽基板的裝置層形成的裝置結構。裝置結構包括位在該裝置層上的閘極結構、位在該裝置層中的通道、以及位在該裝置層中的隔離區。通道位於該閘極結構中，並且該通道由半導體材料在應變下所構成。裝置層的一部分位於隔離區與通道之間。裝置層的此部分處於比通道的半導體材料中的應變更小的應變下。
10‧‧‧絕緣體上覆半導體(SOI)基板
12‧‧‧裝置層
14‧‧‧埋置型氧化物(BOX)層
16‧‧‧處理晶圓
18‧‧‧硬遮罩層
20‧‧‧開口
22‧‧‧磊晶半導體層
23‧‧‧氧化殘留物
24‧‧‧部分或已處理部分
25、40、42‧‧‧部分
26‧‧‧蝕刻遮罩
28、30、32、34‧‧‧溝槽
36、38‧‧‧側壁
44、46、48、70‧‧‧隔離區
50、52‧‧‧裝置區
51、53‧‧‧場效電晶體
54、55‧‧‧閘極結構
56‧‧‧非導電性間隔物
60、62、64、66‧‧‧源極/汲極區
68‧‧‧通道
72‧‧‧縱軸
d1‧‧‧尺寸
d2‧‧‧長度
附圖是合併於本說明書的一部分並構成該部分，繪示本發明的各項具體實施例，並且連同上述對本發明的一般性說明、及下文對具體實施例提供的詳細說明，目的是為了闡釋本發明的具體實施例。
第1圖至第5圖是基板的一部分的截面圖，其根據本發明的一具體實施例繪示形成裝置結構的製作程序的接連階段。
第6圖是示意性俯視圖，其中為求清楚說明而展示閘極堆疊、裝置層的已處理部分、溝槽隔離區、以及在該已處理部分中提供應變保存性的裝置層的部分。
請參閱第1圖，並且根據本發明的一具體實施例，絕緣體上覆半導體(SOI)基板10包括裝置層12、由 矽的氧化物(例如：SiO2)所構成形式為埋置型氧化物(buried oxide；BOX)層14的埋置型介電層、以及處理晶圓(handle wafer)16。裝置層12通過中介的BOX層14而與處理晶圓16分開，並且比處理晶圓16薄很多。在一項具體實施例中，裝置層12可具備可用於製造全空乏SOI裝置(fully-depleted SOI device；FDSOI)的極薄絕緣體上覆半導體(extremely thin semiconductor on insulator；ETSOI)基板的特性而極薄(即2nm至15nm的厚度)。裝置層12與處理晶圓16可由諸如單晶矽的單晶半導體材料所構成。BOX層14具有沿著介面與處理晶圓16直接接觸的表面、及沿著介面與裝置層12直接接觸的另一表面，而且這些表面通過延展至SOI基板10的邊沿的BOX層14的厚度來分開。裝置層12通過BOX層14與處理晶圓16電隔離。
硬遮罩層18位於裝置層12的頂端表面上。硬遮罩層18可由介電材料所組成，諸如通過化學氣相沉積所沉積的氮化矽(Si3N4)。選擇構成硬遮罩層18的介電材料以提供相對於構成裝置層12的半導體材料的蝕刻選擇性。使用蝕刻遮罩及蝕刻程序圖案化硬遮罩層18以形成開口20，其穿過硬遮罩層18延展至裝置層12的頂端表面。
在硬遮罩層18中的開口20內側的一部分裝置層12上、以及在裝置層12的頂端表面上形成磊晶(epitaxial)半導體層22。在一具體實施例中，磊晶半導體層22可含有鍺，並且特別的是，可由化學氣相沉積(CVD)所沉積並具有範圍自2%至50%的鍺濃度(即鍺含量與鍺及矽 含量的比率)的矽鍺(SiGe)所構成。磊晶半導體層22可使用磊晶生長程序來形成。磊晶生長是一種藉以在裝置層12的單晶半導體材料上沉積磊晶半導體層22的單晶半導體材料的程序，而且其中裝置層12的單晶材料的晶向及晶體結構於磊晶半導體層22的半導體材料中重現。磊晶半導體層22可通過選擇性磊晶生長程序來形成，其中成分半導體材料就半導體表面上的磊晶生長而集結，但未就起自絕緣體表面(諸如硬遮罩層18的頂端表面)的磊晶生長而集結。
請參閱第2圖，其中相似的參考元件符號是指第1圖中及後續製作階段時相似的特徵，熱程序用於令鍺原子自磊晶半導體層22(第1圖)傳送(例如：擴散)到名義上與開口20的區域重合的裝置層12的一部分24內。裝置層12的已處理部分24自裝置層12的頂端表面延展至BOX層14，並且與BOX層14直接接觸。換句話說，裝置層12的整個厚度通過熱程序在與磊晶半導體層22接觸的區段上方局部改質而形成與裝置層12的圍繞的未處理區段具有不同組成的已處理部分。有差異的組成在裝置層12的已處理部分24內付與應變，其在一項具體實施例中可以是壓縮應變。
在一具體實施例中，熱程序可包含熱縮合作用(thermal condensation)，其涉及濕式熱氧化程序或乾式熱氧化程序。在氧化作用期間，鍺原子隨著磊晶半導體層22起於其頂端表面朝與裝置層12的部分24介接處跨布其厚度氧化而不可逆地自磊晶半導體層22傳送到裝置層12 內。就其它因素而言，熱縮合作用基於各具有鑽石晶格結構的鍺及矽、以及介於鍺與矽之間關於氧的不同化學親和性。
在一具體實施例中，熱縮合作用可在含有至少一種含氧氣體的氧化環境中通過乾式氧化程序來進行(例如：在範圍例如自850℃至1250℃的基板溫度下使用氧當作氧化氣體的乾式氧化作用)。熱程序可涉及熱氧化作用(thermal oxidation)與退火的交替週期。硬遮罩層18具不透氧性，防止裝置層12的受包覆部分起氧化作用。熱縮合作用的最終結果是，磊晶半導體層22轉換成空無鍺的氧化殘留物23，並且接收鍺的裝置層12的已處理部分24轉換成保留初始半導體材料的單晶狀態的鍺充實半導體材料，裝置層12由此初始半導體材料所組成。BOX層14拒絕鍺的擴散，使得偏離磊晶半導體層22的鍺完全位於裝置層12的已處理部分24中。
就其它因素，裝置層12的已處理部分24中的鍺濃度取決於裝置層12的厚度與組成、以及磊晶半導體層22的鍺含量及厚度。在一具體實施例中，裝置層12的已處理部分24初始可由矽所組成，並且可通過熱程序轉換成所具鍺濃度範圍自2%至50%的矽鍺。裝置層12的已處理部分24可通過將鍺引進其組成來增加厚度。在氧化作用之後，可使用非氧化性氣氛(例如：乾氮)中的附加熱退火，在導致均質化但不造成應變鬆弛的條件下，使裝置層12的已處理部分24中的鍺分佈均質化。
裝置層12的已處理部分24可因為其引進鍺所誘發的晶體結構改變而將壓縮應變加入。鍺原子位於構成具有已改質組成的裝置層12的半導體材料的晶體結構中的晶格位置，並且具有比例如矽原子更大的原子尺寸。大體上，矽鍺比矽具有稍微更大的晶格常數。與裝置層12的圍繞的未處理部分接觸時，強迫已處理部分24的晶格結構符合裝置層12的圍繞的半導體材料的晶格結構，其中產生引入裝置層12的已處理部分24的壓縮應變。增加已處理部分24的鍺含量會使所加入壓縮應變的量增加。
熱程序之後，因熱程序而空無鍺的組成的磊晶半導體層22的氧化殘留物23，舉例而言，可使用稀氫氟酸(dilute hydrofluoric acid；HF)例如通過蝕刻來選擇性移除。隨後，硬遮罩層18可舉例而言，使用化學機械研磨(CMP)或化學蝕刻自裝置層12的頂端表面移除。藉此曝露裝置層12的頂端表面以進行進一步處理。
請參閱第3圖，其中相似的參考元件符號是指第2圖中及後續製作階段時相似的特徵，蝕刻遮罩26形成於裝置層12的頂端表面上。蝕刻遮罩26可由諸如有機光阻的一層光敏材料所構成，該光敏材料可予以通過旋轉塗布程序塗敷成流體、預烘培、曝露至透過光遮罩投射的光、曝光後烘焙，然後利用化學顯影劑顯影。蝕刻遮罩26的圖案化界定與後續溝槽的位置重合的開口，該等溝槽用於形成隔離區並且藉此就不同類型的場效電晶體界定裝置區。
溝槽28、30、32可通過乾式蝕刻程序在構成裝置層12的半導體材料中形成，並且位於蝕刻遮罩26中開口的各別位置。溝槽28、30、32深達BOX層14的頂端表面。換句話說，溝槽28、30、32伸透裝置層12的整個厚度連至BOX層14的頂端表面。
蝕刻遮罩26的一部分25具有比裝置層12的已處理部分24的長度d2更大的尺寸d1，並且相對於裝置層12的已處理部分24對準，使得形成溝槽28、30、32時，裝置層12的已處理部分24受保護並保留。蝕刻遮罩26的部分25的尺寸d1大於早先用以形成裝置層12的已處理部分24的硬遮罩層18中開口20的對應尺寸。
溝槽28的側壁36與蝕刻遮罩26的部分25的側壁對準。溝槽30的側壁38與蝕刻遮罩26的部分25的對立側壁對準。溝槽28、30兩者隔開，使得裝置層12的一部分40位於溝槽34的側壁36與裝置層12的已處理部分24之間，並且裝置層12的一部分42位於溝槽28的側壁38與裝置層12的已處理部分24之間。裝置層12的部分40、42與裝置層12的已處理部24並列(且共同延展)。裝置層12的部分40、42作用在於促進保存形成溝槽28、30、32之後加入裝置層12的已處理部分24的壓縮應變。
請參閱第4圖，其中相似的參考元件符號是指第3圖中及後續製作階段時相似的特徵，可通過沉積電絕緣體填充溝槽，然後使用例如化學機械研磨相對於裝置層12的頂端表面平坦化電絕緣體，在溝槽28、30、32中 形成隔離區44、46、48。包含隔離區44、46、48的電絕緣體可以是通過化學氣相沉積所沉積的矽的氧化物(例如：二氧化矽)。在一具體實施例中，包含隔離區44、46、48的電絕緣體可以是利用臭氧(ozone)與四乙基正矽酸鹽(tetraethylorthosilicate；TEOS)當作反應劑氣體進行次大氣壓化學氣相沉積所沉積的高外觀比程序(high-aspect-ratio process；HARP)氧化物膜。
裝置區50界定於隔離區44與隔離區46之間，並且包括裝置層12的部分40、42及裝置層12的已處理部分24。裝置層12的部分40、42分別與隔離區44、46並列(且共同延展)、與裝置層12的已處理部分24並列(且共同延展)、以及可以無應變。裝置區50可用於建構p型場效電晶體。
裝置區52是通過位於隔離區46與隔離區48之間的裝置層12的一部分所界定。裝置區52可用於建構n型場效電晶體。
請參閱第5及6圖，其中相似的參考元件符號是指第4圖中及後續製作階段時相似的特徵，場效電晶體51、53可在前段(front end of line；FEOL)處理期間，通過互補式金屬氧化物半導體(CMOS)程序，使用各別裝置區50、52(第4圖)來製作。場效電晶體51、53分別包括由閘極介電質與閘極電極所組成的閘極結構54、55。閘極電極可由金屬、矽化物、多結晶矽(多晶矽)、或這些材料的組合，通過物理氣相沉積(PVD)、化學氣相等沉積所構成。 閘極介電質可由諸如二氧化矽、氮氧化矽、例如氧化鉿或氮氧化鉿的高k介電材料等介電或絕緣材料，通過化學氣相沉積、原子層沉積(ALD)等沉積所構成。閘極介電質與閘極電極可使用微影及蝕刻程序通過圖案化其成分材料的層堆疊來形成。非導電性間隔物56可在閘極結構54、55的側壁上形成。
場效電晶體51包括位於其閘極結構54側翼的隆起的源極/汲極區60、62，而場效電晶體53同樣地包括位於其閘極結構54側翼的隆起的源極/汲極區64、66。磊晶生長程序可用於沉積諸如矽、矽鍺(SiGe)、或碳摻雜矽的半導體材料以形成隆起的源極/汲極區60、62、64、66，並且可在沉積期間包括原位摻雜以付與導電性類型。如圖所示，源極/汲極區60、62、64、66可具有突起形狀，或可替代地具有釘紮型形狀。閘極結構54、55的作用可在於自對準隆起的源極/汲極區60、62、64、66的磊晶半導體材料。隆起的源極/汲極區60、62的半導體材料可包含選自於週期表第III族的p型摻質(例如：硼(B))，其有效付與p型導電性。隆起的源極/汲極區64、66的半導體材料可包含出自週期表第V族的n型摻質(例如：磷(P)或砷(As))，其有效付與n型導電性。"源極/汲極區"一詞於本文中使用時，意為可作用為場效電晶體51、53的源極或汲極的半導體材料的摻雜區。
場效電晶體53的通道68(位於其隆起的源極/汲極區64、66之間且位於其閘極結構54下方)由出自 裝置層12的半導體材料所構成。場效電晶體51的通道(位於其隆起的源極/汲極區60、62之間且位於其閘極結構54下方)由裝置層12的已處理部分24的半導體材料所構成。
閘極結構54以給定電壓偏壓時，對通道施加電場以在其通道變為導通的"接通(ON)"狀態與"斷開(OFF)"狀態之間切換場效電晶體51。在"接通"狀態中，電荷載子(charge carriers)在通道中從充當場效電晶體51的源極的源極/汲極區60、62其中一者流動至充當場效電晶體51的汲極的源極/汲極區60、62其中另一者。在"斷開"狀態中，通道可視為全空乏，因為場效電晶體51的通道部分的整個高度實質沒有電荷載子，若裝置層12的厚度極薄則可特別觀測到此現象。類似考慮適用於場效電晶體53。
包含場效電晶體51的通道的裝置層12的已處理部分24的鍺充實組成可起改善場效電晶體51的效能的作用，其特徵可為p型場效電晶體。特別的是，裝置層12的已處理部分24的鍺增強型組成強化操作期間的電洞載子遷移率。因為裝置層12的已處理部分24於裝置層12的整個厚度自閘極結構64的底端表面延展至BOX層14的頂端表面，全空乏通道的整體可加入增強載子遷移率的應變。
隔離區44、46及含有隔離區44、46的溝槽28、30的位置通過蝕刻遮罩26中的開口來初始選擇及實施，使得隔離區44、46的形成未與裝置層12的已處理部分24交會。所以，加入界定場效電晶體51的通道的裝置 層12的已處理部分24並順著橫切於閘極結構64的縱軸72的方向的應變並未鬆弛，意為電洞載子遷移率的增強性並未因形成隔離區44、46而降低。將裝置層12的已處理部分24與隔離區44、46及內有隔離區44、46駐留的溝槽28、30分開的裝置層12的部分40、42促進保存其通過熱程序(例如：縮合作用)形成時加入裝置層12的已處理部分24的壓縮應變。
場效電晶體51的通道中保留的壓縮應變於場效電晶體51的通道長度受到引導，其橫切於閘極結構64的縱軸72(即穿過閘極結構64的中心延展的線條)。在與閘極結構64的縱軸平行的寬度維度中，隔離區70與裝置層12的已處理部分24相連並毗連(即觸及或接觸)。用於形成這些隔離區70的溝槽穿透裝置層12的已處理部分24。結果是，平行於閘極結構64的長軸而受到引導的壓縮應變的分量得以鬆弛，以使得裝置層12的已處理部分24順著橫切於此縱軸的方向受到單軸應變，並未受到雙軸應變。
在場效電晶體51為n型場效電晶體的一替代具體實施例中，裝置層12的已處理部分24可置放於拉伸應力下，其提升n型場效電晶體的通道中的電子載子遷移率。為達此目的，可選擇磊晶半導體層22的組成以提供熱處理後受到拉伸應變的已處理部分24(通道)。舉例而言，磊晶半導體層22可由摻有碳的矽(Si：C)所組成，諸如碳(C)的比矽更小的原子可自磊晶半導體層22轉移到裝置 層12的已處理部分24內。
本方法如以上所述，系用於製作積體電路晶片。產生的積體電路晶片可由製作商以空白晶圓形式(例如：作為具有多個未封裝晶片的單一晶圓)、當作裸晶粒、或以封裝形式來配送。在後例中，晶片嵌裝於單晶片封裝(例如：塑膠載體，有導線黏貼至主機板或其它更高層階載體)中、或多晶片封裝(例如：具有表面互連或埋置型互連任一者或兩者的陶瓷載體)中。無論如何，晶片可與其它晶片、離散電路元件、及/或其它信號處理裝置整合，作為中間產品或或最終產品的部分。
本文中對"垂直"、"水平"等用語的參照屬於舉例，並非限制，用來建立參考架構。"水平"一詞於本文中使用時，定義為與半導體基板的習知平面平行的平面，與其實際三維空間方位無關。"垂直"與"正交"等詞是指垂直於水平的方向，如剛才的定義。"橫向"一詞是指水平平面內的維度。諸如"上面"及"下面"等詞用於指出元件或結構彼此的相對位置，與相對高度截然不同。
一特徵可連至或與另一元件進行"連接"或"耦合"，其可直接連接或耦合至其它元件，或取而代之，可存在一或多個中介組件。如無中介元件，一特徵可"直接連接"或"直接耦合"至另一元件。如有至少一個中介元件，一特徵可"間接連接"或"間接耦合"至另一元件。
本發明的各項具體實施例的描述已為了說明目的而介紹，但用意不在於窮舉或受限於所揭示的具體 實施例。許多修改及變例對於所屬技術領域中具有通常知識者將會顯而易知，但不會脫離所述具體實施例的範疇及精神。本文中使用的術語是為了最佳闡釋具體實施例的原理、對市場出現的技術所作的實務應用或技術改良、或讓所屬技術領域中具有通常知識者能夠理解本文中所揭示的具體實施例而選擇。

Claims (20)

  1. 一種使用絕緣體上覆矽基板的裝置層形成的裝置結構，該裝置結構包含：位在該裝置層上的閘極結構；位在該裝置層中的通道，該通道位於該閘極結構下方，並且該通道由半導體材料在第一應變下所構成；以及位在該裝置層中的第一隔離區，其中，該裝置層的第一部分位於該第一隔離區與該通道之間，該通道從該閘極結構延展超過該裝置層的全部厚度至該絕緣體上覆矽基板的埋置型氧化物層，並且該裝置層的該第一部分處於比該通道的該半導體材料中的該第一應變更小的第二應變下。
  2. 如申請專利範圍第1項所述的裝置結構，其中，該裝置層的該第一部分與該通道並列，並且該裝置層的該第一部分與該第一隔離區並列。
  3. 如申請專利範圍第1項所述的裝置結構，更包含：位在該裝置層中的第二隔離區；以及該裝置層的第二部分，位於該第二隔離區與該通道之間，其中，該裝置層的該第二部分處於比該通道的該半導體材料中的該第一應變更小的第三應變下。
  4. 如申請專利範圍第1項所述的裝置結構，其中，該裝置層的該第一部分由半導體材料所組成，該通道的該半導 體材料與該裝置層的該第一部分的該半導體材料具有不同的組成，並且該通道的該半導體材料自該裝置層的頂端表面延展至該埋置型氧化物層。
  5. 如申請專利範圍第4項所述的裝置結構，其中，該裝置層具有範圍自2nm至15nm的厚度。
  6. 如申請專利範圍第4項所述的裝置結構，其中，該通道的該半導體材料由矽鍺所構成，而該裝置層的該第一部分的該半導體材料由矽所構成。
  7. 如申請專利範圍第1項所述的裝置結構，其中，該閘極結構具有橫切於該閘極結構的縱軸的長度，並且該通道的該半導體材料中的該第一應變是在平行於該長度的該通道中受到引導。
  8. 如申請專利範圍第7項所述的裝置結構，其中，該通道具有平行於該閘極結構的該縱軸的寬度，並且更包含：位在該裝置層中的第二隔離區，該第二隔離區配置成順著該寬度的方向接觸該通道。
  9. 如申請專利範圍第1項所述的裝置結構，更包含：與該通道耦合的源極；以及與該通道耦合的汲極，其中，該通道的該半導體材料中的該第一應變於該源極與該汲極之間受到引導。
  10. 如申請專利範圍第1項所述的裝置結構，其中，該裝置層的該第一部分無應變，並且該通道的該半導體材料中的該第一應變是壓縮應變。
  11. 一種使用絕緣體上覆矽基板的裝置層形成裝置結構的方法，該方法包含：形成位在該裝置層中的通道；形成位在該裝置層中的第一隔離區，使得該裝置層的第一部分介於該第一隔離區與該通道之間；以及形成位在該裝置層上的閘極結構；其中，該通道位於該閘極結構下方並且是在第一應變下由半導體材料所構成，該通道從該閘極結構延展超過該裝置層的全部厚度至該絕緣體上覆矽基板的埋置型氧化物層，並且該裝置層的該第一部分處於比該通道的該半導體材料中的該第一應變更小的第二應變下。
  12. 如申請專利範圍第11項所述的方法，其中，形成位在該裝置層中的該通道包含：形成具有延展至該裝置層的開口的硬遮罩；在該開口內側的該裝置層上沉積磊晶半導體層；以及將一元件的原子自該磊晶半導體層傳送到該裝置層內，其中，該磊晶半導體層與該裝置層具有不同組成。
  13. 如申請專利範圍第12項所述的方法，其中，該磊晶半導體層的該組成包含矽鍺，而將該元件的該原子自該磊晶半導體層傳送到該裝置層的該第一部分內包含：進行熱程序以將鍺原子自該磊晶半導體層傳送到 該裝置層內。
  14. 如申請專利範圍第13項所述的方法，其中，該熱程序是熱縮合作用，其中，該磊晶半導體層的該矽鍺隨著該鍺自該磊晶半導體層傳送到該裝置層內而通過熱氧化作用轉換成矽的氧化物。
  15. 如申請專利範圍第11項所述的方法，更包含：形成位在該裝置層中的第二隔離區，使得該裝置層的第二部分位於該第二隔離區與該通道之間，其中，該裝置層的該第二部分處於比該通道的該半導體材料中的該第一應變更小的第三應變下。
  16. 如申請專利範圍第11項所述的方法，其中，該裝置層的該第一部分由半導體材料所組成，該通道的該半導體材料與該裝置層的該部分的該半導體材料具有不同的組成，並且該通道的該半導體材料自該裝置層的頂端表面延展至該埋置型氧化物層。
  17. 如申請專利範圍第11項所述的方法，其中，該閘極結構具有橫切於該閘極結構的縱軸的長度，並且該通道的該半導體材料中的該第一應變是在平行於該長度的該通道中受到引導。
  18. 如申請專利範圍第17項所述的方法，其中，該通道具有平行於該閘極結構的該縱軸的寬度，並且更包含：形成位在該裝置層中的第二隔離區，其中，該第二隔離區配置成順著該寬度的方向接觸該通道。
  19. 如申請專利範圍第11項所述的方法，更包含：形成與該通道耦合的源極；以及形成與該通道耦合的汲極，其中，該通道的該半導體材料中的該第一應變於該源極與該汲極之間受到引導。
  20. 如申請專利範圍第11項所述的方法，其中，該裝置層的該第一部分無應變，並且該通道的該半導體材料中的該第一應變是壓縮應變。
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