TWI688989B - 用於nfet和pfet裝置的間隙壁的半導體結構及其製造方法 - Google Patents
用於nfet和pfet裝置的間隙壁的半導體結構及其製造方法 Download PDFInfo
- Publication number
- TWI688989B TWI688989B TW106119471A TW106119471A TWI688989B TW I688989 B TWI688989 B TW I688989B TW 106119471 A TW106119471 A TW 106119471A TW 106119471 A TW106119471 A TW 106119471A TW I688989 B TWI688989 B TW I688989B
- Authority
- TW
- Taiwan
- Prior art keywords
- fin structures
- epitaxial growth
- substrate
- item
- patent application
- Prior art date
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 55
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 28
- 239000003989 dielectric material Substances 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 2
- 238000000407 epitaxy Methods 0.000 claims 2
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 10
- 238000005530 etching Methods 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本發明係關於半導體結構,尤其關於用在NFET和PFET裝置的間隙壁整合方案及其製造方法。該結構包括:複數個用於NFET裝置的磊晶成長鰭結構,具有一第一尺寸的側壁間隙壁;以及複數個用於PFET裝置的磊晶成長鰭結構,具有該第一尺寸的側壁間隙壁。
Description
本發明係關於半導體結構,尤其關於用在NFET和PFET裝置的間隙壁整合方案及其製造方法。
FinFET在積體電路中提供卓越的可擴展性水準以及提昇的整合性水準,FinFET例如也提供對通道傳導的改善電氣控制以及降低的漏電流位準。再者,該FinFET可克服某些其他短通道效應。此外,FinFET可提供較低功率消耗而允許較高整合程度,以較低電壓運作造就出較低臨界電壓,並且相較於平面裝置通常可提昇操作速度。
隨著FinFET比例縮小,控制NFET與PFET裝置之間該間隙壁的厚度就成為關鍵,例如在一種裝置上增加間隙壁厚度可有效限制整個裝置結構的比例縮放。這在目前技術節點及其以外存在問題,其中記錄製造程序的過程需要間隙壁沉積,以在磊晶程序期間保護PFET裝置,導致PFET裝置的間隙壁厚度增加。亦即,該額外間隙壁造成該NFET裝置與該PFET裝置之間不同的間隙壁厚度。在裝置之間空間有限的先進技術節點中,在裝置之間需要額外空間的此額外間隙壁厚度變得越來越關鍵。
在本發明的樣態中,一結構包括:複數個用於NFET裝置的磊晶成長鰭結構,具有一第一尺寸的側壁間隙壁;以及複數個用於PFET裝置的磊晶成長鰭結構,具有該第一尺寸的側壁間隙壁。
在本發明的樣態中,一方法包括:在一基材的一第一側上形成複數個磊晶成長鰭結構,同時保護該基材的一第二側上之鰭結構;在該基材的該第一側上之該等磊晶成長鰭結構上形成側壁間隙壁,同時保護該基材的該第二側上之該等鰭結構;移除該基材的該第二側上之該等鰭結構,同時保護該基材的該第一側上之該等磊晶成長鰭結構;在該等已移除鰭結構的位置上該基材之該第二側上形成複數個磊晶成長鰭結構,同時保護該基材的該第一側上之該等磊晶成長鰭結構;以及在該基材的該第二側上之該等磊晶成長鰭結構上形成側壁間隙壁,同時保護該基材的該第一側上之該等磊晶成長鰭結構。
在本發明的樣態中,一方法包括:在該基材的一第一側以及該基材的一第二側上所形成之複數個鰭結構上沉積非晶質材料;保護該基材的該第二側上之該非晶質材料,同時移除該基材的該第一側上之該非晶質材料;在該非晶質材料的一露出表面上形成一氧化層;用磊晶成長鰭結構取代該基材的該第一側上之該等複數個鰭結構;在該基材的該第一側上該等磊晶鰭結構之上形成側壁;保護該基材的該第一側上之該等磊晶鰭結構,同時用磊晶成長鰭結構取代該基材的該第二側上之該等複數個鰭結構;以及在該基材的該第二側上該等磊晶鰭結構之上形成側壁。
10‧‧‧結構
12‧‧‧鰭結構
12a、12b‧‧‧側邊
12a'、12b'‧‧‧磊晶鰭結構
14‧‧‧淺溝槽隔離區域
16‧‧‧間隙壁材料
18‧‧‧非晶矽材料
20‧‧‧硬光罩
20'‧‧‧硬光罩
22‧‧‧凹槽
24‧‧‧側壁
26‧‧‧源極和汲極區
26'‧‧‧源極和汲極區
28‧‧‧間隙壁材料
28'‧‧‧間隙壁材料
30‧‧‧中間層介電材料
30'‧‧‧中間層介電材料
利用本發明示範具體實施例的非限制範例,參考提及的許多圖式,從下列詳細描述當中描述本發明。
圖1顯示根據本發明態樣的一結構與個別製程。
圖2顯示根據本發明態樣的其他部件之間已露出之鰭結構與個別製程。
圖3顯示根據本發明態樣形成於其他部件之間非晶矽(a-Si)材料已露出表面上之側壁結構與個別製程。
圖4顯示根據本發明態樣的其他部件之間一裝置結構的一第一側上之磊晶鰭結構與個別製程。
圖5顯示根據本發明態樣的其他部件之間該磊晶鰭結構上之間隙壁與中間層介電材料與個別製程。
圖6顯示根據本發明態樣的其他部件之間該中間層介電材料上之一硬罩與個別製程。
圖7顯示根據本發明態樣的其他部件之間該裝置的一第二側上之磊晶鰭結構與個別製程。
圖8顯示根據本發明態樣的其他部件之間該裝置結構的該第二側上該等磊晶鰭結構上之間隙壁與中間層介電材料與個別製程。
本發明係關於半導體結構,尤其關於用在NFET和PFET裝置的間隙壁整合方案及其製造方法。更具體地並且有利地,本發明提供一種提供相同間隙壁厚度給NFET和PFET裝置的間隙壁整合方案,例如:相較於造成NFET和PFET之間不同間隙壁厚度的傳統處理,本文內提供的該整合方案使用一種造成NFET和PFET鰭結構上具有一致間隙壁厚度的間隙壁沉積處理。
本發明的結構可用許多不同工具以許多方式來製造。一般來說,該等方法與工具用來形成尺寸為毫米與奈米等級的結構。用來製造本發明結構的該等方法,即技術,採用積體電路(IC)技術,例如:這些結構建立在晶圓上,並且藉由在晶圓頂部上以光微影蝕刻處理來製作圖案的材料膜來實現。尤其是,該等結構的製造使用三種基本構件:(i)將材料薄膜沉積在一基材上,(ii)利用光微影蝕刻成像將一製圖光罩應用於該等薄膜頂端 上,以及(iii)依照該光罩的選擇來蝕刻該等薄膜。
圖1顯示根據本發明態樣的一結構與個別製程。結構10包括由一Si晶圓塊材或其他半導體材料或絕緣體上矽(silicon-on-insulator,簡稱SOI)基材所形成的複數個鰭結構12,例如:在具體實施例內,複數個鰭結構12可由任何合適的半導體材料形成,包含但不受限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其他III/V或II/VI族複合半導體。使用傳統CMOS處理,可在鰭結構12之間形成淺溝槽隔離(shallow trench isolation,簡稱STI)區域14(例如氧化物材料)。
在具體實施例內,通過傳統側壁影像轉印(sidewall image transfer,簡稱SIT)技術,可形成複數個鰭結構12。在該SIT技術中,使用傳統沉積處理,將例如SiO2這類的一心軸材料(mandrel material)形成於該半導體材料上。在該心軸材料上形成一抗蝕層,並曝光來形成一圖案(開口),然後通過該開口執行一反應離子蝕刻,來形成該等心軸。在具體實施例內,根據鰭結構12之間的所要尺寸,該等心軸可具有不同寬度及/或間隔。間隙壁形成於該等心軸的側壁上,其材料較佳與該等心軸不同,並使用傳統沉積處理來形成。例如:該等間隙壁的寬度與鰭結構12的尺寸匹配。使用對心軸材料有選擇性的傳統蝕刻處理移除或剝離該等心軸,然後在該等間隙壁的間隙之內執行蝕刻,以形成該子微影部件,例如鰭結構12。然後可剝離該等側壁間隙壁。
仍舊參閱圖1,一間隙壁材料16沉積於鰭結構12的露出表面以及STI區域14上。在具體實施例內,間隙壁材料16為不同材料之間的低k介電材料,例如SiCON。間隙壁材料16利用傳統沉積處理來沉積,例如原子層沉積(atomic layer deposition,簡稱ALD)。間隙壁材料16的厚度可大約是1nm至大約40nm;不過本文考慮其他尺寸。
一非晶矽(a-Si)材料18使用傳統化學氣相沉積(chemical vapor deposition,簡稱CVD)處理,沉積在間隙壁材料16上。使用精通技術 人士知道的化學機械拋光(chemical mechanical polishing,簡稱CMP)處理,將a-Si材料18平整化。在具體實施例內,非晶矽(a-Si)材料18將當成光罩,分開圖1中所示側邊12a、12b之間的該NFET和PFET接合形成處理,如本文內的進一步說明。尤其是,該整合方案將運用該a-Si當成該光罩來分開該等NFET和PFET接合形成處理,運用Si與該等硬光罩材料,例如氧化物、氮化物或氮氧化物之間的優異蝕刻選擇性。
在圖2中,一硬光罩材料20沉積於a-Si材料18上。在具體實施例內,硬光罩材料20較佳為與間隙壁材料16不同的材料,例如:硬光罩材料20可為使用一傳統沉積處理,例如CVD,所沉積的SiN。然後使用傳統微影與蝕刻處理,移除該結構一側邊12a(例如PFET側)上的硬光罩材料20和a-Si材料18,例如:在硬光罩材料20上形成的一抗蝕層暴露在能量(光線)之下,來形成對應至該結構的PFET側邊12a上鰭結構12的一圖案(開口)。用化學品(或化學物質)選擇性地蝕刻或移除該結構的PFET側邊12a上硬光罩材料20和a-Si材料18,來執行一反應離子蝕刻(reactive ion etching,簡稱RIE)。在具體實施例內,於此蝕刻處理期間,間隙壁材料16將當成蝕刻阻擋層。
在移除硬光罩材料20之後,使用額外蝕刻處理,在該基材的側邊12b上(例如NFET側)形成硬光罩材料20底下a-Si材料18的一凹槽22。在具體實施例內,該蝕刻處理為等向性蝕刻處理,將在硬光罩材料20底下形成大約2nm至大約5nm的凹槽,例如在硬光罩材料20底下移除大約2nm至大約5nm的a-Si材料18。該抗蝕層可使用傳統剝離劑或氧化灰化技術去除。
如圖3所示,在硬光罩材料20底下露出的a-Si材料18上形成一側壁24。側壁24故意內嵌在硬光罩材料20底下,保護材料避免在後續RIE處理期間受損。在具體實施例內,側壁24為由一a-Si氧化處理所形成的氧化物材料,例如:該a-Si氧化處理包括在低溫時將該結構放入一 氧爐內,接著進行快速熱退火(rapid thermal anneal,簡稱RTA)處理。在具體實施例內,該低溫處理可低於700℃,較佳介於大約600C至大約700℃之間。
在圖4中,可移除PFET側邊12a上的已露出鰭結構12,接著進行磊晶成長處理來形成PFET鰭結構,例如在具體實施例內,利用傳統RIE處理,選擇適用於間隙壁材料16和鰭結構12的已露出部分,可去除已露出鰭結構12。在此步驟中,側壁24將保護NFET側邊12b上的該結構。
接在鰭結構12的已露出部分去除之後,運用一磊晶成長處理,例如磊晶SiGe成長處理,在該第一側上形成磊晶鰭結構12a'。在此成長處理期間,氧化側壁24將避免在a-Si材料18上磊晶成長。在具體實施例內,磊晶鰭結構12a'可用於PFET裝置(由業界所熟知的適當摻雜或離子植入處理所形成)。執行一PFET源極與汲極植入,來形成源極和汲極區26用於新形成的磊晶鰭結構12a'。
如圖5所示,間隙壁材料28沉積在磊晶鰭結構12a'的該等已露出表面上。在具體實施例內,間隙壁材料28為利用傳統沉積處理,例如ALD,所沉積的低k介電材料,例如SiN。間隙壁材料28的厚度可大約是1nm至大約40nm;不過本文考慮其他尺寸。使用一傳統CVD處理,在間隙壁材料28上沉積一中間層介電材料30,例如SiO2。使用一CMP處理將中間層介電材料30平面化。在具體實施例內,中間層介電材料30將平面化至NFET側邊12b上硬光罩材料20的水準。
在圖6中,硬光罩20'沉積在中間層介電材料30,例如SiO2,以及硬光罩材料20的露出表面上。在具體實施例內,硬光罩20'使用一傳統沉積處理,例如CVD,來沉積,並且可為與硬光罩20相同的材料,例如SiN。在PFET側邊12a上的硬光罩材料20'將會與NFET側邊12b上硬光罩20、20'的組合還要薄。
如圖7所示,從NFET側邊12b移除硬光罩20'、20,並且 從PFET側邊12a移除硬光罩20',接著移除a-Si材料18。當硬光罩材料20'比PFET側邊12a還要薄時,在NFET側邊12b上硬光罩20的額外移除也將導致中間層介電材料30凹陷至大約側壁24的高度。如應該了解,側壁24應該在該結構的NFET側邊12b上該a-Si材料移除期間,進一步保護中間層介電材料30避免遭到蝕刻。在具體實施例內,可用如本文所述的傳統蝕刻(RIE)處理,去除硬光罩20'、20和a-Si材料18。
如圖7進一步顯示,利用傳統RIE處理可去除NFET側邊12b上的已露出鰭結構12,接著執行磊晶成長處理來形成磊晶鰭結構12b'(利用業界內已知的適當摻雜或離子植入處理形成於NFET裝置內)。在具體實施例內,該磊晶成長處理為一磊晶SiGe成長處理。執行一NFET源極與汲極植入來形成源極與汲極區26'。
如圖8進一步顯示,間隙壁材料28'沉積在磊晶鰭結構12b'的該等已露出表面上。在具體實施例內,間隙壁材料28'為利用傳統沉積處理,例如ALD,所沉積的低k介電材料,例如SiN。間隙壁材料28'的厚度與PFET側邊12a上間隙壁材料28的厚度相同,例如大約1nm至大約40nm;不過本文也考慮其他尺寸。使用一傳統CVD處理,在間隙壁材料28上沉積一中間層介電材料30',例如SiO2。使用一CMP將中間層介電材料30'平面化。
應該了解,本文說明的處理步驟可逆轉,如此在該結構的該PFET側邊之前先在該結構的該NFET側邊上形成磊晶鰭與間隙壁。然而,在任何情況下,可透過本文所說明的該間隙壁整合方案,形成相同厚度的間隙壁給NFET和PFET裝置,這樣讓裝置之間的關鍵尺寸變窄(例如間隙)。另外,通過實施本文所說明的該間隙壁整合方案,可消除傳統整合方案所需,在磊晶處理期間保護該PFET裝置的額外間隙壁沉積步驟。
上述該(等)方法用於積體電路晶片製造。結果積體電路晶片可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成 裸晶粒或已封裝形式來散佈。在後者案例中,晶片固定在單晶片封裝內(像是塑膠載體,具有導線黏貼至主機板或其他更高層載體)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中,晶片與其他晶片、離散電路元件以及/或其他信號處理裝置整合成為(a)中間產品,像是主機板,或(b)末端產品。末端產品可為包括積體電路晶片的任何產品,範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
許多本發明具體實施例的描述已經為了說明而呈現,但非要將本發明受限在所公布形式中。在不脫離所描述具體實施例之範疇與精神的前提下,本技術之一般技術者將瞭解許多修正例以及變化例。本文內使用的術語係為了能最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進,或可讓精通技術人士能理解本文所揭示的具體實施例。
12‧‧‧鰭結構
12a、12b‧‧‧側邊
12a'、12b'‧‧‧磊晶鰭結構
14‧‧‧淺溝槽隔離區域
24‧‧‧側壁
26‧‧‧源極和汲極區
26'‧‧‧源極和汲極區
28‧‧‧間隙壁材料
28'‧‧‧間隙壁材料
30‧‧‧中間層介電材料
30'‧‧‧中間層介電材料
Claims (35)
- 一種半導體元件的結構,包括:位於一半導體基底結構上的複數個用於NFET裝置的磊晶成長鰭結構,具有一第一尺寸的側壁間隙壁;位於該半導體基底結構上的複數個用於PFET裝置的磊晶成長鰭結構,具有該第一尺寸的側壁間隙壁;以及位於該半導體基底結構上的一a-Si氧化物側壁,用來分隔該等NFET裝置的該等磊晶成長鰭結構與該等PFET裝置的該等磊晶成長鰭結構。
- 如申請專利範圍第1項所述之結構,其中用於該NFET裝置和PFET裝置的該等複數個磊晶成長鰭結構為SiGe鰭結構。
- 如申請專利範圍第1項所述之結構,其中用於該NFET裝置和PFET裝置的該等磊晶成長鰭結構之該等側壁間隙壁為SiN。
- 如申請專利範圍第1項所述之結構,其中該第一尺寸為大約1nm至大約40nm的厚度。
- 如申請專利範圍第1項所述之結構,其中該等側壁間隙壁是位於該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構之間的低k介電材料。
- 如申請專利範圍第5項所述之結構,其中該等側壁間隙壁是位於該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構之間的氧化物材料的表面上。
- 如申請專利範圍第6項所述之結構,其中該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構是位於該半導體基底結構的部分蝕刻的鰭結構上。
- 如申請專利範圍第7項所述之結構,其中該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構直接與該等部分蝕刻的鰭結構接觸。
- 如申請專利範圍第7項所述之結構,其中該等部分蝕刻的鰭結構為半導體材料。
- 如申請專利範圍第9項所述之結構,其中該等部分蝕刻的鰭結構被該等氧化物材料分開。
- 如申請專利範圍第10項所述之結構,其中該等氧化物材料為淺溝槽隔離區。
- 如申請專利範圍第11項所述之結構,其中該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構被層間介電材料覆蓋。
- 如申請專利範圍第12項所述之結構,還包括氧化側壁將覆蓋該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構的該等層間介電材料分開。
- 如申請專利範圍第1項所述之結構,其中; 該等側壁間隙壁為低k介電材料,位於該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構之間;該等側壁間隙壁係設置在介於該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構之間的氧化材料的表面上;以及該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構係設置在該半導體基底結構的部分蝕刻的鰭結構上。
- 如申請專利範圍第14項所述之結構,其中該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構係設置直接與該等部分蝕刻的鰭結構接觸。
- 如申請專利範圍第14項所述之結構,其中該等部分蝕刻的鰭結構為半導體材料。
- 如申請專利範圍第16項所述之結構,其中該等部分蝕刻的鰭結構係由氧化物材料隔開。
- 如申請專利範圍第17項所述之結構,其中該等氧化物材料為淺溝槽隔離區。
- 如申請專利範圍第18項所述之結構,其中該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構係由層間介電材料所覆蓋。
- 如申請專利範圍第19項所述之結構,還包括一氧化側壁將覆蓋該等用於NFET裝置和該等用於PFET裝置的該等磊晶成長鰭結構的該等層間介電材料分開。
- 一種半導體元件的製造方法,包括: 在一基材的一第一側上形成複數個磊晶成長鰭結構,同時保護該基材的一第二側上之鰭結構;在該基材的該第一側上之該等磊晶成長鰭結構上形成側壁間隙壁,同時保護該基材的該第二側上之該等鰭結構;移除該基材的該第二側上之該等鰭結構,同時保護該基材的該第一側上之該等磊晶成長鰭結構;在該等已移除鰭結構的位置上之該基材第二側上形成複數個磊晶成長鰭結構,同時保護該基材的該第一側上之該等磊晶成長鰭結構;以及在該基材的該第二側上之該等磊晶成長鰭結構上形成側壁間隙壁,同時保護該基材的該第一側上之該等磊晶成長鰭結構。
- 如申請專利範圍第21項所述之方法,其中在該基材的該第二側邊上之該等鰭結構受到一a-Si材料的保護。
- 如申請專利範圍第22項所述之方法,進一步包括在該第一側邊與該第二側邊之間一接合處的該a-Si材料上形成一氧化層。
- 如申請專利範圍第23項所述之方法,其中該氧化層形成於在該a-Si材料上形成的一硬光罩材料底下該a-Si材料之凹槽內。
- 如申請專利範圍第23項所述之方法,其中在該基材的該第一側邊上,該氧化層在鰭結構移除期間保護該a-Si材料,並且在該基材的該第一側邊上,該氧化層在形成該等複數個磊晶成長鰭結構期間保護該a-Si材料上的磊晶成長。
- 如申請專利範圍第23項所述之方法,其中該氧化層在CMOS處理來在該基材第二側邊上形成複數個磊晶成長鰭結構期間,保護該基材第一側邊上該等複數個磊晶成長鰭結構之上中間層介電材料。
- 如申請專利範圍第26項所述之方法,其中在該基材第二側邊上形成該等複數個磊晶成長鰭結構的該CMOS處理包括去除該基材第二側邊上該等鰭結構,接著一磊晶成長處理。
- 如申請專利範圍第21項所述之方法,其中在該基材第一側邊和第二側邊上的該等複數個磊晶成長鰭結構為SiGe成長材料。
- 如申請專利範圍第21項所述之方法,其中在該基材第一側邊和第二側邊上該等複數個磊晶成長鰭結構上形成相同尺寸的該等側壁間隙壁。
- 如申請專利範圍第21項所述之方法,其中在該基材第一側邊上形成該等複數個磊晶成長鰭結構包括去除該第一側邊上該等鰭結構,接著SiGe材料的磊晶成長處理。
- 一種半導體元件的製造方法,包括:在該基材的一第一側以及該基材的一第二側上所形成之複數個鰭結構上沉積非晶質材料;保護該基材的該第二側上之該非晶質材料,同時移除該基材的該第一側上之該非晶質材料;在該非晶質材料的一露出表面上形成一氧化層;用磊晶成長鰭結構取代該基材的該第一側上之該等複數個鰭結構,在該基材的該第一側上該等磊晶鰭結構之上形成側壁; 保護該基材的該第一側上之該等磊晶鰭結構,同時用磊晶成長鰭結構取代該基材的該第二側上之該等複數個鰭結構;以及在該基材的該第二側上該等磊晶鰭結構之上形成側壁。
- 如申請專利範圍第31項所述之方法,進一步包括在一硬光罩材料的底下,將該基材第二側邊上的該非晶質材料形成凹槽,並使用氧化處理在該凹槽內該非晶質材料所露出的表面上形成該氧化層。
- 如申請專利範圍第31項所述之方法,其中該非晶質材料為a-Si。
- 如申請專利範圍第31項所述之方法,其中該基材第一側邊和第二側邊上該等磊晶鰭結構上之該等側壁具有相同尺寸。
- 如申請專利範圍第31項所述之方法,其中該第一側邊上的該等磊晶鰭結構為PFET裝置,並且該第二側邊上的該等磊晶鰭結構為NFET裝置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/334,964 US10468310B2 (en) | 2016-10-26 | 2016-10-26 | Spacer integration scheme for FNET and PFET devices |
US15/334,964 | 2016-10-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201816847A TW201816847A (zh) | 2018-05-01 |
TWI688989B true TWI688989B (zh) | 2020-03-21 |
Family
ID=61969889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106119471A TWI688989B (zh) | 2016-10-26 | 2017-06-12 | 用於nfet和pfet裝置的間隙壁的半導體結構及其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10468310B2 (zh) |
CN (1) | CN107993932B (zh) |
TW (1) | TWI688989B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10115807B2 (en) * | 2015-11-18 | 2018-10-30 | Globalfoundries Inc. | Method, apparatus and system for improved performance using tall fins in finFET devices |
US11295991B2 (en) * | 2020-02-24 | 2022-04-05 | Qualcomm Incorporated | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130126951A1 (en) * | 2009-09-29 | 2013-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Fabricating FinFET Device and Structure Thereof |
US20150137236A1 (en) * | 2013-11-20 | 2015-05-21 | GLOBALFOUNDERIES Inc. | Silicon-on-insulator finfet with bulk source and drain |
TW201521095A (zh) * | 2013-11-22 | 2015-06-01 | Ibm | 形成具不同通道材料之n型與p型互補式金氧半場效電晶體的結構與方法 |
US9054189B1 (en) * | 2014-01-06 | 2015-06-09 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US20150214059A1 (en) * | 2014-01-28 | 2015-07-30 | GlobalFoundries, Inc. | Integrated circuits with metal-insulator-semiconductor (mis) contact structures and methods for fabricating same |
US20150357331A1 (en) * | 2014-05-08 | 2015-12-10 | International Business Machines Corporation | Finfet and fin-passive devices |
US20150380438A1 (en) * | 2014-06-26 | 2015-12-31 | International Business Machines Corporation | Trapping dislocations in high-mobility fins below isolation layer |
TW201601218A (zh) * | 2014-06-27 | 2016-01-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及非平面電路裝置之製造方法 |
US20160111542A1 (en) * | 2014-10-17 | 2016-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finfet) device and method for forming the same |
US9331074B1 (en) * | 2015-01-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20160133528A1 (en) * | 2014-11-06 | 2016-05-12 | International Business Machines Corporation | Forming strained fins of different material on a substrate |
US20160155670A1 (en) * | 2014-12-01 | 2016-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stage fin formation methods and structures thereof |
US20160225673A1 (en) * | 2013-12-28 | 2016-08-04 | Texas Instruments Incorporated | High mobility transistors |
US20160240535A1 (en) * | 2015-02-16 | 2016-08-18 | International Business Machines Corporation | Cmos nfet and pfet comparable spacer width |
US20160268378A1 (en) * | 2015-03-12 | 2016-09-15 | Globalfoundries Inc. | Integrated strained fin and relaxed fin |
US9449884B1 (en) * | 2015-12-15 | 2016-09-20 | International Business Machines Corporation | Semiconductor device with trench epitaxy and contact |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130033461A1 (en) * | 2011-08-03 | 2013-02-07 | Silverbrook Research Pty Ltd | System for notetaking with source document referencing |
US8969974B2 (en) * | 2012-06-14 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device |
US9685380B2 (en) * | 2013-05-31 | 2017-06-20 | Stmicroelectronics, Inc. | Method to co-integrate SiGe and Si channels for finFET devices |
KR20150000546A (ko) * | 2013-06-24 | 2015-01-05 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
EP3084807A4 (en) * | 2013-12-19 | 2017-08-16 | Intel Corporation | Method of forming a wrap-around contact on a semicondcutor device |
US9899268B2 (en) * | 2015-03-11 | 2018-02-20 | Globalfoundries Inc. | Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device |
US9607901B2 (en) * | 2015-05-06 | 2017-03-28 | Stmicroelectronics, Inc. | Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology |
-
2016
- 2016-10-26 US US15/334,964 patent/US10468310B2/en active Active
-
2017
- 2017-06-12 TW TW106119471A patent/TWI688989B/zh active
- 2017-07-26 CN CN201710616989.2A patent/CN107993932B/zh active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130126951A1 (en) * | 2009-09-29 | 2013-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Fabricating FinFET Device and Structure Thereof |
US20150137236A1 (en) * | 2013-11-20 | 2015-05-21 | GLOBALFOUNDERIES Inc. | Silicon-on-insulator finfet with bulk source and drain |
TW201521095A (zh) * | 2013-11-22 | 2015-06-01 | Ibm | 形成具不同通道材料之n型與p型互補式金氧半場效電晶體的結構與方法 |
US20160225673A1 (en) * | 2013-12-28 | 2016-08-04 | Texas Instruments Incorporated | High mobility transistors |
US9054189B1 (en) * | 2014-01-06 | 2015-06-09 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US20150214059A1 (en) * | 2014-01-28 | 2015-07-30 | GlobalFoundries, Inc. | Integrated circuits with metal-insulator-semiconductor (mis) contact structures and methods for fabricating same |
US20150357331A1 (en) * | 2014-05-08 | 2015-12-10 | International Business Machines Corporation | Finfet and fin-passive devices |
US20150380438A1 (en) * | 2014-06-26 | 2015-12-31 | International Business Machines Corporation | Trapping dislocations in high-mobility fins below isolation layer |
TW201601218A (zh) * | 2014-06-27 | 2016-01-01 | 台灣積體電路製造股份有限公司 | 半導體裝置及非平面電路裝置之製造方法 |
US20160111542A1 (en) * | 2014-10-17 | 2016-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finfet) device and method for forming the same |
TW201626571A (zh) * | 2014-10-17 | 2016-07-16 | 台灣積體電路製造股份有限公司 | 鰭式場效電晶體裝置結構及其形成方法 |
US20160133528A1 (en) * | 2014-11-06 | 2016-05-12 | International Business Machines Corporation | Forming strained fins of different material on a substrate |
US20160155670A1 (en) * | 2014-12-01 | 2016-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stage fin formation methods and structures thereof |
US9331074B1 (en) * | 2015-01-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20160240535A1 (en) * | 2015-02-16 | 2016-08-18 | International Business Machines Corporation | Cmos nfet and pfet comparable spacer width |
US20160268378A1 (en) * | 2015-03-12 | 2016-09-15 | Globalfoundries Inc. | Integrated strained fin and relaxed fin |
US9449884B1 (en) * | 2015-12-15 | 2016-09-20 | International Business Machines Corporation | Semiconductor device with trench epitaxy and contact |
Also Published As
Publication number | Publication date |
---|---|
US20180114730A1 (en) | 2018-04-26 |
CN107993932A (zh) | 2018-05-04 |
TW201816847A (zh) | 2018-05-01 |
US10468310B2 (en) | 2019-11-05 |
CN107993932B (zh) | 2022-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11749720B2 (en) | Integrated circuit structure and method with solid phase diffusion | |
TWI573267B (zh) | 半導體裝置與製作非平面電路裝置的方法 | |
US10580704B2 (en) | Semiconductor devices with sidewall spacers of equal thickness | |
US10236293B2 (en) | FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET | |
US9601492B1 (en) | FinFET devices and methods of forming the same | |
TW201719769A (zh) | 鰭式場效電晶體的製作方法 | |
TWI637509B (zh) | 使用絕緣體上覆矽基板的裝置層的裝置結構及其形成方法 | |
TW201724281A (zh) | 鰭式場效電晶體的製作方法 | |
KR20190002273A (ko) | FinFET을 위한 하이브리드 방위를 갖는 집적 회로 구조물 및 방법 | |
US20180108732A1 (en) | Notched fin structures and methods of manufacture | |
CN109119470B (zh) | 边界间隔物结构以及集成 | |
US10224330B2 (en) | Self-aligned junction structures | |
TWI688989B (zh) | 用於nfet和pfet裝置的間隙壁的半導體結構及其製造方法 | |
US10680065B2 (en) | Field-effect transistors with a grown silicon-germanium channel | |
US20180350607A1 (en) | Semiconductor structure | |
US20180233580A1 (en) | Semiconductor structure with gate height scaling | |
TWI714176B (zh) | 具降低短路與均勻倒角的置換金屬閘極及其製造方法 | |
US10741668B2 (en) | Short channel and long channel devices | |
US10950505B2 (en) | Multiple finFET formation with epitaxy separation | |
TW202410162A (zh) | 半導體裝置及其形成方法 |