CN109119470B - 边界间隔物结构以及集成 - Google Patents

边界间隔物结构以及集成 Download PDF

Info

Publication number
CN109119470B
CN109119470B CN201711281409.5A CN201711281409A CN109119470B CN 109119470 B CN109119470 B CN 109119470B CN 201711281409 A CN201711281409 A CN 201711281409A CN 109119470 B CN109119470 B CN 109119470B
Authority
CN
China
Prior art keywords
fin structure
forming
fin
epitaxial
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711281409.5A
Other languages
English (en)
Other versions
CN109119470A (zh
Inventor
J·R·霍尔特
亓屹
罗先庆
彭建伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN109119470A publication Critical patent/CN109119470A/zh
Application granted granted Critical
Publication of CN109119470B publication Critical patent/CN109119470B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本公开涉及半导体结构，更具体地，涉及与鳍FET器件一起使用的N‑P边界间隔物结构及其制造方法。该方法包括：形成多个第一鳍结构；在多个鳍结构中的第一鳍结构和多个鳍结构中的第二鳍结构之间形成阻挡层；以及在第一鳍结构上形成外延材料，而至少通过形成在第一鳍结构和第二鳍结构之间的阻挡层来阻挡外延材料延伸到第二鳍结构上。

Description

边界间隔物结构以及集成
技术领域
本公开涉及半导体结构，更具体地，涉及与鳍FET器件一起使用的边界间隔物结构以及制造方法。
背景技术
随着技术节点的提升，在邻近的鳍结构上形成的n-EPI层和p-EPI层之间提供了越来越小的空间。例如，在7nm结构中，对于n-EPI和p-EPI的空间通常仅为大约50nm或更小。这个小间隔可导致对于邻近器件的n-EPI和p-EPI之间或者n-EPI和Vdd电源层之间的N-P短路。例如，在邻近鳍上执行的外延生长工艺期间，外延生长的尺寸会发生变化，或者会发生异常外延生长，这种外延生长扩张超出了形成在各自鳍上的掩模，导致外延材料的合并。
解决该问题的方法是减小在鳍上形成外延层的生长时间，因为EPI层的实际尺寸是生长时间的函数。然而，这可以导致形成不充足的EPI层，而这反过来将限制器件的性能，特别是由于EPI层用于形成鳍FET器件的源极和漏极区域。用于减小邻近鳍结构的外延层之间短路的可能性的另一种方法是使用鳍的侧面上的侧壁间隔物的剩余部分来约束外延生长，因为在7nm节点技术中对于全EPI生长，n-EPI和p-EPI之间的空间是不足的。然而，这又导致EPI体积显著小于所期望的，从而限制了器件的性能。
发明内容
在本公开的一个方面中，一种方法包括：形成多个第一鳍结构；在多个鳍结构中的第一器件的第一鳍结构与第二器件的第二鳍结构之间形成阻挡层；以及在第一鳍结构上形成外延材料，而至少通过形成在第一鳍结构和第二鳍结构之间的阻挡层来阻挡外延材料延伸到第二鳍结构上。
在本公开的一个方面中，一种方法包括：形成用于第一器件类型的第一鳍结构；形成用于与第一器件类型邻近的第二器件类型的第二鳍结构；在第一鳍结构之上形成掩模；在第二鳍结构和掩模之上形成阻挡材料；部分去除阻挡材料以在第二鳍结构的侧壁和掩模的侧壁上留下阻挡材料；去除掩模以在第一器件类型和第二器件类型之间的边界处形成垂直阻挡层；以及在第二鳍结构上生长外延层，而垂直阻挡层防止外延层延伸超出边界。
在本公开的一个方面中，中间结构包括：第一器件的第一鳍结构；与第一鳍结构邻近的第二器件的第二鳍结构；在第一器件和第二器件之间的边界处的阻挡材料；以及在第一器件的边界内的第一鳍结构上的外延材料以及第二器件的边界内的第二鳍结构上的外延材料。阻挡材料被构造成防止第一鳍结构和第二鳍结构的外延材料合并在一起并延伸超出边界。
附图说明
在下面的详细描述中通过本公开的示例性实施例的非限制性示例参考所述多个附图来描述本公开。
图1示出了根据本公开的方面的进入结构以及相应的制造工艺。
图2示出了根据本公开的方面的除了其它特征之外的掩模和鳍结构之上的阻挡层以及相应的制造工艺。
图3示出了根据本公开的方面的除了其它特征之外的掩模上和鳍结构之上的阻挡层的垂直部分以及相应的制造工艺。
图4示出了根据本公开的方面的除了其它特征之外的部分去除以暴露鳍结构的间隔物层以及相应的制造工艺。
图5示出了根据本公开的方面的除了其它特征之外的在鳍结构的暴露部分上的外延生长以及相应的制造工艺。
图6示出了根据本公开的方面的除了其它特征之外的在其它鳍结构的暴露部分上的外延生长以及相应的制造工艺。
图7示出了根据本公开的方面的除了其它特征之外的去除PFET结构和NFET结构的外延层之间的阻挡层以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更具体地，涉及与鳍FET器件一起使用的边界间隔物结构以及制造方法。更具体地，本公开提供了在邻近器件(例如，PFET和NFET)的鳍结构之间以阻挡层形式的物理边界，以防止邻近鳍结构之间的空间中的外延层的合并。有利地，在实施例中，邻近鳍结构之间的阻挡层将防止外延层合并在一起而导致器件的短路。此外，边界防止一个鳍结构的外延层短路到邻近鳍结构的Vdd电源线。
在更具体的实施例中，在本公开中，掩模形成在第一器件上的第一鳍结构之上，并且阻挡材料形成在掩模和第二器件的暴露的第二鳍结构之上。然后阻挡层的部分被部分地去除，在第一器件的鳍结构和第二鳍结构上的掩模的侧壁上留下阻挡材料。覆盖第一鳍结构的掩模可被去除，在不同器件的鳍结构之间留下阻挡层的垂直区域。然后可以执行外延生长工艺以生长例如源极和漏极区域。阻挡材料将防止在第一器件或第二器件的鳍结构上形成的外延层交叉两个不同器件之间的边界。另外，邻近鳍结构之间的阻挡材料可以在没有附加处理步骤(例如，掩蔽步骤)的情况下形成，由此简化了制造工艺。
还要注意的是，虽然上面的描述是对于PFET和NFET器件提供的，但是本公开可以与在任何两个鳍结构之间插入阻挡层结合使用，并且不限于N-P边界。例如，除了其它器件之外，可以插入阻挡层以消除N/N短路或P/P短路。
本公开的结构和方法可以使用多种不同的工具以多种方式制造和执行。通常，方法和工具用于形成尺寸在微米和纳米级的结构。已经从集成电路(IC)技术中采用了用于制造本公开的结构的方法，即技术。例如，这些结构构建在晶片上，并且通过在晶片顶部上通过光刻工艺图案化的材料的膜来实现。具体地，所公开的结构和所公开的方法的制造使用三个基本构建块：(i)在衬底上沉积材料的薄膜，(ii)通过光刻成像在膜的顶部上施加图案化掩模，以及(iii)将膜选择性地蚀刻到掩模。
图1示出了根据本公开的方面的进入结构以及相应的制造工艺。更具体地，图1示出了包括多个鳍结构104、108的鳍FET结构100。在实施例中，鳍结构104、108从衬底材料102形成。在7nm节点技术中，例如，鳍结构108和鳍结构104之间的典型间隔可以是大约20至50nm。在实施例中，衬底材料102可以由包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其它III/V或II/VI化合物半导体的任何合适的半导体材料构成。
在实施例中，鳍结构104、108可以由侧壁图像技术(SIT)形成。在SIT技术的示例中，使用常规的化学气相沉积(CVD)工艺将芯轴材料(例如，SiO2)沉积在基板102上。抗蚀剂形成在芯轴材料上，并暴露于光以形成图案(开口)。反应离子蚀刻通过开口被施行以形成芯轴。在实施例中，取决于窄鳍结构104、108和/或宽鳍结构之间的期望尺寸，芯轴可以具有不同的宽度和/或间隔。
在芯轴的侧壁上形成间隔物，该间隔物优选为不同于芯轴的材料，并且使用本领域技术人员已知的常规沉积工艺形成。例如，间隔物可以具有与窄鳍结构104、108的尺寸相匹配的宽度。使用对芯轴材料有选择性的常规蚀刻工艺去除或剥离芯轴。然后在间隔物的间隔内执行蚀刻以形成亚光刻特征。然后可以剥离侧壁间隔物。在实施例中，如本公开所设想的，宽鳍结构也可在该或其它图案化工艺期间形成，或者通过其它常规图案化工艺形成。鳍结构104可以用于形成该结构的PFET 106侧；而鳍结构108可以用于形成该结构的NFET侧110。
在鳍结构104、108之间形成浅沟槽隔离结构(STI)112。在实施例中，可以通过本领域已知的常规光刻、蚀刻和沉积工艺来形成STI结构112。在另一个实施例中，在鳍结构104、108之上形成间隔物材料114(例如，氮化物或其它介电材料)。在更具体的实施例中，间隔物材料114可以是为后续材料和蚀刻工艺提供选择性的任何绝缘材料。使用常规化学气相沉积(CVD)、等离子体增强CVD(PECVD)或其它共形沉积工艺，可以将间隔物材料114形成为约2nm至约10nm的厚度。此外，鳍结构104(例如，器件的NFET侧110)被光刻掩模116(即，光致抗蚀剂掩蔽层)覆盖。
图2示出了掩模116和鳍结构104之上的阻挡层118。更具体地，如图2所示，阻挡层118是在掩模116和鳍结构104之上形成的N-P阻挡层。在实施例中，阻挡层118可以由不允许外延材料的晶体生长的任何绝缘材料形成。在实施例中，例如，阻挡层118可以由包括但不限于Al2O3的金属氧化物构成。其它材料可以包括例如SiOC或其它绝缘材料。阻挡层118优选地形成为具有约2nm至约12nm的厚度，并且使用诸如CVD或PECVD工艺的常规技术来沉积。
图3示出了去除阻挡层118的部分之后的结构。具体地，如图3所示，通过各向异性蚀刻工艺去除阻挡层118的水平表面。该过程导致阻挡层118的垂直部分120保留在器件的PFET侧106上的鳍结构104的间隔物材料114的侧壁上，而去除阻挡层的其余水平表面。通过该方式，间隔物材料114上的垂直部分120可用于形成鳍结构104、108的侧壁上的间隔物。在此过程中，阻挡层118的垂直部分也可通过蚀刻工艺被轻微地凹进。
在实施例中，有利地，可以形成N-P边界或阻挡122和鳍结构104、108上的侧壁间隔物而无需单独的掩蔽步骤。换句话说，图2中所示的阻挡层118的初始形成允许形成N-P边界(以防止结构的PFET侧106与结构的NFET侧110的外延层之间的短路)和侧壁间隔物120，而不需要单独的掩蔽步骤。对此，应注意的是，侧壁间隔物120还可用于在后续源极和漏极形成期间防止不期望的掺杂剂和杂质扩散到结构的PFET侧106或NFET侧110的下部中。在实施例中，侧壁间隔物120可以通过其上形成侧壁衬里间隔物的间隔物材料114的一部分与衬底102和STI 112的上表面分离。
在图4中，除了其它特征之外，间隔物材料114被部分地去除以暴露鳍结构104。在实施例中，例如，间隔物材料114可以通过氮化物蚀刻被部分地去除。注意，阻挡层的垂直部分120将在该蚀刻工艺期间用作掩模，防止间隔物材料114的完全去除。间隔物蚀刻还将暴露鳍结构104的部分用于后续的外延生长工艺。在间隔物蚀刻之后，鳍结构104将部分地凹进至间隔物材料114的高度以下。在实施例中，鳍结构104的凹进可通过具有选择性化学的反应离子蚀刻(RIE)工艺来提供。从图4中可以看出，用于该结构的PFET侧106的鳍结构104现在被暴露，使它们可用于后续的外延生长工艺。
仍然参考图4，在器件的NFET侧110上，通过常规氧灰化工艺或其它剥离剂工艺去除掩模材料。通过该方式，阻挡层122的部分将保留在NFET侧110与PFET侧106之间，在该结构的NFET侧110与PFET侧106之间形成N-P边界或阻挡122。该N-P边界或阻挡122将限制或防止外延生长扩张超出器件的PFET侧106。因此，可以避免不同器件(例如，PFET器件106和NFET器件110)之间的短路。
在实施例中，对于在鳍结构的蚀刻之前初始的鳍高度为约45nm的情况，N-P边界或者阻挡122可以具有至少30nm的边界高度。然而，应当认识到，N-P边界或阻挡122的其它高度在此也是可预期的，例如50nm、53nm等。N-P边界或阻挡122的厚度可以在约2nm至约12nm的范围内，优选厚度为约10nm至约12nm。注意的是，虽然图4示出了被暴露的鳍结构104的设置，但是也预期了这些过程以首先暴露NFET侧110的鳍结构108。
如图5所示，外延生长工艺在鳍结构104的暴露部分上执行，形成外延层124(例如，p-EPI层)。例如，外延层124可用于凸起的源极和漏极区域。根据本公开，N-P边界或阻挡122将形成边界以防止外延层124扩张超出N-P边界或阻挡122到结构的NFET侧110的鳍结构108周围的区域中。如此，N-P边界或阻挡122将防止外延层124与结构的NFET侧110的元件之间的短路。此外，如本领域技术人员应当理解的，鳍结构108上的间隔物材料114将防止外延材料在结构的PFET侧110上生长。
图6示出了在结构的NFET侧110上的外延材料126的形成。例如，在图6中，去除结构的NFET侧110上的掩模，并且在结构的PFET侧106上形成掩模128。更具体地，掩模128形成在外延层124之上。其后，部分地去除间隔物材料114以暴露鳍结构108。在实施例中，间隔物材料114可例如通过氮化物蚀刻而被部分地去除。间隔物蚀刻还将暴露鳍结构108的部分。在间隔物蚀刻之后，鳍结构108将部分地凹进至间隔物材料114的高度以下。在实施例中，鳍结构108的凹进可以通过具有选择性化学的RIE工艺来提供。从图6中可以看出，用于结构的NFET侧110的鳍结构108现在被暴露，使它可用于后续的外延生长。
仍然参考图6，外延生长工艺在鳍结构108的暴露部分上执行，形成外延层126(例如，n-EPI层)。根据本公开，N-P边界或阻挡122将防止外延层126扩张超出N-P边界或阻挡122到器件106的PFET侧的鳍结构104周围的区域中。更具体地，在工艺的该阶段处，N-P边界或阻挡122将防止外延层126与外延层124合并。通过该方式，防止了器件的短路。在生长工艺之后，掩模128可以通过任何常规的去除工艺(例如，氧灰化或其它剥离剂)来去除。
图7示出了在执行去除N-P边界或阻挡122的可选步骤之后的图6的结构。如图7所示，间隔物材料114的部分可保留在STI 112衬底的上表面上以避免不必要的去除步骤。在实施例中，N-P边界或阻挡122可以通过具有选择性化学的RIE工艺去除。
在上述处理步骤之后，根据常规工艺，可以使用外延层124和126形成源极和漏极区域。例如，离子注入。在替代实施例中，外延层124和126可以被原位掺杂以形成凸起的源极和漏极区域。随后，通过本领域技术人员已知的常规光刻、蚀刻和沉积方法来形成金属化结构(例如，布线结构、互连结构)，以完成PFET器件106和NFET器件110的形成。
例如，可以在外延层之上形成绝缘层。形成在绝缘层之上的抗蚀剂暴露于能量(光)以形成图案(开口)。具有选择性化学的蚀刻工艺(例如，RIE)将用于通过抗蚀剂的开口在绝缘材料中形成一个或多个沟槽。然后可以通过常规氧灰化工艺或其它已知的剥离剂来去除抗蚀剂。在去除抗蚀剂之后，可以通过任何常规的沉积工艺(例如，化学气相沉积(CVD)工艺)来沉积导电材料。可以通过常规的化学机械抛光(CMP)工艺去除绝缘材料的表面上的任何残留材料。还应注意的是，Vdd电源线通常在处理期间在外延层中的一个上形成，其中阻挡层118用于防止鳍FET结构上的外延层的不期望的扩张而扩张到与Vdd电源线的接触中。
如上所述的方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(也就是说，作为具有多个未封装芯片的单个晶片)作为裸芯片或以封装形式分发。在后一种情况下，芯片安装在单个芯片封装(诸如塑料载体，具有固定到母板或其它更高级别载体的引线)或多芯片封装(诸如具有单面或双面表面互连或掩埋互连的陶瓷载体)中。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理设备集成，作为(a)中间产品(诸如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
为了说明的目的，已经呈现了本公开的各种实施例的描述，但并不旨在穷举或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。选择在此所使用的术语是为了最好地解释实施例的原理、对市场中发现的技术的实际应用或技术改进，或使得本领域普通技术人员能够理解在此所公开的实施例。

Claims (19)

1.一种用于制造半导体结构的方法，包括：
形成多个第一鳍结构；
在多个鳍结构中的第一鳍结构与多个鳍结构中的第二鳍结构之间形成阻挡层；
在所述第一鳍结构上形成外延材料，而通过形成在所述第一鳍结构与所述第二鳍结构之间的所述阻挡层来阻挡所述外延材料延伸到所述第二鳍结构上；
在形成所述阻挡层之前，在所述第一鳍结构和所述第二鳍结构上形成绝缘材料；
在形成所述阻挡层之前，在所述第二鳍结构之上形成掩模材料；
在形成所述阻挡层之前，在所述第一鳍结构和所述掩模材料上沉积用于所述阻挡层的阻挡材料；以及
去除在所述掩模材料和所述第一鳍结构上的所述阻挡材料的水平部分，以形成所述第一鳍结构的所述阻挡层和间隔物。
2.根据权利要求1所述的方法，还包括在所述第二鳍结构之上形成绝缘层和阻挡材料，其防止所述外延材料形成在所述第二鳍结构上。
3.根据权利要求1所述的方法，其中，所述阻挡层防止形成在所述第一鳍结构上的所述外延材料延伸到另一器件的区域。
4.根据权利要求3所述的方法，其中，形成所述外延材料是形成在所述第一鳍结构的暴露的半导体材料上的生长工艺。
5.根据权利要求4所述的方法，其中，所述第一鳍结构的所述暴露的半导体材料还包括去除所述第一鳍结构上的所述绝缘材料的部分，接着所述暴露的半导体材料的凹进。
6.根据权利要求1所述的方法，其中，所述阻挡层和所述间隔物在单个蚀刻步骤中形成。
7.根据权利要求1所述的方法，还包括在所述第二鳍结构上形成外延材料，而保护所述第一鳍结构上的所述外延材料。
8.根据权利要求1所述的方法，还包括：
去除所述绝缘材料的部分以暴露所述第一鳍结构的半导体材料；
在所述第一鳍结构的所述暴露的部分上形成所述外延材料，而所述绝缘材料和所述阻挡材料在所述第二鳍结构上；
保护所述外延材料，而暴露所述第二鳍结构的半导体材料；以及
在所述第二鳍结构上形成外延材料，而在所述第一鳍结构和所述第二鳍结构之间形成的所述阻挡层防止所述第二鳍结构上的所述外延材料在所述第一鳍结构上的所述外延材料上扩张。
9.根据权利要求1所述的方法，其中，所述第一鳍结构是第一器件以及所述第二鳍结构是第二器件。
10.根据权利要求1所述的方法，其中，所述阻挡层包括金属氧化物或金属氮化物。
11.根据权利要求10所述的方法，其中，所述金属氧化物是Al2O3。
12.一种用于制造半导体结构的方法，包括：
形成用于第一器件类型的第一鳍结构；
形成用于与所述第一器件类型邻近的第二器件类型的第二鳍结构；
在所述第一鳍结构和所述第二鳍结构上形成绝缘材料；
在所述第一鳍结构之上形成掩模；
在所述第二鳍结构和所述掩模之上形成阻挡材料；
去除在所述掩模和在所述第二鳍结构上的所述绝缘材料上的所述阻挡材料的水平部分以在所述第二鳍结构上的所述绝缘材料的侧壁和所述掩模的侧壁上留下阻挡材料；
去除所述掩模以在所述第一器件类型和所述第二器件类型之间的边界处形成垂直阻挡层；以及
在所述第二鳍结构上生长外延层，而所述垂直阻挡层防止所述外延层延伸超出所述边界。
13.根据权利要求12所述的方法，其中，所述第一器件类型和所述第二器件类型是不同类型的器件。
14.根据权利要求12所述的方法，其中，去除所述阻挡材料形成在所述第二鳍结构上的间隔物。
15.根据权利要求12所述的方法，还包括从沉积在所述第二鳍结构上的所述阻挡材料在所述第二鳍结构的侧壁上形成间隔物材料，接着是凹进蚀刻步骤。
16.根据权利要求12所述的方法，其中，所述阻挡材料包括金属氧化物或金属氮化物。
17.根据权利要求16所述的方法，其中，所述金属氧化物是Al2O3。
18.一种中间半导体结构，包括：
第一器件的第一鳍结构；
与所述第一鳍结构邻近的第二器件的第二鳍结构；
在所述第一鳍结构和所述第二鳍结构上的绝缘材料；
阻挡材料，包括在所述第一器件和所述第二器件之间的边界处的第一部分和在所述第一鳍结构的侧壁上的所述绝缘材料的侧壁上的第二部分；以及
在所述第一器件的所述边界内的所述第一鳍结构上的外延材料，以及在所述第二器件的所述边界内的所述第二鳍结构上的外延材料，
其中，所述阻挡材料的所述第一部分被构造成防止所述第一鳍结构和所述第二鳍结构的所述外延材料合并在一起并延伸超出所述边界。
19.根据权利要求18所述的中间半导体结构，其中，所述阻挡材料是Al2O3。
CN201711281409.5A 2017-06-22 2017-12-07 边界间隔物结构以及集成 Active CN109119470B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/630547 2017-06-22
US15/630,547 US10262903B2 (en) 2017-06-22 2017-06-22 Boundary spacer structure and integration

Publications (2)

Publication Number Publication Date
CN109119470A CN109119470A (zh) 2019-01-01
CN109119470B true CN109119470B (zh) 2021-11-05

Family

ID=64693438

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711281409.5A Active CN109119470B (zh) 2017-06-22 2017-12-07 边界间隔物结构以及集成

Country Status (3)

Country Link
US (1) US10262903B2 (zh)
CN (1) CN109119470B (zh)
TW (1) TWI666692B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10658242B2 (en) * 2017-11-21 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with Fin structures
US10763363B2 (en) 2018-04-10 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gradient doped region of recessed fin forming a FinFET device
US11217584B2 (en) 2019-10-23 2022-01-04 Globalfoundries U.S. Inc. Limiting lateral epitaxy growth at N-P boundary using inner spacer, and related structure
US11862519B2 (en) * 2021-08-30 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device with epitaxial features having adjusted profile and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633143A (zh) * 2012-08-21 2014-03-12 意法半导体公司 在最外鳍的外侧表面上包括外延生长阻挡物的多鳍finfet器件和相关方法
CN104517857A (zh) * 2013-09-27 2015-04-15 三星电子株式会社 包括鳍形场效应晶体管的集成电路器件及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US8691651B2 (en) * 2011-08-25 2014-04-08 United Microelectronics Corp. Method of forming non-planar FET
US9553093B1 (en) * 2015-12-11 2017-01-24 International Business Machines Corporation Spacer for dual epi CMOS devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633143A (zh) * 2012-08-21 2014-03-12 意法半导体公司 在最外鳍的外侧表面上包括外延生长阻挡物的多鳍finfet器件和相关方法
CN104517857A (zh) * 2013-09-27 2015-04-15 三星电子株式会社 包括鳍形场效应晶体管的集成电路器件及其形成方法

Also Published As

Publication number Publication date
CN109119470A (zh) 2019-01-01
US10262903B2 (en) 2019-04-16
TWI666692B (zh) 2019-07-21
US20180374759A1 (en) 2018-12-27
TW201905981A (zh) 2019-02-01

Similar Documents

Publication Publication Date Title
US10593779B2 (en) Replacement metal gate structures
US9887198B2 (en) Semiconductor devices with sidewall spacers of equal thickness
CN110176453B (zh) 中段制程结构
CN109119470B (zh) 边界间隔物结构以及集成
CN110047829B (zh) 中段制程结构
US11810812B2 (en) Single diffusion cut for gate structures
US20180108732A1 (en) Notched fin structures and methods of manufacture
US10651173B1 (en) Single diffusion cut for gate structures
TW202137572A (zh) 積體晶片
CN109950160B (zh) 半导体元件的精细互连的制备方法
TWI729283B (zh) 接觸結構
CN107993932B (zh) 用于nfet和pfet器件的间隔物集成方案
US9564317B1 (en) Method of forming a nanowire
US11651992B2 (en) Gap fill void and connection structures
US11171237B2 (en) Middle of line gate structures
CN114122006A (zh) 具有包含腔结构的局部绝缘体上半导体区域的晶片

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant