TW201905981A - 邊界間隙壁結構及積體化 - Google Patents

邊界間隙壁結構及積體化

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TW201905981A
TW201905981A TW106142397A TW106142397A TW201905981A TW 201905981 A TW201905981 A TW 201905981A TW 106142397 A TW106142397 A TW 106142397A TW 106142397 A TW106142397 A TW 106142397A TW 201905981 A TW201905981 A TW 201905981A
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fin structure
forming
barrier
barrier layer
fin
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TW106142397A
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TWI666692B (zh
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賈森Ｒ 霍特
亓屹
羅先慶
彭建偉
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明係有關半導體結構，尤其是有關連同finFET裝置所使用的N-P邊界間隙壁結構及其製造方法。所述方法包括形成複數個第一鰭結構；在該等鰭結構的一第一鰭結構與該等鰭結構的一第二鰭結構之間形成一阻障層；以及在該第一鰭結構上形成一磊晶材料，而透過至少在該第一鰭結構與該第二鰭結構之間所形成的該阻障層，阻擋該磊晶材料延伸到該第二鰭結構。

Description

邊界間隙壁結構及積體化
本發明係有關半導體結構，尤其是有關連同finFET裝置使用的邊界間隙壁結構及其製造方法。
隨著技術節點的進展，在相鄰鰭結構上所形成的n-EPI層與p-EPI層之間僅提供愈來愈小的空間。例如，在7nm結構中，介於n-EPI和p-EPI的空間通常僅僅約50nm或更小。此小間隙可能在相鄰裝置的n-EPI與p-EPI之間、或在n-EPI與Vdd電源層之間導致N-P短路。例如，在相鄰鰭上進行的磊晶生長製程期間，磊晶生長的大小可發生變化，或可發生異常的磊晶生長，擴展超出形成在各自鰭上的光罩，從而導致磊晶材料合併。
由於EPI層的實際大小係生長時間的函數，因此解決此問題的方法係減少在鰭上形成磊晶層的生長時間。然而，這可能導致形成不適宜的EPI層，尤其由於EPI層係用於形成finFET裝置的源極和汲極區，因此進而將限制裝置性能。由於n-EPI與p-EPI之間的空間不足以用於在7nm節點技術中的完整EPI生長，因此減少相鄰鰭結構的磊晶層之間的短路可能性的另一種方法，係使用鰭側面上的側壁間隙壁的剩餘部分約束磊晶生長。然而，這又會導致EPI體積大幅小於實際所需，從而限制裝置性能。
在所揭示內容的各種態樣中，一種方法包含：形成複數個第一鰭結構；在該等複數個鰭結構的一第一裝置的一第一鰭結構與一第二裝置的一第二鰭結構之間形成一阻障層；及在該第一鰭結構上形成一磊晶材料，同時透過形成在該第一鰭結構與該第二鰭結構之間的至少該阻障層，阻擋該磊晶材料延伸到該第二鰭結構上。
在本發明之一態樣中，一種方法包含：形成用於一第一裝置類型的一第一鰭結構；形成用於相鄰該第一裝置類型的一第二裝置類型的一第二鰭結構；在該第一鰭結構上方形成一光罩；在該第二鰭結構和該光罩上形成一阻障材料；部分去除該阻障材料，以在該第二鰭結構的一側壁和該光罩的一側壁上留下一阻障材料；去除該光罩，以在該第一裝置類型與該第二裝置類型之間的一邊界形成一垂直阻障層；及在該第二鰭結構上生長一磊晶層，同時該垂直阻障層防止該磊晶層延伸超出該邊界。
在本發明之一態樣中，一種中間結構包含：一第一裝置的一第一鰭結構；一第二裝置的一第二鰭結構，其相鄰該第一鰭結構；一阻障材料，其在該第一裝置與該第二裝置之間的一邊界；及一磊晶材料，其在該第一裝置的邊界內的第一鰭結構上，以及該第二裝置的邊界內的第二鰭結構上的磊晶材料。該阻障材料係結構化，以防止該第一鰭結構和該第二鰭結構的磊晶材料合併在一起及延伸超出該邊界。
100‧‧‧finFET結構
102‧‧‧基材
104、108‧‧‧鰭結構
106‧‧‧PFET裝置
110‧‧‧NFET裝置
112‧‧‧淺溝槽隔離(STI)結構
114‧‧‧間隙壁材料
116‧‧‧光罩
118‧‧‧阻障層
120‧‧‧側壁間隙壁
122‧‧‧N-P邊界或阻障
124‧‧‧磊晶層
126‧‧‧磊晶層
128‧‧‧光罩
在接下來的實施方式中，將藉由本發明的示例性具體實施例的非限制性範例，連同參考所提及的複數個圖式說明本發明。
圖1顯示依據本發明的態樣的引入結構和各自製程。
圖2顯示除了其他特徵之外，依據本發明的態樣之在光罩和鰭結構上方的阻障層、及各自製程。
圖3顯示除了其他特徵之外，依據本發明的態樣之光罩和鰭結構上方的阻障層的垂直部分、及各自製程。
圖4顯示除了其他特徵之外，依據本發明的態樣之部分去除以暴露該等鰭結構的間隙壁層、及各自製程。
圖5顯示除了其他特徵之外，依據本發明的態樣之鰭結構的暴露部分上的磊晶生長、及各自製程。
圖6顯示除了其他特徵之外，依據本發明的態樣之其他鰭結構的暴露部分上的磊晶生長、及各自製程。
圖7顯示除了其他特徵之外，依據本發明的態樣之去除用於PFET結構和NFET結構的該等磊晶層之間的阻障層、及各自製程。
本發明係有關半導體結構，尤其是有關連同finFET裝置使用的邊界間隙壁結構及製造方法。更具體而言，本發明提供形式在相鄰裝置(例如PFET和NFET)的鰭結構之間的阻障層的實體邊界，以防止相鄰鰭結構之間的空間中的磊晶層合併。優點係，在具體實施例中，該等相鄰鰭結構之間的阻障層將防止磊晶層合併在一起導致裝置短路。此外，該邊界防止一鰭結構的磊晶層短路到相鄰鰭結構的Vdd電源線。
在本發明更具體的實施例中，在第一裝置上的第一鰭結構上方形成光罩，並在該光罩和第二裝置的暴露第二鰭結構上方形成阻障材料。然後部分去除該阻障層的各部分，從而在該第一裝置的鰭結構和該第二鰭結構上的光罩的側壁上留下該阻障材料。可去除覆蓋該第一鰭結構的光罩，從而在不同裝置的該等鰭結構之間留下該阻障層的垂直範圍。然後可進行磊晶生長製程，以生長例如源極和汲極區。該阻障材料將防止擇一形成在該第一裝置或該第二裝置的鰭結構上的磊晶層跨越兩個不同裝置之間的邊界。又再者，無需附加處理步驟(例如光罩製程步驟)即可形成相鄰鰭 結構之間的阻障材料，由此簡化了製程步驟。
應注意的是，儘管已針對PFET和NFET裝置提供以上說明，但本發明可搭配在任何兩鰭結構之間插入阻障層使用，且不限於N-P邊界。例如，除了其他裝置之外，可插入該阻障層以排除N/N短路或P/P短路。
本發明的該等結構和方法可使用多種不同的工具以多種方式製造及進行。一般來說，該等方法和工具係用於形成具有微米和奈米尺度的結構。用於製造本發明的該等結構的方法(即技術)已從積體電路(integrated circuit，IC)技術導入。例如，該等結構係建構在晶圓上，並實現在由晶圓頂部上的光微影製程所圖案化的材料薄膜中。特別是，該等所揭示結構的製造和該等所揭示方法使用三個基本建構區塊：(i)在基材上沉積材料薄膜、(ii)透過光微影成像在該等薄膜上施加圖案化的光罩，及(iii)選擇性蝕刻該光罩的薄膜。
圖1顯示依據本發明的態樣之引入結構和各製程。更具體而言，圖1例示包含複數個鰭結構104、108的finFET結構100。在一具體實施例中，該等鰭結構104、108係由基材材料102形成。在7nm節點技術中，例如，該等鰭結構108與該等鰭結構104之間的一般間隙可約為20-50nm。在具體實施例中，基材材料102可能係由任何適合的半導體材料組成，包括但不限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和其他III/V族或II/VI族化合物半導體。
在具體實施例中，該等鰭結構104、108可由側壁影像技術(sidewall image technique，簡稱SIT)形成。在SIT技術的範例中，可使用習知的化學氣相沉積(chemical vapor deposition，簡稱CVD)製程在基材102上沉積半導體陰極金屬芯材(mandrel)(例如SiO2)。光阻劑係形成在該半導體陰極金屬芯材上，並曝光以形成圖案(開口)。透過該等開口進行活性離子蝕刻，以形成該等半導體陰極金屬芯。在具體實施例中，該等半導體陰極金 屬芯可依該等窄鰭結構104、108與/或寬鰭結構之間的該等所需尺寸而定，具有不同的寬度及/或間隙。
間隙壁係形成在該等半導體陰極金屬芯的該等側壁上，其較佳為不同於該等半導體陰極金屬芯材，且其係使用熟習此領域技術者已習知的沉積製程形成。例如，該等間隙壁可具有匹配該等窄鰭結構104、108的該等尺寸的寬度。該等半導體陰極金屬芯係使用對該半導體陰極金屬芯材具選擇性的習知蝕刻製程以去除或剝離。然後再對該等間隙壁的間隙內部進行蝕刻，以形成該等亞微影(sub-lithographic)特徵。然後可剝離該等側壁間隙壁。在具體實施例中，如本發明所考慮，該等寬鰭結構也可在此或其他圖案化製程期間形成，或是透過其他習知圖案化製程形成。鰭結構104可用於形成該結構的PFET側面106；然而，鰭結構108可用於形成該結構的NFET側面110。
淺溝槽隔離(shallow trench isolation，簡稱STI)結構112係在該等鰭結構104、108之間形成。在具體實施例中，該等STI結構112可透過如此技術領域已知的習知微影、蝕刻和沉積製程形成。在進一步具體實施例中，間隙壁材料114(如氮化物或其他介電體材料)係在該等鰭結構104、108上方形成。在進一步具體實施例中，間隙壁材料114可為對後續材料和蝕刻製程提供選擇性的任何絕緣體材料。間隙壁材料114可使用習知的化學氣相沉積(CVD)、電漿輔助CVD(plasma enhanced CVD，簡稱PECVD)或其他共形沉積製程形成為約2nm至約10nm的厚度。此外，該等鰭結構104(如該裝置的NFET側面110)係由微影光罩116(即光阻光罩層)所覆蓋。
圖2顯示光罩116和鰭結構104上方的阻障層118。更具體而言，在圖2中，阻障層118係形成在光罩116和該等鰭結構104上方的N-P阻障層。在具體實施例中，阻障層118可由不允許磊晶材料的晶體生長的任何絕緣體材料形成。在具體實施例中，例如，阻障層118可由金屬氧 化物組成，包括但不限於Al2O3。附加材料可包括例如SiOC或其他絕緣體材料。阻障層118較佳為形成具有約2nm至約12nm的厚度，並係使用例如CVD或PECVD製程的習知技術沉積。
圖3顯示去除阻障層118的各部分之後的結構。具體而言，如圖3所示，阻障層118的水平表面係透過各向異性蝕刻製程去除。此製程導致阻障層118的垂直部分120保留在該裝置的PFET側面106上的該等鰭結構104的間隙壁材料114的側壁上，同時去除該阻障層的該等剩餘的水平表面。如此，間隙壁材料114上的該等垂直部分120可用於在該等鰭結構104、108的該等側壁上形成間隙壁。在此製程中，阻障層118的該等垂直部分也可能透過該蝕刻製程稍微凹陷。
在具體實施例中，且其優點在於，無需分開光罩製程步驟即可形成該等鰭結構104、108上的N-P邊界或阻障122和側壁間隙壁。換言之，初期形成圖2所示阻障層118無需分開的光罩步驟，即容許形成N-P邊界(以防止該結構的該等PFET側面106的該等磊晶層與該結構的NFET側面110之間的短路)和該等側壁間隙壁120兩者。關於這點，應注意該等側壁間隙壁120也可用於在後續源極和汲極形成期間，防止不需要的摻雜物和雜質擴散到該結構的PFET側面106或NFET側面110的底層部分中。在具體實施例中，該等側壁間隙壁120可由其上形成該等側壁襯裡間隙壁的間隙壁材料114的一部分，從基材102和STI 112的上部表面隔開。
在圖4中，間隙壁材料114係部分去除，以暴露該等鰭結構104及其他特徵。在具體實施例中，例如，間隙壁材料114可透過氮化物蝕刻部分去除。應注意的是，該阻障層的該等垂直部分120將用作此蝕刻製程期間的光罩，從而防止完全去除間隙壁材料114。該間隙壁蝕刻也將暴露用於後續磊晶生長製程的該等鰭結構104的各部分。在該間隙壁蝕刻之後，該等鰭結構104將部分凹陷成低於間隙壁材料114的高度。在具體實施例中，該等鰭結構104的凹部可透過具有選擇性化學反應的活性離子蝕刻(RIE) 製程提供。從圖4所示應可瞭解，現在暴露出用於該結構的PFET側面106的該等鰭結構104，從而使其可用於後續磊晶生長製程。
請再參考圖4，該光罩材料係透過該裝置的NFET側面110上的習知氧氣灰化製程或其他剝離劑(stripant)製程去除。如此，阻障層118的一部分將保留在NFET側面110與PFET側面106之間，從而在該結構的NFET側面110與PFET側面106之間形成N-P邊界或阻障122。此N-P邊界或阻障122將限制或防止磊晶生長擴展超出該裝置的PFET側面106。據此，可避免該等不同裝置(如PFET裝置106和NFET裝置110)之間的短路。
在具體實施例中，對在蝕刻該等鰭結構之前的初期鰭高度約為45nm的情況而言，N-P邊界或阻障122可具有至少30nm的邊界高度。不過亦應明白的是，本說明書所揭露內容也考慮N-P邊界或阻障122的其他高度(如50nm、53nm等)。N-P邊界或阻障122的厚度可在自約2nm至約12nm的範圍內，其中較佳厚度約為自10nm至約12nm。應注意的是，儘管圖4顯示暴露出的該等鰭結構104的設置，但也設想該等製程首先暴露NFET側面110的鰭結構108。
如圖5所示，磊晶生長製程係在形成磊晶層124(如p-EPI層)的該等鰭結構104的該等暴露部分上進行。例如，磊晶層124可用於抬高式(raised)源極和汲極區。依據本發明所揭露內容，N-P邊界或阻障122將形成邊界，以防止磊晶層124擴展超出N-P邊界或阻障122到該結構的NFET側面110的鰭結構108周圍的區域中。如此，N-P邊界或阻障122將防止該結構的磊晶層124與NFET側面110的各元件之間的短路。此外，如熟習此領域技術者應可理解的是，鰭結構108上的間隙壁材料114將防止該磊晶材料在該結構的NFET側面110上生長。
圖6顯示在該結構的NFET側面110上形成磊晶材料126。例如，在圖6中，去除該結構的NFET側面110上的光罩，並在該結構的PFET側面106上形成光罩128。更具體而言，光罩128係在磊晶層124上 方形成。其後，間隙壁材料114係部分去除，以暴露該鰭結構108。在具體實施例中，例如，間隙壁材料114可透過氮化物蝕刻予以部分去除。該間隙壁蝕刻也將暴露該等鰭結構108的各部分。在該間隙壁蝕刻之後，該等鰭結構108將部分凹陷成低於間隙壁材料114的高度。在具體實施例中，該等鰭結構108的凹部可透過具有選擇性化學反應的RIE製程提供。從圖6所示應可瞭解，現在暴露出用於該結構的NFET側面110的鰭結構108，從而使其可用於後續磊晶生長。
請再參考圖6，磊晶生長製程係在形成磊晶層126(如n-EPI層)的鰭結構108的該等暴露部分上進行。依據本發明，N-P邊界或阻障122將防止磊晶層126擴展超出N-P邊界或阻障122到該裝置的PFET側面106的該等鰭結構104周圍的區域中。更具體而言，在所述製程的此階段，N-P邊界或阻障122將防止磊晶層126與磊晶層124合併。如此，防止該等裝置的短路。在生長製程之後，可透過任何習知去除製程(如氧氣灰化或其他剝離劑)將光罩128去除。
圖7顯示在進行去除N-P邊界或阻障122的選擇性步驟之後結果所致圖6的結構。如圖7所示，間隙壁材料114的一部分可保留在STI 112基材的上部表面上，以避免不必要的去除步驟。在具體實施例中，N-P邊界或阻障122可透過具有選擇性化學反應的RIE製程去除。
在以上說明的製程步驟之後，可使用依據習知製程(如離子植入)的該等磊晶層124和126形成源極和汲極區。在替代的具體實施例中，該等磊晶層124和126可為原位摻雜，以形成該等昇起式源極和汲極區。其後，透過熟習此領域技術者已知的習知微影、蝕刻和沉積等方法形成金屬化結構(如佈線結構)、內連線結構，以完成PFET裝置106和NFET裝置110的形成。
例如，可在該等磊晶層上方形成絕緣體層。形成在該等絕緣體層上方的光阻劑係暴露於能量(光)，以形成圖案化(開口)。具有選擇性化 學反應的蝕刻製程(如RIE)將用於透過該光阻劑的該等開口，在該絕緣體材料中形成一個或多個溝槽。然後該光阻劑可透過習知氧氣灰化製程或其他已知剝離劑去除。在去除該光阻劑之後，可透過任何習知沉積製程(如化學氣相沉積(CVD)製程)沉積導電材料。該絕緣體材料表面上的任何殘餘材料，皆可透過習知化學機械拋光(chemical mechanical polishing，簡稱CMP)製程去除。也應注意Vdd電源佈線通常係在處理期間在該等磊晶層之一上形成，其中阻障層118用於防止finFET結構上不需要的磊晶層擴展到與該Vdd電源佈線接觸。
如以上所說明的該(等)方法係用於製造積體電路晶片。該等所得到的積體電路晶片可由該業者以原始晶圓形式(即作為具有多個未封裝晶片的單一晶圓)、作為裸晶粒或以封裝形式分銷。在後者情況下，該晶片係安裝在單晶片封裝(例如塑料載體，具有貼附於主機板或其他更高層級載體的引線)或多晶片封裝(例如陶瓷載體，擇一具有表面內連線或嵌埋內連線或兩者)中。在任何情況下，該晶片隨後皆擇一作為(a)中間產品(例如主機板)或(b)最終產品的一部分與其他晶片、個別電路元件及/或其他信號處理裝置積體。該最終產品可為包括積體電路晶片的任何產品，範圍從玩具和其他低端應用到具有顯示器、鍵盤或其他輸入裝置和中央處理器的高端電腦產品皆包括。
為了例示目的已描述本發明的該等各種具體實施例的該等說明，但不欲為全面性或限於所揭示的該等具體實施例。對此領域一般技術者而言，將顯而易見許多修飾例和變化例，而不悖離該等所說明的具體實施例的範疇與精神。本說明書使用的術語經過選擇，以最佳解說該等具體實施例的該等原理、該整個市場上所找到的技術的實際應用或技術改進，或讓此領域一般技術者能理解本說明書所揭示的該等具體實施例。

Claims (20)

  1. 一種方法包含：形成複數個第一鰭結構；在該等鰭結構的一第一鰭結構與該等複數個鰭結構的一第二鰭結構之間形成一阻障層；及在該第一鰭結構上形成一磊晶材料，同時透過形成在該第一鰭結構與該第二鰭結構之間的阻障層，阻擋該磊晶材料延伸到該第二鰭結構上。
  2. 如申請專利範圍第1項所述之方法，其更包含在該第二鰭結構上方形成一絕緣體層和阻障材料，其防止該磊晶材料在該第二鰭結構上形成。
  3. 如申請專利範圍第1項所述之方法，其中該阻障層防止形成在該第一鰭結構上的磊晶材料延伸到另一裝置的一區域。
  4. 如申請專利範圍第3項所述之方法，其中該形成磊晶材料係形成在該第一鰭結構的暴露半導體材料上的一生長製程。
  5. 如申請專利範圍第4項所述之方法，其更包含：在形成該阻障層之前，在該第一鰭結構和該第二鰭結構上形成一絕緣體材料；在形成該阻障層之前，在該第二鰭結構上方形成一光罩材料；在形成該阻障層之前，在該第一鰭結構和該光罩材料上沉積用於該阻障層的一阻障材料；及去除該光罩材料和該第一鰭結構上的阻障材料的水平部分，以形成該第一鰭結構的阻障層和間隙壁。
  6. 如申請專利範圍第5項所述之方法，其中該第一鰭結構的暴露半導體材料更包含去除該第一鰭結構上的絕緣體材料的一部分，接著去除該暴露半導體材料的一凹部。
  7. 如申請專利範圍第5項所述之方法，其中該阻障層和該間隙壁係在一單一蝕刻步驟中形成。
  8. 如申請專利範圍第1項所述之方法，其更包含在該第二鰭結構上形成一磊晶材料，同時保護該第一鰭結構上的磊晶材料。
  9. 如申請專利範圍第8項所述之方法，其更包含：在形成該阻障層之前，在該第一鰭結構和該第二鰭結構上形成一絕緣體材料；在形成該阻障層之前，在該第二鰭結構上方形成一光罩材料；在形成該阻障層之前，在該第一鰭結構和該光罩材料上沉積用於該阻障層的一阻障材料；去除該光罩材料和該第一鰭結構上的阻障材料的水平部分，以形成用於該第一鰭結構的阻障層和間隙壁；去除該絕緣體材料的各部分，以暴露該第一鰭結構的半導體材料；在該第一鰭結構的暴露部分上形成該磊晶材料，同時該絕緣體材料和該阻障材料係在該第二鰭結構上；保護該磊晶材料，同時暴露該第二鰭結構的半導體材料；及在該第二鰭結構上形成磊晶材料，同時形成在該第一鰭結構與該第二鰭結構之間的阻障層防止該第二鰭結構上的磊晶材料在該第一鰭結構上的磊晶材料上擴展。
  10. 如申請專利範圍第1項所述之方法，其中該第一鰭結構係一第一裝置，且第二鰭結構係一第二裝置。
  11. 如申請專利範圍第1項所述之方法，其中該阻障層係由一金屬氧化物或一金屬氮化物所構成。
  12. 如申請專利範圍第11項所述之方法，其中該金屬氧化物係Al 2O 3。
  13. 一種方法包含：形成用於一第一裝置類型的一第一鰭結構；形成用於相鄰該第一裝置類型的一第二裝置類型的一第二鰭結構；在該第一鰭結構上方形成一光罩；在該第二鰭結構和該光罩上形成一阻障材料；部分去除該阻障材料，以在該第二鰭結構的一側壁和該光罩的一側壁上留下一阻障材料；去除該光罩，以在該第一裝置類型與該第二裝置類型之間的一邊界形成一垂直阻障層；及在該第二鰭結構上生長一磊晶層，同時該垂直阻障層防止該磊晶層延伸超出該邊界。
  14. 如申請專利範圍第13項所述之方法，其中該第一裝置類型和該第二裝置類型係不同類型的裝置。
  15. 如申請專利範圍第13項所述之方法，其中該部分去除該阻障材料在該第二鰭結構上形成一間隙壁。
  16. 如申請專利範圍第13項所述之方法，其更包含從沉積在該第二鰭結構上的阻障材料在該第二鰭結構的側壁上形成一間隙壁材料，接著進行一凹部蝕刻製程。
  17. 如申請專利範圍第13項所述之方法，其中該阻障材料係由一金屬氧化物或金屬氮化物構成。
  18. 如申請專利範圍第17項所述之方法，其中該金屬氧化物係Al 2O 3。
  19. 一種中間結構包含：一第一裝置的一第一鰭結構；一第二裝置的一第二鰭結構，其相鄰該第一鰭結構；一阻障材料，其在該第一裝置與該第二裝置之間的一邊界；及一磊晶材料，其在該第一裝置的邊界內的第一鰭結構上，及該第二裝置的邊界內的第二鰭結構上的磊晶材料，其中該阻障材料係結構化，以防止該第一鰭結構和該第二鰭結構的磊晶材料合併在一起及延伸超出該邊界。
  20. 如申請專利範圍第19項所述之中間結構，其中該阻障材料係金屬氧化物Al 2O 3。
TW106142397A 2017-06-22 2017-12-04 具邊界間隙壁的半導體結構及其製造方法 TWI666692B (zh)

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