JP2010537433A - 異なる高さの隣接シリコンフィンを製造する方法 - Google Patents
異なる高さの隣接シリコンフィンを製造する方法 Download PDFInfo
- Publication number
- JP2010537433A JP2010537433A JP2010522100A JP2010522100A JP2010537433A JP 2010537433 A JP2010537433 A JP 2010537433A JP 2010522100 A JP2010522100 A JP 2010522100A JP 2010522100 A JP2010522100 A JP 2010522100A JP 2010537433 A JP2010537433 A JP 2010537433A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- layer
- isolation structure
- fin
- silicon fin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 157
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 157
- 239000010703 silicon Substances 0.000 title claims abstract description 157
- 238000000034 method Methods 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 49
- 238000005530 etching Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- -1 carbon-doped oxide Chemical compound 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 241001417523 Plesiopidae Species 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 1
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (20)
- 半導体基板上に第1及び第2のシリコンフィンを形成する工程であり、各シリコンフィンがその頂面に分離構造を含む、工程;
前記半導体基板上に絶縁層を堆積する工程;
前記第1のシリコンフィンをマスクするが前記第2のシリコンフィンをマスクしないマスク構造を形成する工程;
前記第2のシリコンフィンの頂部から前記分離構造を除去する工程;
前記第2のシリコンフィンの頂面にシリコン層をエピタキシャル成長させることによって、前記第2のシリコンフィンを延長する工程;及び
前記絶縁層の少なくとも一部を除去する工程;
を有する方法。 - 前記分離構造は、窒化物及び酸窒化物からなる群から選択された材料を有する、請求項1に記載の方法。
- 前記分離構造は、およそ10nmと100nmとの間の厚さを有する、請求項2に記載の方法。
- 前記絶縁層は二酸化シリコンを有する、請求項1に記載の方法。
- 前記マスク構造は窒化シリコンを有する、請求項1に記載の方法。
- 前記第2のシリコンフィンの頂部から前記分離構造を除去する工程は、ウェット化学エッチングを適用して前記分離構造を除去することを有する、請求項1に記載の方法。
- 前記絶縁層の少なくとも一部を除去する工程に先立って、前記マスク構造を除去する工程を更に有する請求項1に記載の方法。
- エピタキシャル成長された前記シリコン層を平坦化して余分なシリコンを除去する工程、を更に有する請求項1に記載の方法。
- 前記マスク構造を形成する工程の前に、前記分離構造の頂面を露出させるように前記絶縁層を平坦化する工程を更に有する請求項1に記載の方法。
- 上に分離層が堆積されたシリコン基板を供給する工程;
前記分離層をパターニングして第1の分離構造及び第2の分離構造を形成する工程;
前記シリコン基板をパターニングして、前記第1の分離構造の下の第1のシリコンフィンと前記第2の分離構造の下の第2のシリコンフィンとを形成する工程;
前記半導体基板上に絶縁層を堆積する工程;
前記絶縁層を平坦化して、前記第1の分離構造の頂面と前記第2の分離構造の頂面とを露出させる工程;
前記絶縁層上にマスク層を堆積する工程;
前記マスク層をパターニングして、前記第1の分離構造をマスクするが前記第2の分離構造をマスクしないマスク構造を形成する工程;
ウェット化学エッチングを適用し、前記第2の分離構造を除去して前記第2のシリコンフィンを露出させる工程;
前記第2のシリコンフィン上にシリコン層をエピタキシャル成長させる工程;及び
前記絶縁層を後退させ、前記第1のシリコンフィンの少なくとも一部と前記第2のシリコンフィンの少なくとも一部とを露出させる工程;
を有する方法。 - 前記第1のシリコンフィン及び前記第2のシリコンフィンを覆う共形の誘電体層を堆積する工程;
前記共形の誘電体層上に電極層を堆積する工程;及び
前記電極層及び前記誘電体層をパターニングして、前記第1のシリコンフィン上の第1のゲート誘電体層及び第1のゲート電極と、前記第2のシリコンフィン上の第2のゲート誘電体層及び第2のゲート電極とを形成する工程;
を更に有する請求項10に記載の方法。 - エピタキシャル成長された前記シリコン層を平坦化して余分なシリコンを除去する工程、を更に有する請求項10に記載の方法。
- 前記分離層は窒化物層又は酸窒化物層を有する、請求項10に記載の方法。
- 前記マスク層は窒化シリコンを有する、請求項10に記載の方法。
- 前記共形の誘電体層はhigh−k誘電体層を有する、請求項11に記載の方法。
- 前記電極層はポリシリコン層又は金属層を有する、請求項11に記載の方法。
- シリコン基板;
前記シリコン基板上に形成され、第1の高さを有する第1のシリコンフィン;及び
前記シリコン基板上に形成され、前記第1の高さより大きい第2の高さを有する第2のシリコンフィン;
を有する装置。 - 前記第1のシリコンフィンと前記第2のシリコンフィンとの間の高さの差は、前記第2のシリコンフィン上にシリコン層をエピタキシャル成長させることによって作り出されている、請求項17に記載の装置。
- 前記第1のシリコンフィン及び前記第2のシリコンフィンの各々上に形成されたゲート誘電体層及びゲート電極、を更に有する請求項17に記載の装置。
- 前記第1のシリコンフィンは前記第2のシリコンフィンに隣接している、請求項17に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/848,235 US20090057846A1 (en) | 2007-08-30 | 2007-08-30 | Method to fabricate adjacent silicon fins of differing heights |
US11/848,235 | 2007-08-30 | ||
PCT/US2008/074161 WO2009032576A2 (en) | 2007-08-30 | 2008-08-25 | Method to fabricate adjacent silicon fins of differing heights |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010537433A true JP2010537433A (ja) | 2010-12-02 |
JP5230737B2 JP5230737B2 (ja) | 2013-07-10 |
Family
ID=40406106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010522100A Active JP5230737B2 (ja) | 2007-08-30 | 2008-08-25 | 異なる高さの隣接シリコンフィンを製造する方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090057846A1 (ja) |
JP (1) | JP5230737B2 (ja) |
KR (1) | KR101248339B1 (ja) |
CN (1) | CN101779284B (ja) |
GB (1) | GB201003532D0 (ja) |
WO (1) | WO2009032576A2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197589A (ja) * | 2012-03-19 | 2013-09-30 | Samsung Electronics Co Ltd | 電界効果トランジスタの製造方法 |
JP2014179604A (ja) * | 2013-03-11 | 2014-09-25 | Renesas Electronics Corp | フィンfet構造を有する半導体装置及びその製造方法 |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8048723B2 (en) | 2008-12-05 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs having dielectric punch-through stoppers |
US8106459B2 (en) | 2008-05-06 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having dielectric punch-through stoppers |
US8263462B2 (en) | 2008-12-31 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric punch-through stoppers for forming FinFETs having dual fin heights |
US8293616B2 (en) | 2009-02-24 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of fabrication of semiconductor devices with low capacitance |
US8592320B2 (en) * | 2011-08-15 | 2013-11-26 | Nanya Technology Corporation | Method for forming fin-shaped semiconductor structure |
US8759904B2 (en) * | 2011-08-24 | 2014-06-24 | GlobalFoundries, Inc. | Electronic device having plural FIN-FETs with different FIN heights and planar FETs on the same substrate |
CN103000517B (zh) * | 2011-09-09 | 2016-02-10 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
CN103021851B (zh) * | 2011-09-21 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | 一种多栅极场效应晶体管的制作方法 |
US9893163B2 (en) * | 2011-11-04 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D capacitor and method of manufacturing same |
CN103137445B (zh) * | 2011-12-05 | 2015-12-02 | 中芯国际集成电路制造(上海)有限公司 | 形成Finfet掺杂鳍状物的方法 |
US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
US20130302954A1 (en) * | 2012-05-10 | 2013-11-14 | Globalfoundries Inc. | Methods of forming fins for a finfet device without performing a cmp process |
US8927432B2 (en) * | 2012-06-14 | 2015-01-06 | International Business Machines Corporation | Continuously scalable width and height semiconductor fins |
US8673718B2 (en) * | 2012-07-09 | 2014-03-18 | Globalfoundries Inc. | Methods of forming FinFET devices with alternative channel materials |
US9142400B1 (en) * | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
US9728464B2 (en) | 2012-07-27 | 2017-08-08 | Intel Corporation | Self-aligned 3-D epitaxial structures for MOS device fabrication |
CN103594344A (zh) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | 多高度FinFET器件的制造方法 |
CN103632978B (zh) * | 2012-08-29 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104022082B (zh) * | 2013-02-28 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | 静态存储单元及其形成方法 |
CN104022116B (zh) * | 2013-02-28 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | 静态存储单元及其形成方法 |
US9159576B2 (en) | 2013-03-05 | 2015-10-13 | Qualcomm Incorporated | Method of forming finFET having fins of different height |
US9178066B2 (en) * | 2013-08-30 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Limited | Methods for forming a semiconductor arrangement with structures having different heights |
KR102146469B1 (ko) | 2014-04-30 | 2020-08-21 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
US9508743B2 (en) * | 2014-10-28 | 2016-11-29 | Globalfoundries Inc. | Dual three-dimensional and RF semiconductor devices using local SOI |
CN104409356B (zh) * | 2014-11-28 | 2017-12-05 | 上海华力微电子有限公司 | 形成鳍式场效应晶体管的方法 |
US9269628B1 (en) * | 2014-12-04 | 2016-02-23 | Globalfoundries Inc. | Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices |
EP3182461B1 (en) * | 2015-12-16 | 2022-08-03 | IMEC vzw | Method for fabricating finfet technology with locally higher fin-to-fin pitch |
CN107579108B (zh) * | 2016-07-04 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN110045460B (zh) * | 2019-05-31 | 2020-11-27 | 中国科学院微电子研究所 | 一种光波导的制造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188273A (ja) * | 2001-12-13 | 2003-07-04 | Tadahiro Omi | 相補型mis装置 |
JP2005251873A (ja) * | 2004-03-02 | 2005-09-15 | National Institute Of Advanced Industrial & Technology | 半導体集積回路およびその製造方法 |
WO2005104238A1 (de) * | 2004-04-27 | 2005-11-03 | Infineon Technologies Ag | Fin-feldeffekttransistor-anordnung und verfahren zum herstellen einer fin-feldeffekttransistor-anordnung |
JP2007149942A (ja) * | 2005-11-28 | 2007-06-14 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2007201021A (ja) * | 2006-01-24 | 2007-08-09 | Toshiba Corp | 半導体装置 |
JP2008124423A (ja) * | 2006-10-20 | 2008-05-29 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US20080230852A1 (en) * | 2007-03-06 | 2008-09-25 | Chen-Hua Yu | Fabrication of FinFETs with multiple fin heights |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6642090B1 (en) * | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US6909147B2 (en) * | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
US6911383B2 (en) * | 2003-06-26 | 2005-06-28 | International Business Machines Corporation | Hybrid planar and finFET CMOS devices |
US6835618B1 (en) * | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
US7224029B2 (en) * | 2004-01-28 | 2007-05-29 | International Business Machines Corporation | Method and structure to create multiple device widths in FinFET technology in both bulk and SOI |
US7196380B2 (en) * | 2005-01-13 | 2007-03-27 | International Business Machines Corporation | High mobility plane FinFET with equal drive strength |
US7456055B2 (en) * | 2006-03-15 | 2008-11-25 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor fins |
US7638843B2 (en) * | 2006-05-05 | 2009-12-29 | Texas Instruments Incorporated | Integrating high performance and low power multi-gate devices |
US7544994B2 (en) * | 2006-11-06 | 2009-06-09 | International Business Machines Corporation | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure |
EP2073267A1 (en) * | 2007-12-19 | 2009-06-24 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | Method of fabricating multi-gate semiconductor devices and devices obtained |
-
2007
- 2007-08-30 US US11/848,235 patent/US20090057846A1/en not_active Abandoned
-
2008
- 2008-08-25 WO PCT/US2008/074161 patent/WO2009032576A2/en active Application Filing
- 2008-08-25 JP JP2010522100A patent/JP5230737B2/ja active Active
- 2008-08-25 CN CN2008801032765A patent/CN101779284B/zh not_active Expired - Fee Related
- 2008-08-25 KR KR1020107004529A patent/KR101248339B1/ko active IP Right Grant
-
2010
- 2010-03-03 GB GBGB1003532.7A patent/GB201003532D0/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188273A (ja) * | 2001-12-13 | 2003-07-04 | Tadahiro Omi | 相補型mis装置 |
JP2005251873A (ja) * | 2004-03-02 | 2005-09-15 | National Institute Of Advanced Industrial & Technology | 半導体集積回路およびその製造方法 |
WO2005104238A1 (de) * | 2004-04-27 | 2005-11-03 | Infineon Technologies Ag | Fin-feldeffekttransistor-anordnung und verfahren zum herstellen einer fin-feldeffekttransistor-anordnung |
JP2007149942A (ja) * | 2005-11-28 | 2007-06-14 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2007201021A (ja) * | 2006-01-24 | 2007-08-09 | Toshiba Corp | 半導体装置 |
JP2008124423A (ja) * | 2006-10-20 | 2008-05-29 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US20080230852A1 (en) * | 2007-03-06 | 2008-09-25 | Chen-Hua Yu | Fabrication of FinFETs with multiple fin heights |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197589A (ja) * | 2012-03-19 | 2013-09-30 | Samsung Electronics Co Ltd | 電界効果トランジスタの製造方法 |
JP2014179604A (ja) * | 2013-03-11 | 2014-09-25 | Renesas Electronics Corp | フィンfet構造を有する半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20090057846A1 (en) | 2009-03-05 |
CN101779284B (zh) | 2013-04-24 |
GB201003532D0 (en) | 2010-04-21 |
JP5230737B2 (ja) | 2013-07-10 |
KR101248339B1 (ko) | 2013-04-01 |
WO2009032576A2 (en) | 2009-03-12 |
WO2009032576A3 (en) | 2009-05-07 |
CN101779284A (zh) | 2010-07-14 |
KR20100049621A (ko) | 2010-05-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5230737B2 (ja) | 異なる高さの隣接シリコンフィンを製造する方法 | |
US9589845B1 (en) | Fin cut enabling single diffusion breaks | |
US8039326B2 (en) | Methods for fabricating bulk FinFET devices having deep trench isolation | |
US8796156B2 (en) | Cross OD FinFET patterning | |
TWI505402B (zh) | 在塊體半導體材料上形成隔離鰭結構的方法 | |
US7824983B2 (en) | Methods of providing electrical isolation in semiconductor structures | |
US20180005895A1 (en) | Vertical transistor with variable gate length | |
TWI706450B (zh) | 半導體裝置與其形成方法 | |
EP2455967B1 (en) | A method for forming a buried dielectric layer underneath a semiconductor fin | |
TW201719769A (zh) | 鰭式場效電晶體的製作方法 | |
US9425053B2 (en) | Block mask litho on high aspect ratio topography with minimal semiconductor material damage | |
EP2311077A1 (en) | Method of forming finned semiconductor devices with trench isolation | |
TWI725557B (zh) | 半導體裝置的製造方法 | |
US20040157396A1 (en) | Methods for forming double gate electrodes using tunnel and trench | |
TW201905981A (zh) | 邊界間隙壁結構及積體化 | |
WO2019007335A1 (zh) | 半导体器件及其制备方法 | |
US7879726B2 (en) | Methods of forming semiconductor devices using selective etching of an active region through a hardmask | |
US8269307B2 (en) | Shallow trench isolation structure and method for forming the same | |
TW202240912A (zh) | 半導體裝置 | |
CN105826200A (zh) | 晶体管及其形成方法 | |
CN109300972A (zh) | Finfet器件及其形成方法 | |
KR20090002655A (ko) | 반도체 소자 제조 방법 | |
KR100629694B1 (ko) | 반도체 소자 제조 방법 | |
KR20220020761A (ko) | 갭충전 구조물 및 그 제조 방법 | |
CN113690185A (zh) | 半导体结构及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120518 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120529 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120824 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120831 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120925 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121030 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130122 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130219 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130319 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160329 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5230737 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |