WO2019007335A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2019007335A1
WO2019007335A1 PCT/CN2018/094316 CN2018094316W WO2019007335A1 WO 2019007335 A1 WO2019007335 A1 WO 2019007335A1 CN 2018094316 W CN2018094316 W CN 2018094316W WO 2019007335 A1 WO2019007335 A1 WO 2019007335A1
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layer
region
dielectric layer
semiconductor device
forming
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PCT/CN2018/094316
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English (en)
French (fr)
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金华俊
孙贵鹏
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无锡华润上华科技有限公司
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Priority to US16/462,432 priority Critical patent/US10811520B2/en
Publication of WO2019007335A1 publication Critical patent/WO2019007335A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of fabricating the same.
  • MOS metal oxide semiconductor field effect transistor
  • a semiconductor device and a method of fabricating the same are provided in accordance with various embodiments of the present application.
  • a method of fabricating a semiconductor device comprising:
  • first dielectric layer and a second dielectric layer on the polysilicon layer, in the first opening, and in the second opening, and forming a source region sidewall on the sidewall of the first opening, in the second opening
  • the sidewall of the drain forms a side wall of the drain
  • a semiconductor device including:
  • a semiconductor substrate having a well region and a channel region in the well region
  • a gate oxide layer and a polysilicon layer on the semiconductor substrate and a first opening for forming a source region and a second opening for forming a drain region disposed on the gate oxide layer and the polysilicon layer;
  • a source side wall of the first opening sidewall and a drain side wall of the second opening sidewall wherein the source side wall is the first dielectric layer
  • the drain side wall Including a first dielectric layer and a second dielectric layer stacked in sequence
  • FIG. 1 is a flow chart showing a method of fabricating a semiconductor device in an embodiment
  • 2A-2J are schematic cross-sectional views of devices respectively obtained by successively performing steps of a method in accordance with an embodiment.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device in an embodiment, and a method of fabricating a semiconductor device, comprising the steps of:
  • Step S110 forming a well region in the semiconductor substrate and forming a channel region in the well region, and forming a gate oxide layer and a polysilicon layer on the well region.
  • a semiconductor substrate 200 is provided.
  • the constituent material of the semiconductor substrate 200 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), and silicon on insulator ( SSOI), silicon germanium (S-SiGeOI) on insulator, silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the semiconductor substrate 200 is selected from a P-type semiconductor substrate 200.
  • the semiconductor substrate 200 is oxidized, a buffer layer (silicon oxide layer, not shown) is formed, a silicon nitride layer is deposited on the buffer layer, the well region 201 is defined by photolithography, and is ion-etched by reactive ions.
  • the silicon oxide layer is etched, and phosphorus P+ is first implanted into the semiconductor substrate 200 by ion implantation, and then arsenic As+ is formed to form the N-type well region 201.
  • the conductivity type of the semiconductor substrate and the conductivity type of the well region 201 located in the semiconductor substrate 200 may be set according to actual needs, and are not limited thereto.
  • the channel region 202 is also formed by ion implantation or other means within the well region 201.
  • gate oxide layer 210 is formed on semiconductor substrate 200 by a thermal oxidation or chemical oxidation process.
  • the gate oxide layer 210 includes a first gate oxide layer 211 region corresponding to the source region in the vertical direction and a second gate oxide layer 213 region corresponding to the drain region in the vertical direction; wherein the first gate oxide layer 211 The thickness of the region is smaller than the thickness of the region of the second gate oxide layer 213.
  • the thickness of the first gate oxide layer 211 region is 15 nm, and the thickness of the second gate oxide layer 213 region is 44 nm. Since the thickness of the second gate oxide layer 213 is higher than the thickness of the first gate oxide layer 211, leakage can be improved.
  • the voltage of the zone A high voltage metal oxide semiconductor field effect transistor (MOS) device can be formed by forming gate oxide layers 210 of different thicknesses in different regions.
  • MOS metal oxide semiconductor field effect transistor
  • the method for fabricating a semiconductor device further includes the step of forming a polysilicon layer 220 on the gate oxide layer 210, wherein the method of forming the polysilicon layer 220 may employ a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor phase. Deposition, fast thermal chemical vapor deposition plasma enhanced chemical vapor deposition.
  • a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor phase. Deposition, fast thermal chemical vapor deposition plasma enhanced chemical vapor deposition.
  • the thickness of the polysilicon layer 220 is 180 to 220 nm. In the present embodiment, the thickness of the polysilicon layer 220 is 200 nm.
  • Step S120 etching a portion of the gate oxide layer and the polysilicon layer and exposing a first opening for forming a source region and a second opening for forming a drain region.
  • a portion of the gate oxide layer 210 and the polysilicon layer 220 are simultaneously etched to form a first opening 221 and a second opening 223.
  • the bottom surface of the first opening 221 is a top surface of the partial channel region 202.
  • the first opening 221 defines a position of the source wall and the source region.
  • the second opening 223 is separated from the first opening 221, and
  • the bottom surface of the second opening 223 is the top surface of the well region 201, and the second opening 223 can define the position of the drain side wall and the drain region.
  • the process steps of forming the first opening 221 and the second opening 223 include: forming a mask layer having a pattern of the first opening 221 and the second opening 223 on the polysilicon layer 220, and forming a mask by a conventional photolithography and etching process
  • the mask layer may be a single layer structure or a multilayer structure, the mask layer having a single layer structure is a patterned photoresist layer, and the mask layer having a multilayer structure may include patterning from bottom to top.
  • the advanced patterned layer, the anti-reflective coating and the photoresist layer; the mask layer is used as a mask, while the gate oxide layer 210 and the polysilicon layer 220 are etched, and the first opening 221 is formed in the gate oxide layer 210 and the polysilicon layer 220.
  • the second opening 223, the etching may be a conventional anisotropic dry etching; the mask layer may be removed, the mask layer may be removed by a conventional ashing process; and the wet cleaning may be performed to remove by-products and impurities generated by the etching. .
  • the channel region 202 in the well region 201 may also be formed by ion implantation from the first opening 221 after the first opening 221 is formed.
  • Step S130 forming a first dielectric layer on the polysilicon layer, in the first opening, in the second opening, forming a second dielectric layer on the first dielectric layer, and forming a source region on a sidewall of the first opening a side wall, a side wall of the drain region is formed on a sidewall of the second opening.
  • a first dielectric layer 230 is formed on the polysilicon layer 220 (not shown), the first opening 221, and the second opening 223, wherein the first dielectric layer 230 is formed in the first opening.
  • the sidewalls and the bottom surface of the second dielectric layer 230 are formed on the sidewalls and the bottom surface of the second opening 223 but do not fill the first opening 221 and the second opening 223.
  • a second dielectric layer 240 is formed on the basis of the first dielectric layer 230 (not shown).
  • the thickness of the second dielectric layer 240 is greater than the thickness of the first dielectric layer 230.
  • the method of forming the first dielectric layer 230 and the second dielectric layer 240 may employ chemical vapor deposition such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition plasma enhanced chemical vapor deposition.
  • the first dielectric layer 230 is an oxide layer having a thickness ranging from 8 to 12 nanometers.
  • the second dielectric layer 240 is a silicon nitride layer; the silicon nitride layer has a thickness ranging from 80 to 120 nanometers.
  • the silicon nitride layer and the oxide layer are etched by photolithography, etching, etc. to form a source region sidewall 241 and a drain region spacer 243, except for the source region sidewall 241 and
  • the silicon nitride layer and the oxide layer outside the drain side wall 243 are all etched away to expose the polysilicon layer 220.
  • the silicon nitride layer and the oxide layer in the middle portion of the first opening 221 are also etched into the channel region 202, and a portion of the channel region 202 is exposed.
  • a portion of the silicon nitride layer and oxide layer within the second opening 223 are etched into the well region 201 and expose the well region 201.
  • the etch can be an anisotropic dry etch or/and a wet etch.
  • Step S140 forming a dielectric oxide layer on the polysilicon layer, etching and retaining the dielectric oxide layer on the sidewall of the drain region.
  • a dielectric oxide layer 250 is formed on the polysilicon layer 220 by deposition, wherein the dielectric oxide layer 250 is also formed on the sidewall of the source region spacer 241, the bottom of the first opening 221 (channel region 202). The dielectric oxide layer 250 is also formed on the sidewall of the drain side wall 243 and the bottom of the second opening 223 (well region 201).
  • the photolithographic plate of the dielectric oxide layer 250 is used to lithography and etch the barrier layer to protect the drain region sidewall 243 from being etched away. That is, the dielectric oxide layer 250 on the drain side wall 243 is not etched, the drain side wall 243 includes a double layer structure of silicon nitride and dielectric oxide layer, and the drain side wall 243 can reduce the electric field strength of the drain end. Conducive to the breakdown characteristics of the device.
  • the dielectric oxide layer 250 may be a silicon dioxide layer.
  • Step S150 removing the second dielectric layer in the side wall of the source region and retaining the first dielectric layer.
  • the second dielectric layer 240 (silicon nitride layer) of the source region (having one end of the channel region 202) side wall 241 is floated by wet rinsing.
  • the dielectric layer in the source side wall 241 is such that only the first dielectric layer 230 (oxide layer) is a layer of medium. That is, the lateral thickness of the source side wall 241 (which may also be referred to as the thickness of the first dielectric layer 230) is reduced relative to the lateral thickness of the drain side wall 243 without changing the structure of the drain region.
  • the pitch of the polysilicon layer is to be reduced, the width of the sidewall spacer is reduced.
  • the side wall of the source area and the side wall of the drain area are simultaneously formed. If the width of the side wall of the source area or the drain area is reduced, the electric field strength of the drain area will decrease with the side wall of the drain area. Small and enhanced, which in turn affects the semiconductor device's leakage increase in the off state.
  • the lateral thickness of the source side wall is reduced, and the pitch of the polysilicon layer 220 corresponding to the source region is shortened, thereby reducing the size of the entire semiconductor device and reducing the on-resistance of the semiconductor device. .
  • the lithographic layer of the existing lithography layer is used to form the barrier layer, and the double-layer dielectric layer in the sidewall spacer 243 is retained, thereby reducing the process cost, and at the same time ensuring that the electric field in the drain region does not change and does not affect the semiconductor device.
  • Original features are used to form the barrier layer, and the double-layer dielectric layer in the sidewall spacer 243 , thereby reducing the process cost, and at the same time ensuring that the electric field in the drain region does not change and does not affect the semiconductor device.
  • the method of fabricating the semiconductor device before the step S140 forms the dielectric oxide layer 250 on the polysilicon layer 220, the method of fabricating the semiconductor device further includes the step of forming the source region 203 and the drain region 204 in the well region 201.
  • the method of fabricating a semiconductor device further includes forming a source region 203 and a drain region 204 in a semiconductor substrate by a phosphorus ion or arsenic ion implantation process. Since the source region 203 and the channel region 202 in the semiconductor substrate are both formed before the step S150, the impurity distribution of the source region is not affected.
  • step S150 further comprising forming an interlayer dielectric layer on the polysilicon layer; A step of forming a contact hole in the interlayer dielectric layer.
  • a method of fabricating a semiconductor device further includes forming a first interlayer dielectric layer 260 and a second interlayer dielectric layer 270 on a semiconductor substrate.
  • the materials of the first interlayer dielectric layer 260 and the second interlayer dielectric layer 270 have a low dielectric constant material including, but not limited to, a silicic acid having a k value of 2.5 to 2.9.
  • the first interlayer dielectric layer 260 and the second interlayer dielectric layer 270 may be formed by chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like. As shown in FIG.
  • the method of fabricating a semiconductor device further includes forming a contact hole 261 penetrating through the first interlayer dielectric layer 260 and the second interlayer dielectric layer 270 by a photolithography and etching process.
  • a mask layer having a pattern of contact holes 261 is formed on the second interlayer dielectric layer 270, and the first interlayer dielectric layer 260 and the second interlayer dielectric layer 270 are etched by using the mask layer as a mask.
  • a contact hole 261 exposing the source region 203 and the drain region 204 is formed in the first interlayer dielectric layer 260 and the second interlayer dielectric layer 270.
  • a metal layer is filled in the via hole to form a metal. Connection line.
  • the conventional drain side wall includes a first dielectric layer and a second dielectric layer (silicon nitride layer), and the silicon nitride layer is corroded when the silicon nitride of the sidewall of the drain region is etched during the formation of the contact hole.
  • the lower rate may cause the contact hole not to etch through to the source region.
  • the (silicon nitride layer) contact needs to ensure that the distance between the contact hole 261 and the polysilicon layer 220 is greater than the width of the source region side wall 241 or the drain region spacer 243. Since the second dielectric layer 240 (silicon nitride layer) in the source region sidewall 241 is floated, the smaller the width of the source region spacer 241, the smaller the distance between the contact hole 261 and the polysilicon layer 220, and the polysilicon layer. The spacing of 220 is also smaller.
  • the semiconductor device prepared by the above method may be an N-type MOS transistor, a P-type MOS transistor, a high voltage MOS transistor, or the like.
  • the lateral thickness of the source side wall can be reduced, the pitch of the polysilicon layer 220 corresponding to the source region can be shortened, the size of the entire semiconductor device can be reduced, and the on-resistance of the semiconductor device can be reduced.
  • the existing barrier layer retains the double-layer dielectric layer in the sidewall spacer 243, which reduces the process cost, and at the same time ensures that the electric field in the drain region does not change and does not affect the original characteristics of the semiconductor device.
  • the semiconductor device includes a semiconductor substrate (not shown) having a well region 201 and a channel region 202 located in the well region 201. a gate oxide layer 210 and a polysilicon layer 220 on the semiconductor substrate, and a first opening (not labeled) for forming the source region 203 disposed on the gate oxide layer 210 and the polysilicon layer 220 a second opening (not labeled) for forming the drain region 204; a source region sidewall 241 at the sidewall of the first opening; and a drain sidewall spacer 243 at the sidewall of the second opening, wherein the source
  • the side wall 241 includes the first dielectric layer 230
  • the drain side wall 243 includes a first dielectric layer 230 and a second dielectric layer 240 which are sequentially stacked; and a dielectric oxide layer on the side wall 243 of the drain region. 250.
  • the first dielectric layer 230 is an oxide layer and the second dielectric layer 240 is a silicon nitride layer.
  • the thickness of the oxide layer ranges from 8 to 12 nanometers; and the thickness of the silicon nitride layer ranges from 80 to 120 nanometers.
  • the semiconductor device further includes a source region 203 and a drain region 204 located within the well region 201, and the source region 203 and the drain region 204 are formed by a phosphorus ion or arsenic ion implantation process.
  • the source area is corresponding to the first opening
  • the drain area is corresponding to the second opening.
  • the semiconductor device further includes an interlayer dielectric layer 260 on the polysilicon layer 220, and a contact hole 261 in the interlayer dielectric layer 260.
  • the material of the interlayer dielectric layer 260 may be a material having a low dielectric constant including, but not limited to, a silicate compound having a k value of 2.5 to 2.9 (Hydrogen Silsesquioxane, abbreviated as HSQ), A methyl silicate compound (Methyl Silsesquioxane, MSQ for short) having a k value of 2.2, a porous silica formed by a chemical vapor deposition method, or the like.
  • the interlayer dielectric layer 260 may be formed by a chemical vapor deposition method such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like.
  • a contact hole 261 penetrating the interlayer dielectric layer 260 is formed by a photolithography and etching process.
  • a mask layer having a pattern of contact holes 261 is formed on the interlayer dielectric layer 260, with the mask layer as a mask, the interlayer dielectric layer 260 is etched, and the well region 201 is exposed in the interlayer dielectric layer 260.
  • a metal layer is filled in the via holes to form metal connection lines.
  • the distance between the contact hole 261 and the polysilicon layer 220 is greater than the source side wall 241 or the drain side.
  • the width of the wall 243 The smaller the width of the source side wall 241 or the drain side wall 243, the smaller the distance between the contact hole 261 and the polysilicon layer 220, and the smaller the pitch of the polysilicon layer 220.
  • the semiconductor device may be an N-type MOS transistor, a P-type MOS transistor, a high voltage MOS transistor, or the like.
  • the semiconductor device reduces the lateral thickness of the source side wall and shortens the pitch of the polysilicon layer 220 corresponding to the source region, thereby reducing the size of the entire semiconductor device and reducing the on-resistance of the semiconductor device.
  • the existing barrier layer retains the double-layer dielectric layer in the sidewall of the drain region, which reduces the process cost, and at the same time ensures that the electric field in the drain region does not change and does not affect the original characteristics of the semiconductor device.

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Abstract

一种半导体器件的制备方法，包括：在半导体衬底(200)内形成阱区(201)以及在阱区(201)内形成沟道区(202)，并在阱区(201)上形成栅氧化层(210)和多晶硅层(220)；刻蚀部分栅氧化层(210)和多晶硅层(220)并露出用于形成源区的第一开口(221)和用于形成漏区的第二开口(223)；在多晶硅层(220)上、第一开口(221)内、第二开口(223)内依次形成第一介质层(230)和第二介质层(240)，并在第一开口(221)的侧壁形成源区侧墙，在第二开口(223)的侧壁形成漏区侧墙；在多晶硅层(220)上形成介质氧化层(250)，刻蚀并保留位于漏区侧墙上的介质氧化层(250)；去除源区侧墙中的第二介质层(240)并保留第一介质层(230)。

Description

半导体器件及其制备方法 技术领域
本发明涉及半导体技术领域，特别是涉及半导体器件及其制备方法。
背景技术
在半导体技术中，即使元件尺寸持续减少，仍希望晶体管的性能可更为增进，也希望能制造出结合低、中、高电压应用范围的集成电路半导体装置。但是受限于在线工艺能力控制的问题，金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor，MOS)中多晶硅层的间距被限制在一定的尺寸上没有办法缩小。
发明内容
根据本申请的各种实施例提供一种半导体器件及其制备方法。
一种半导体器件的制备方法，包括：
在半导体衬底内形成阱区以及在所述阱区内形成沟道区，并在所述阱区上形成栅氧化层和多晶硅层；
刻蚀部分所述栅氧化层和多晶硅层并露出用于形成源区的第一开口和用于形成漏区的第二开口；
在所述多晶硅层上、第一开口内、第二开口内依次形成第一介质层和第二介质层，并在所述第一开口的侧壁形成源区侧墙，在所述第二开口的侧壁形成漏区侧墙；
在所述多晶硅层上形成介质氧化层，刻蚀并保留位于所述漏区侧墙上的所述介质氧化层；
去除所述源区侧墙中的第二介质层并保留所述第一介质层。
此外，还提供一种半导体器件，包括：
半导体衬底，所述半导体内设有阱区以及位于所述阱区内的沟道区；
位于所述半导体衬底上的栅氧化层和多晶硅层，以及设置在所述栅氧化层和多晶硅层上的用于形成源区的第一开口和用于形成漏区的第二开口；
位于所述第一开口侧壁的源区侧墙和位于所述第二开口侧壁的漏区侧墙，其中，所述源区侧墙为所述第一介质层，所述漏区侧墙包括依次层叠的第一介质层、第二介质层；以及
位于所述漏区侧墙上的介质氧化层。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一副或多副附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为一个实施例中半导体器件制备方法的流程图；
图2A-2J为根据一实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所 使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1为一个实施例中半导体器件的制备方法的流程图，半导体器件的制备方法，包括如下步骤：
步骤S110：在半导体衬底内形成阱区以及在所述阱区内形成沟道区，并在所述阱区上形成栅氧化层和多晶硅层。
如图2A所示，提供半导体衬底200，半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在本实施例中，半导体衬底200的构成材料选用P型半导体衬底200。
在一个实施例中，氧化半导体衬底200，形成缓冲层(氧化硅层，图未示)，在缓冲层上淀积氮化硅层，通过光刻定义出阱区201，并通过反应离子刻蚀氧化硅层，通过离子注入的方式在半导体衬底200中先注入磷P+，后注砷As+形成N型阱区201。在其他实施例中，其半导体衬底的导电类型，与位于半导体衬底200中阱区201的导电类型可以根据实际需求来设定，并不限于此。
在一个实施例中，还在阱区201内通过离子注入或其他方式形成沟道区202。
在一个实施例中，在半导体衬底200上用热氧化或者化学氧化工艺形成栅氧化层210。
具体地，所述栅氧化层210包括在竖直方向对应源区的第一栅氧化层211区域和在竖直方向对应漏区的第二栅氧化层213区域；其中，第一栅氧化层211区域的厚度小于所述第二栅氧化层213区域的厚度。
进一步地，第一栅氧化层211区域的厚度为15nm，第二栅氧化层213区域的厚度为44nm，由于第二栅氧化层213的厚度高于第一栅氧化层211的厚度，可以提高漏区的电压。通过在不同的区域形成不同厚度的栅氧化层210， 可以形成高压金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor，MOS)器件。
如图2B所示，半导体器件的制备方法还包括在栅氧化层210上形成多晶硅层220的步骤，其中，形成多晶硅层220的方法可以采用化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积等离子体增强化学气相沉积。
具体地，多晶硅层220的厚度为180～220nm，在本实施例中，多晶硅层220的厚度为2 00nm。
步骤S120：刻蚀部分所述栅氧化层和多晶硅层并露出用于形成源区的第一开口和用于形成漏区的第二开口。
如图2C所示，同时刻蚀部分栅氧化层210和多晶硅层220，刻蚀形成第一开口221和第二开口223。其中，第一开口221的底面为部分沟道区202的顶面，第一开口221可以定义后续形成源区侧墙以及源区的位置，第二开口223与第一开口221隔离设置，且第二开口223的底面为阱区201的顶面，第二开口223可以定义后续形成漏区侧墙以及漏区的位置。
形成第一开口221和第二开口223的工艺步骤包括：在多晶硅层220上形成具有第一开口221和第二开口223图案的掩膜层，可以采用常规的光刻、刻蚀工艺形成掩膜层，掩膜层可以为单层结构或多层结构，具有单层结构的掩膜层为图案化的光刻胶层，具有多层结构的掩膜层可以包括自下而上层叠的图案化的先进图案化层、抗反射涂层和光刻胶层；以掩膜层为掩膜，同时蚀刻栅氧化层210和多晶硅层220，在栅氧化层210和多晶硅层220形成第一开口221和第二开口223，蚀刻可以是常规的各向异性的干法蚀刻；去除掩膜层，可以采用常规的灰化工艺去除掩膜层；实施湿法清洗，以去除蚀刻所产生的副产物和杂质。
在一个实施例中，其阱区201内的沟道区202也可以在形成第一开口221后，从第一开口221通过离子注入的方式形成。
步骤S130：在所述多晶硅层上、第一开口内、第二开口内形成第一介质层，在第一介质层上形成第二介质层，并在所述第一开口的侧壁形成源区侧 墙，在所述第二开口的侧壁形成漏区侧墙。
如图2D所示，在一个实施例中，在多晶硅层220(图未标)、第一开口221、第二开口223形成第一介质层230，其中，第一介质层230形成于第一开口221的侧壁、底面，第一介质层230形成于第二开口223的侧壁、底面，但未填满第一开口221和第二开口223。
如图2E所示，进一步地，在第一介质层230(图未标)的基础上，形成第二介质层240。其中，第二介质层240的厚度大于第一介质层230的厚度。形成第一介质层230和第二介质层240的方法可以采用化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积等离子体增强化学气相沉积。
在一个实施例中，所述第一介质层230为氧化层，所述氧化层的厚度范围为8～12纳米。所述第二介质层240为氮化硅层；所述氮化硅层的厚度范围为80～120纳米。
如图2F所示，在一个实施例中，通过光刻、刻蚀等工艺刻蚀氮化硅层和氧化层，形成源区侧墙241和漏区侧墙243，除源区侧墙241和漏区侧墙243外的氮化硅层和氧化层全部刻蚀去除露出多晶硅层220。相应的，第一开口221内的中间部分的氮化硅层和氧化层也被刻蚀至沟道区202，并露出部分沟道区202。第二开口223内的一部分的氮化硅层和氧化层刻蚀至阱区201，并露出阱区201。蚀刻可以是各向异性的干法蚀刻或/和湿法刻蚀。
步骤S140：在所述多晶硅层上形成介质氧化层，刻蚀并保留位于所述漏区侧墙上的所述介质氧化层。
如图2G所示，在多晶硅层220上通过淀积形成介质氧化层250，其中，介质氧化层250还形成于源区侧墙241的侧壁、第一开口221的底部(沟道区202)；介质氧化层250还形成于漏区侧墙243的侧壁、第二开口223的底部(阱区201)。
如图2H所示，并在刻蚀介质氧化层250时，利用介质氧化层250的光刻版光刻并刻蚀出阻挡层保护漏区侧墙243不被刻掉。也即，漏区侧墙243 上的介质氧化层250并未被刻蚀，漏区侧墙243包括氮化硅和介质氧化层双层结构，漏区侧墙243可以降低漏端的电场强度，有利于器件的击穿特性。其中，介质氧化层250可以为二氧化硅层。
步骤S150：去除所述源区侧墙中的第二介质层并保留所述第一介质层。
如图2I所示，在介质氧化层250刻蚀之后，利用湿法漂洗，将源区(带有沟道区202一端)侧墙241的第二介质层240(氮化硅层)漂掉，使得源区侧墙241中的介质层只有第一介质层230(氧化层)一层介质。也即，在不改变漏区结构的前提下，实现了源区侧墙241的横向厚度(也可以称之为第一介质层230的厚度)相对于漏区侧墙243的横向厚度的减小，缩短了源区所对应的多晶硅层220的间距，即可减小整个半导体器件的尺寸，降低了半导体器件的导通电阻。
传统技术中，如果要缩小多晶硅层的间距，就要减小侧墙的宽度。而在一般的工艺流程下，源区侧墙和漏区侧墙是同时形成的，如果减小源区或漏区侧墙的宽度，则漏区的电场强度会随着漏区侧墙的减小而增强，进而影响到半导体器件在截止态下漏电增强。而通过上述半导体器件的制备方法，减少了源端侧墙的横向厚度，缩短了源区所对应的多晶硅层220的间距，即可减小整个半导体器件的尺寸，降低了半导体器件的导通电阻。同时利用现有的光刻层次的光刻版形成阻挡层，保留了漏区侧墙243中双层介质层，降低了工艺成本，同时又能够保证漏区电场不发生变化，不会影响半导体器件的原有特性。
在一个实施例中，步骤S140在所述多晶硅层220上形成介质氧化层250前，半导体器件的制备方法还包括在所述阱区201内形成所述源区203和漏区204的步骤。
如图2G所示，在一个实施例中，半导体器件的制造方法还包括通过磷离子或砷离子注入工艺在半导体衬底中形成源区203和漏区204。由于半导体衬底中的源区203、沟道区202均在步骤S150之前形成，因此不会影响源区的杂质分布。
在一个实施例中，在步骤S150，去除所述源区侧墙中的第二介质层并保留所述第一介质层的步骤后，还包括在所述多晶硅层上形成层间介质层；以及在所述层间介质层中形成接触孔的步骤。
如图2J所示，在一个实施例中，半导体器件的制造方法还包括在半导体衬底上形成第一层间介质层260和第二层间介质层270。作为示例，第一层间介质层260和第二层间介质层270的材料具有低介电常数的材料，所述具有低介电常数的材料包括但不限于k值为2.5-2.9的硅酸盐化合物(Hydrogen Silsesquioxane，简称为HSQ)、k值为2.2的甲基硅酸盐化合物(Methyl Silsesquioxane，简称MSQ)、以及化学气相沉积方法形成的多孔性二氧化硅等等。第一层间介质层260和第二层间介质层270的形成方法可以采用化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积等。如图2J所示，在一个实施例中，半导体器件的制造方法还包括通过光刻、刻蚀工艺形成贯穿第一层间介质层260和第二层间介质层270的接触孔261。作为示例，在第二层间介质层270上形成具有接触孔261图案的掩膜层，以该掩膜层为掩膜，蚀刻第一层间介质层260和第二层间介质层270，在第一层间介质层260和第二层间介质层270中形成露出源区203和漏区204的接触孔261，去除该掩膜层后，在所述通孔中填充金属层，以形成金属连接线。
传统的漏区侧墙中包括第一介质层和第二介质层(氮化硅层)，在形成接触孔的过程中腐蚀到漏区侧墙的氮化硅时，其氮化硅层被腐蚀的速率较低，可能会造成接触孔不能刻蚀贯穿至源区，为了防止接触孔刻蚀出现异常，需要限定接触孔与氮化硅层之间的安全距离。也即，在形成接触孔261时，应确保其接触孔261不会与源区侧墙241中的第二介质层240(氮化硅层)、漏区侧墙243中的第二介质层240(氮化硅层)接触，需要保证接触孔261到多晶硅层220的距离大于源区侧墙241或漏区侧墙243的宽度。由于源区侧墙241中的第二介质层240(氮化硅层)被漂掉，其源区侧墙241的宽度越小，接触孔261到多晶硅层220的距离也就越小，多晶硅层220的间距也就 越小。
通过上述方法制备的半导体器件可以为N型MOS管、P型MOS管、高压MOS管等。通过上述半导体器件的制备方法，可以减少了源端侧墙的横向厚度，缩短了源区所对应的多晶硅层220的间距，即可减小整个半导体器件的尺寸，降低了半导体器件的导通电阻。同时利用现有的阻挡层保留了漏区侧墙243中双层介质层，降低了工艺成本，同时又能够保证漏区电场不发生变化，不会影响半导体器件的原有特性。
此外，还提供一种半导体器件，如图2J所示，半导体器件包括：半导体衬底(图未示)，所述半导体内设有阱区201以及位于所述阱区201内的沟道区202；位于所述半导体衬底上的栅氧化层210和多晶硅层220，以及设置在所述栅氧化层210和多晶硅层220上的用于形成源区203的第一开口(图未标)和用于形成漏区204的第二开口(图未标)；位于所述第一开口侧壁的源区侧墙241和位于所述第二开口侧壁的漏区侧墙243，其中，所述源区侧墙241包括所述第一介质层230，所述漏区侧墙243包括依次层叠的第一介质层230、第二介质层240；以及位于所述漏区侧墙243上的介质氧化层250。
在一个实施例中，所述第一介质层230为氧化层，所述第二介质层240为氮化硅层。
具体地，所述氧化层的厚度范围为8～12纳米；所述氮化硅层的厚度范围为80～120纳米。
在一个实施例中，半导体器件还包括位于阱区201内的源区203和漏区204，源区203和漏区204的形成是通过磷离子或砷离子注入工艺而形成的。其中，源区与第一开口对应设置，漏区与第二开口对应设置。
在一个实施例中，半导体器件还包括位于所述多晶硅层220上的层间介质层260，以及位于所述层间介质层260中的接触孔261。
层间介质层260的材料可以是具有低介电常数的材料，所述具有低介电常数的材料包括但不限于k值为2.5-2.9的硅酸盐化合物(Hydrogen Silsesquioxane，简称为HSQ)、k值为2.2的甲基硅酸盐化合物(Methyl  Silsesquioxane，简称MSQ)、以及化学气相沉积方法形成的多孔性二氧化硅等等。层间介质层260的形成方法可以采用化学气相沉积法，如低温化学气相沉积、低压化学气相沉积、快热化学气相沉积、等离子体增强化学气相沉积等。通过光刻、刻蚀工艺形成贯穿层间介质层260的接触孔261。作为示例，在层间介质层260上形成具有接触孔261图案的掩膜层，以该掩膜层为掩膜，蚀刻层间介质层260，在层间介质层260中形成露出阱区201的通孔，去除该掩膜层后，在所述通孔中填充金属层，以形成金属连接线。在形成接触孔261时，应确保其接触孔261不会与源区侧墙241、漏区侧墙243接触，需要保证接触孔261到多晶硅层220的距离大于源区侧墙241或漏区侧墙243的宽度。其源区侧墙241或漏区侧墙243的宽度越小，接触孔261到多晶硅层220的距离也就越小，多晶硅层220的间距也就越小。
半导体器件可以为N型MOS管、P型MOS管、高压MOS管等。上述半导体器件，减少了源端侧墙的横向厚度，缩短了源区所对应的多晶硅层220的间距，即可减小整个半导体器件的尺寸，降低了半导体器件的导通电阻。同时利用现有的阻挡层保留了漏区侧墙中双层介质层，降低了工艺成本，同时又能够保证漏区电场不发生变化，不会影响半导体器件的原有特性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件的制备方法，包括：
    在半导体衬底内形成阱区以及在所述阱区内形成沟道区，并在所述阱区上形成栅氧化层和多晶硅层；
    刻蚀部分所述栅氧化层和多晶硅层并露出用于形成源区的第一开口和用于形成漏区的第二开口；
    在所述多晶硅层上、第一开口内、第二开口内形成第一介质层，在所述第一介质层上形成第二介质层，并在所述第一开口的侧壁形成源区侧墙，在所述第二开口的侧壁形成漏区侧墙；
    在所述多晶硅层上形成介质氧化层，刻蚀并保留位于所述漏区侧墙上的所述介质氧化层；
    去除所述源区侧墙中的第二介质层并保留所述第一介质层。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，所述第一介质层为氧化层，所述第二介质层为氮化硅层。
  3. 根据权利要求2所述的半导体器件的制备方法，其中，所述氧化层的厚度范围为8～12纳米；所述氮化硅层的厚度范围为80～120纳米。
  4. 根据权利要求1所述的半导体器件的制备方法，其中，所述栅氧化层包括在竖直方向对应所述源区的第一栅氧化层区域和在竖直方向对应所述漏区的第二栅氧化层区域；其中，
    第一栅氧化层区域的厚度小于所述第二栅氧化层区域的厚度。
  5. 根据权利要求4所述的半导体器件的制备方法，其中，所述第一栅氧化层区域的厚度为15nm，所述第二栅氧化层区域的厚度为44nm。
  6. 根据权利要求1所述的半导体器件的制备方法，其中，所述多晶硅层的厚度为180～220nm。
  7. 根据权利要求1所述的半导体器件的制备方法，其中，所述方法还包括：
    在所述阱区内形成所述源区和漏区。
  8. 根据权利要求5所述的半导体器件的制备方法，其中，所述在所述阱区内形成所述源区和漏区具体是在多晶硅层上形成介质氧化层前通过离子注入工艺在所述半导体衬底中形成源区和漏区。
  9. 根据权利要求1所述的半导体器件的制备方法，其中，所述方法还包括：
    在所述多晶硅层上形成层间介质层；
    在所述层间介质层中形成接触孔。
  10. 根据权利要求9所述的半导体器件的制备方法，其中，所述层间介质层的材料为具有低介电常数的材料。
  11. 根据权利要求9所述的半导体器件的制备方法，其中，位于所述源区内的接触孔到所述多晶硅层的距离大于所述源区侧墙的宽度，位于所述漏区内的接触孔到所述多晶硅层的距离大于所述漏区侧墙的宽度。
  12. 根据权利要求1所述的半导体器件的制备方法，其中，所述在所述第一开口的侧壁形成源区侧墙，在所述第二开口的侧壁形成漏区侧墙的步骤，是刻蚀所述第一介质层和第二介质层，在所述第一开口的侧壁残留的第一介质层和第二介质层形成源区侧墙，在所述第二开口的侧壁残留的第一介质层和第二介质层形成源区侧墙。
  13. 根据权利要求1所述的半导体器件的制备方法，其中，所述介质氧化层为二氧化硅层。
  14. 一种半导体器件，包括：
    半导体衬底，所述半导体内设有阱区以及位于所述阱区内的沟道区；
    叠设于所述半导体衬底上的栅氧化层和多晶硅层，以及设置在所述栅氧化层和多晶硅层上的用于形成源区的第一开口和用于形成漏区的第二开口；
    位于所述第一开口侧壁的源区侧墙和位于所述第二开口侧壁的漏区侧墙，其中，所述源区侧墙包括第一介质层，所述漏区侧墙包括依次层叠的第一介质层、第二介质层；以及
    位于所述漏区侧墙上的介质氧化层。
  15. 根据权利要求14所述的半导体器件，其中，所述第一介质层为氧化层，所述第二介质层为氮化硅层。
  16. 根据权利要求15所述的半导体器件，其中，所述氧化层的厚度范围为8～12纳米；所述氮化硅层的厚度范围为80～120纳米。
  17. 根据权利要求14所述的半导体器件，其中，所述多晶硅层的厚度为180～220nm。
  18. 根据权利要求14所述的半导体器件，其中，还包括位于所述多晶硅层上的第一层间介质层和第二层间介质层，以及贯穿所述第一层间介质层和第二层间介质层的接触孔。
  19. 根据权利要求18所述的半导体器件，其中，所述层间介质层的材料为具有低介电常数的材料。
  20. 根据权利要求18所述的半导体器件，其中，位于所述源区内的接触孔到所述多晶硅层的距离大于所述源区侧墙的宽度，位于所述漏区内的接触孔到所述多晶硅层的距离大于所述漏区侧墙的宽度。
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