CN110176453B - 中段制程结构 - Google Patents

中段制程结构 Download PDF

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CN110176453B
CN110176453B CN201910047004.8A CN201910047004A CN110176453B CN 110176453 B CN110176453 B CN 110176453B CN 201910047004 A CN201910047004 A CN 201910047004A CN 110176453 B CN110176453 B CN 110176453B
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gate
contact
drain regions
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CN110176453A (zh
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臧辉
谢瑞龙
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Lattice Core Usa Inc
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Abstract

本发明涉及中段制程结构。本公开一般涉及半导体结构，更特别地，涉及中段制程结构和制造方法。该结构包括：多个栅极结构，其包括源极和漏极区；连接到源极和漏极区的接触；连接到栅极结构的接触，该接触偏离连接到源极和漏极区的接触；以及互连结构，其与栅极结构的接触和源极和漏极区的接触电接触。

Description

中段制程结构
技术领域
本公开通常涉及半导体结构，更特别地，涉及中段制程结构和制造方法。
背景技术
随着半导体工艺继续向下缩放(例如，缩小)特征之间的期望间隔(即，栅距(pitch))也变小。为此，在较小的技术节点中，由于关键尺寸(CD)缩放和处理能力以及用于制造这种结构的材料，制造例如互连的后段制程(BEOL)和中段制程(MOL)金属化特征甚至变得更加困难。
例如，为了制造用于源极和漏极接触的互连结构，有必要去除邻近栅极结构的电介质材料。该电介质材料的去除通过蚀刻工艺来提供，该蚀刻工艺也倾向于侵蚀栅极结构中的隔离物材料。也就是，在用于形成源极和漏极接触的开口的下游蚀刻工艺中，用于栅极结构的隔离物或侧壁的低k电介质材料可被侵蚀掉。这种材料的损失将暴露栅极结构中的金属材料，导致栅极结构中的金属材料与用于形成接触的金属材料本身之间的短路。
在当前结构中，栅极结构之间必须存在最小间隔，以避免栅极接触与源极和漏极接触之间的短路。然而，随着器件继续向下缩放，在这些传统结构中，最小间距和其他设计规则变得更难以实现。
发明内容
在本公开的方面，一种结构，包括：多个栅极结构，其包括源极和漏极区；连接到所述源极和漏极区的接触；连接到所述栅极结构的接触，所述接触偏离连接到所述源极和漏极区的所述接触；以及互连结构，其与所述栅极结构的所述接触以及所述源极和漏极区的所述接触电接触。
在本公开的方面，一种结构，包括：多个栅极结构，其包括源极和漏极区、栅极接触和从所述栅极接触延伸的互连结构；至少一个源极和漏极接触，其位于相对于所述栅极接触的不同高度处；以及位于所述源极和漏极区、所述栅极接触和所述至少一个源极和漏极接触之上的衬里。
在本公开的方面，一种方法，包括：形成多个栅极结构，所述多个栅极结构包括源极和漏极区以及栅极材料；形成层间电介质层，所述层间电介质层包括位于栅极结构的源极和漏极区之上的牺牲层和电介质帽；打开所述电介质帽的一部分以暴露所述牺牲层；去除所述牺牲层以暴露所述源极和漏极区；暴露所述栅极材料；在所述暴露的栅极材料和所述暴露的源极和漏极区上同时形成偏移金属化特征；以及形成从所述金属化特征延伸的偏移接触。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1A-1C示出了根据本公开的方面的除了其他特征之外的栅极结构以及相应的制造方法。
图2A和2B示出了根据本公开的方面的除了其他特征之外的浅沟槽隔离区以及相应的制造方法。
图3A-3D示出了根据本公开的方面的除了其他特征之外的浅沟槽隔离区以及相应的制造方法。
图4A-4C示出了根据本公开的方面的除了其他特征之外的具有暴露的非晶硅的结构以及相应的制造方法。
图5A-5C示出了根据本公开的方面的除了其他特征之外的具有暴露的源极和漏极区的结构以及相应的制造方法。
图6A-6C示出了根据本公开的方面的除了其他特征之外的虚设(dummy)填充材料以及相应的制造方法。
图7A-7D示出了根据本公开的方面的除了其他特征之外的栅极接触以及源极和漏极接触以及相应的制造方法。
图8A-8D示出了根据本公开的方面的除了其他特征之外的互连结构以及相应的制造方法。
具体实施方式
本公开一般涉及半导体结构，更特别地，涉及中段制程结构和制造方法。在实施例中，本文提供的方法和结构允许栅极接触以及源极和漏极接触相对于彼此偏移。另外，本文提供的方法和结构允许栅极接触以及源极和漏极接触相对于彼此处于不同的高度。有利地，通过具有位于不同高度处的偏移接触，在栅极结构的金属化特征与源极和漏极区的金属化特征之间的制造方法期间，即，在形成用于栅极接触以及源极和漏极接触的互连结构期间，防止短路。以这种方式，本文描述的结构和方法为栅极接触以及源极和漏极接触提供互连结构，而没有任何短路问题。
本公开的结构可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的结构的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，结构的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1A-1C示出了根据本公开的方面的输入结构以及相应的制造方法。更具体地，图1A示出了结构100的顶视图，而图1B示出了在X轴方向上的横截面图，以及图1C示出了在Y轴方向上的横截面图。结构100包括有源区110，该有源区110可以形成器件，例如晶体管。结构100还包括由合适的半导体材料构成的衬底105。例如，衬底105可以由包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP等的任何合适的材料构成。在实施例中，衬底105可以为鳍结构或平面特征的代表。
在实施例中，可以使用侧壁图像转移(SIT)技术来制造鳍结构。在SIT技术的示例中，使用常规的CVD工艺将例如SiO2的芯轴(mandrel)材料沉积在衬底105上。在芯轴材料上形成抗蚀剂，该抗蚀剂被曝光以形成图案(开口)。通过开口执行反应离子蚀刻以形成芯轴。在实施例中，依赖于鳍结构的期望尺寸，芯轴可具有不同的宽度和/或间隔。在芯轴的侧壁上形成隔离物，该隔离物优选为不同于芯轴的材料，并且为使用本领域技术人员已知的常规沉积工艺形成。例如，隔离物的宽度可以与窄鳍结构的尺寸相匹配。使用对芯轴材料有选择性的常规蚀刻工艺去除或剥离芯轴。然后在隔离物的间隔内执行蚀刻以形成亚光刻特征。然后可以剥离侧壁隔离物。
在衬底105上形成栅极结构150。应该理解，栅极结构150可以是平面栅极结构或finFET栅极结构。在任一种情况下，栅极结构150可以使用任何已知的栅极形成工艺来制造，例如，本领域已知的替代栅极制造工艺。以此方式，栅极结构150可以是替代栅极结构。在实施例中，栅极制造工艺以例如多晶硅(poly-Si)的虚设栅极材料开始，以形成虚设栅极结构。使用例如任何常规工艺在衬底105中在虚设栅极结构的侧面上形成源极和漏极(S/D)区115。例如，S/D区115可以通过离子注入工艺、掺杂工艺或通过扩散工艺形成，如本领域技术人员所熟知的，使得不需要进一步解释来理解本公开。在另外的实施例中，S/D区115可以是升高的S/D区，其在虚设栅极结构之间在衬底105的表面上由外延生长形成。以这种方式，多个栅极结构150包括S/D区115。
例如低k电介质的侧壁隔离物140可以沉积在虚设栅极材料的侧壁上。可以通过常规CVD工艺沉积侧壁隔离物140，然后进行图案化工艺，例如各向异性蚀刻工艺，以从结构的水平表面去除任何材料。衬里120沉积在虚设栅极结构的侧壁隔离物140的侧壁上和S/D区115之上。在实施例中，衬里120可以通过化学气相沉积(CVD)工艺沉积。衬里120可由任何合适的材料构成，例如，SiN。
图1B和1C示出了沉积在衬里120上的非晶硅(α-Si)材料125。以此方式，α-Si材料125位于S/D区115之上。α-Si材料125可以通过例如CVD工艺的常规沉积工艺，然后进行蚀刻。使用对α-Si材料125具有选择性的化学(chemistry)的反应离子蚀刻(RIE)蚀刻α-Si材料125。在实施例中，例如，α-Si材料125凹陷到约10nm-50nm范围的高度。层间电介质(ILD)层130沉积在α-Si材料125之上的凹部中。ILD层130可以由通过CVD工艺沉积的例如氧化物的任何合适的电介质材料构成。在沉积ILD层130之后进行化学机械抛光(CMP)工艺。以这种方式，利用以下双层材料创建ILD层：底部牺牲层，即，α-Si材料125，以及顶部电介质帽，即，ILD层130。具体地，ILD层包括位于栅极结构150的源极和漏极区115之上的牺牲层和电介质帽。
将例如多晶硅的虚设栅极材料剥离，形成沟槽并暴露衬底105。使用对虚设栅极材料具有选择性的常规蚀刻工艺去除或剥离虚设栅极材料芯轴。栅极结构150在衬底105上在沟槽内形成。在实施例中，栅极结构150包括栅极电介质材料和金属化特征。栅极电介质材料可以是例如高k栅极电介质材料，例如，基于铪的电介质。在另外的实施例中，高k电介质材料可以包括但不限于：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其多层的组合。依赖于特定的应用和设计参数，金属化特征，即，栅极材料135可以包括任何功函数金属或任何金属的组合。例如，在实施例中，除了其他示例之外，栅极材料135可以是钨(W)材料。
在实施例中，蚀刻栅极材料135以在栅极结构150中形成凹部。以此方式，栅极结构150是凹陷的栅极结构。可以使用例如湿法蚀刻工艺的对栅极材料135的选择性蚀刻工艺来蚀刻栅极材料135。例如使用CVD工艺在栅极材料135之上的凹槽内沉积帽盖材料145，然后进行CMP工艺。除了其他示例之外，帽盖材料145可以是任何合适的帽盖材料，例如，SiN。
图2A和2B示出了在ILD层130中形成浅沟槽隔离(STI)区。在实施例中，使用例如RIE工艺的常规光刻和蚀刻技术在ILD层130中形成沟槽155。例如，在ILD层130上形成的抗蚀剂暴露于能量(光)以形成图案(开口)。例如RIE的具有选择性化学的蚀刻工艺将用于通过抗蚀剂的开口在ILD层130中形成一个或多个沟槽155。然后可以通过常规的氧灰化工艺或其他已知的剥离剂(stripant)去除抗蚀剂。
图3A-3D示出了具有附加横截面图的结构100。具体地，图3A示出了结构100的顶视图，以及图3B和3C示出了在X轴方向上的横截面图，图3D示出了在Y轴方向上的横截面图。图3D示出了填充有电介质材料160的沟槽155以形成STI结构165。在实施例中，除了其他示例之外，电介质材料160可以由例如SiOC的低k电介质材料构成。电介质材料160的沉积是通过CVD工艺，然后进行CMP工艺。
图4A-4C示出了在STI结构165和ILD层130之上形成的光致抗蚀剂170。在实施例中，光致抗蚀剂170暴露于能量(光)以形成图案(开口)。例如RIE工艺的具有选择性化学的蚀刻工艺将用于通过光致抗蚀剂170的开口在ILD层130中形成一个或多个沟槽175，从而暴露α-Si材料125。图4C示出了打开电介质帽(即，ILD层130)的一部分，以暴露牺牲层，即，α-Si材料125。如图4A和4C所示，ILD层130的部分保留邻近电介质材料160。
图5A-5C示出了去除α-Si材料125，形成沟槽175’以暴露源极和漏极(S/D)区115。α-Si材料125可以通过例如湿法蚀刻工艺的常规蚀刻工艺去除。在实施例中，α-Si材料125的蚀刻可以具有或不具有光致抗蚀剂170。在实施例中，α-Si材料125的蚀刻不是方向性的，使得在X轴方向和Y轴方向上留下ILD层130的部分，如图5A和5C所示。可以通过常规的氧灰化工艺或其他已知的剥离剂去除光致抗蚀剂170。
图6A-6C示出了用牺牲材料180填充沟槽175’。在实施例中，除了其他示例之外，牺牲材料180可以是SOH、非晶碳(α-C)或有机平坦化层(OPL)等。使用牺牲材料180以创建用于沉积光致抗蚀剂170’的平坦表面，这将用于蚀刻栅极结构150的帽盖材料145(在后续工艺中沿X轴方向)。在实施例中，在STI结构165、ILD层130和牺牲材料180之上形成光致抗蚀剂170’。光致抗蚀剂170’暴露于能量(光)以形成图案(开口)。将使用例如RIE的具有选择性化学的蚀刻工艺来通过抗蚀剂的开口去除帽盖材料145，从而在X轴方向上形成栅极结构150的栅极材料135中的一个或多个沟槽185。具体地，图6A示出了暴露栅极结构150的栅极材料135。可以通过常规的氧灰化工艺或其他已知的剥离剂去除光致抗蚀剂170’，同时可以通过选择性蚀刻去除牺牲材料180。去除帽盖材料145，即，栅极帽，是用于随后形成到栅极结构150的栅极接触。
图7A-7D示出了根据本公开的方面的除了其他特征之外的源极和漏极和栅极金属化特征以及相应的制造方法。具体地，硅化物衬里190沉积在沟槽185中(在栅极结构150之上，特别是栅极材料135之上)和S/D区115之上。具体地，图7B示出在形成金属化特征之前在暴露的栅极材料135和暴露的源极和漏极区115上沉积衬里190。衬里190经受硅化物工艺。可以使用物理气相沉积(PVD)或CVD工艺来沉积衬里190。除了其他示例之外，衬里90可以是Ti、TiN、TaN、Ru和Co。在硅化物工艺之后，在衬里190上沉积金属材料195，以形成源极和漏极接触200以及栅极接触205。以此方式，源极和漏极接触200以及栅极接触205由相同的金属材料195同时形成。
金属材料195可以通过CVD工艺沉积，并且可以是任何合适的导电材料。例如，金属材料195可以是例如钨(W)、钴(Co)或铜(Cu)。金属材料195的沉积之后是CMP工艺。源极和漏极接触200连接到S/D区115，而栅极接触205连接到栅极结构150。以此方式，栅极结构150的栅极接触205包括衬里190和填充材料(即，金属材料195)。此外，衬里190位于S/D区115、栅极材料135、栅极接触205和至少一个源极和漏极接触之上。
如图7A所示，源极和漏极接触200在X轴方向和Y轴方向上都偏离栅极接触205。以这种方式，连接到栅极结构150的栅极接触205偏离连接到S/D区115的源极和漏极接触200。特别地，栅极结构150的栅极接触205在X轴方向和Y轴方向上偏离S/D区115的源极和漏极接触200。具体地，图7B示出了在暴露的栅极材料135和暴露的S/D区115上同时形成偏移金属化特征，即，接触200、205。此外，如图7B所示，源极和漏极接触200的高度与栅极接触205的高度不同。具体地，源极和漏极接触200的高度低于栅极接触205的高度，使得至少一个源极和漏极接触200位于相对于栅极接触205的不同的高度。以这种方式，栅极结构150的栅极接触205处于与S/D区115的源极和漏极接触200的不同的高度处。
在实施例中，源极和漏极接触200是阶梯形的，在其上具有电介质帽，即，ILD层130。具体地，至少一个源极和漏极接触200是阶梯形的。以这种方式，衬里190将直接接触S/D区115(例如，S/D区115的硅化物)、栅极结构150的侧壁隔离物140，并且在源极和漏极接触200之上的电介质帽下方。具体地，如图8B所示，ILD层130在源极和漏极接触200上形成电介质帽。具体地，电介质帽包括氧化物材料(即，ILD层130的氧化物)和衬里120。
本文描述的结构和方法提供了防止较小技术节点中的短路的益处。具体地，通过使金属材料195同时形成处于不同的高度处并且彼此偏离的源极和漏极接触200以及栅极接触205来防止短路。
图8A-8D示出了形成从源极和漏极接触200以及栅极接触205延伸的金属化特征(例如，互连接触结构)。具体地，蚀刻停止层210沉积在ILD层130和栅极接触205之上。在实施例中，蚀刻停止层210通过CVD工艺沉积，并且可以由例如SiN的氮化物材料构成。ILD层215通过例如CVD工艺沉积在蚀刻停止层210之上。在实施例中，ILD层215可以由例如氧化物材料构成。在沉积ILD层215之后，执行CMP工艺。
可以使用例如RIE工艺的常规光刻和蚀刻工艺形成从接触200、205延伸的互连结构220、225。例如，在ILD层215之上形成的抗蚀剂暴露于能量(光)以形成图案(开口)。例如反应离子蚀刻(RIE)的具有选择性化学的蚀刻工艺将用于通过抗蚀剂的开口在ILD层215中形成一个或多个沟槽。然后可以通过常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂。
在去除抗蚀剂之后，通过例如CVD工艺的常规沉积工艺沉积导电材料，以形成互连结构220、225。在ILD层215的表面上的任何残留导电材料可以通过常规CMP工艺去除。用于形成互连结构220、225的导电材料可以是任何合适的导电材料，例如，钨(W)。在实施例中，互连结构220与源极和漏极接触200直接电接触，而互连结构225与栅极接触205直接电接触。以此方式，互连结构220、225与栅极结构150的接触以及源极和漏极区(S/D)115的接触电接触。图8B示出了形成从金属化特征(即，接触200、205)延伸的偏移接触，即，互连结构220、225。另外，图8B示出了包括源极和漏极区115、栅极材料135、栅极接触205和从栅极接触205延伸的互连结构225的多个栅极结构150。
现在应该理解，本文描述的方法和所得到的结构将用于在MOL工艺期间进一步保护栅极结构的栅极金属。所得到的结构，例如，侧壁结构，将因此防止与源极/漏极区的互连或其他布线结构发生短路。因此，本文描述的方法和结构将增加产量。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种半导体结构，包括：
多个栅极结构，其包括源极和漏极区；
连接到所述源极和漏极区的接触；
硅化物衬里，其覆盖所述源极和漏极区，并且位于所述连接到所述源极和漏极区的接触的侧壁与所述栅极结构的侧壁之间；
连接到所述栅极结构的接触，其偏离所述连接到所述源极和漏极区的接触；以及
互连结构，其与所述栅极结构的所述接触以及所述源极和漏极区的所述接触电接触。
2.根据权利要求1所述的结构，其中所述栅极结构的所述接触包括衬里和填充材料。
3.根据权利要求2所述的结构，其中所述衬里是TiN衬里。
4.根据权利要求3所述的结构，其中所述TiN衬里位于所述源极和漏极区之上。
5.根据权利要求4所述的结构，其中所述填充材料是钴或钨。
6.根据权利要求1所述的结构，其中所述栅极结构的所述接触处于与与所述源极和漏极区的所述接触不同的高度处。
7.根据权利要求1所述的结构，其中所述栅极结构的所述接触在X轴方向上偏离所述源极和漏极区的所述接触。
8.根据权利要求1所述的结构，其中所述栅极结构的所述接触在Y轴方向上偏离所述源极和漏极区的所述接触。
9.根据权利要求1所述的结构，还包括位于所述源极和漏极区的所述接触之上的电介质帽。
10.根据权利要求9所述的结构，其中所述电介质帽包括氧化物材料和衬里。
11.根据权利要求10所述的结构，其中所述衬里由氮化物材料构成。
12.根据权利要求1所述的结构，其中所述栅极结构是替代栅极结构。
13.根据权利要求1所述的结构，其中所述栅极结构是凹陷的栅极结构。
14.一种半导体结构，包括：
多个栅极结构，其包括隔离物、源极和漏极区、栅极接触和从所述栅极接触延伸的互连结构；
至少一个源极和漏极接触，其位于相对于所述栅极接触的不同高度处；以及
硅化物衬里，其覆盖所述源极和漏极区以及所述至少一个源极和漏极接触，所述硅化物衬里位于所述至少一个源极和漏极接触的侧壁与所述隔离物的侧壁之间。
15.根据权利要求14所述的结构，其中所述至少一个源极和漏极接触在X轴或Y轴方向上偏移所述栅极接触。
16.根据权利要求14所述的结构，其中所述至少一个源极和漏极接触是阶梯形的。
17.根据权利要求16所述的结构，还包括位于所述至少一个源极和漏极接触之上的电介质帽。
18.根据权利要求14所述的结构，其中所述衬里由TiN材料构成。
19.一种制造半导体结构的方法，包括：
形成多个栅极结构，所述多个栅极结构包括源极和漏极区以及栅极材料；
形成层间电介质层，所述层间电介质层包括位于栅极结构的源极和漏极区之上的牺牲层和电介质帽；
打开所述电介质帽的一部分以暴露所述牺牲层；
去除所述牺牲层以暴露所述源极和漏极区；
暴露所述栅极材料；
在暴露的栅极材料和暴露的源极和漏极区上同时形成偏移金属化特征；以及
形成从所述金属化特征延伸的偏移接触。
20.根据权利要求19所述的方法，还包括在形成所述金属化特征之前，在所述暴露的栅极材料和所述暴露的源极和漏极区上沉积衬里。
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