TW201935650A - 中段連線結構 - Google Patents

中段連線結構 Download PDF

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TW201935650A
TW201935650A TW107116133A TW107116133A TW201935650A TW 201935650 A TW201935650 A TW 201935650A TW 107116133 A TW107116133 A TW 107116133A TW 107116133 A TW107116133 A TW 107116133A TW 201935650 A TW201935650 A TW 201935650A
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Taiwan
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source
gate
contacts
item
drain regions
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TW107116133A
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TWI712142B (zh
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臧輝
謝瑞龍
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明一般係關於半導體結構，尤其關於中段連線結構及其製造方法。該結構包括：複數個閘極結構，其包含源極和汲極區；接點，其連接至該等源極和汲極區；接點，其連接至與已連接至該等源極和汲極區的該等接點偏離之該等閘極結構；以及互連結構，其與該等閘極結構的該等接點以及該等源極和汲極區的該等接點電性接觸。

Description

中段連線結構
本發明一般係關於半導體結構，尤其關於中段連線結構及其製造方法。
隨著半導體製程持續往下減小，例如縮小，部件之間所要的空間(即間距)也變得更小。因此，在較小的技術節點中，由於關鍵尺寸(critical dimension，CD)縮放和製程能力，以及用於製造這種結構的材料，製造後端連線(back end of line，BEOL)和中段連線(middle of line，MOL)金屬化部件(例如，互連)變得更加困難。
例如：若要製造源極與汲極接點的互連結構，則需要移除與閘極結構相鄰的介電材料。利用蝕刻製程移除該介電材料，不過這也會侵蝕到該閘極結構的間隙壁材料。如此，在形成用於源極與汲極接點的開口之下游蝕刻製程中，會侵蝕到用於該閘極結構的間隙壁與側壁之該低k介電材料。這些材料不見之後將露出該閘極結構的金屬材料，導致該閘極結構的金屬材料與用於形成該接點的金屬材料短路。
在當前的結構中，閘極結構之間必須有最小間隔，以避免該等閘極接點與該等源極與汲極接點之間短路。然而，隨著裝置持續往下減小，在這些傳統結構當中就更難以達成最小間隔以及其他設計規則。
在本發明的態樣中，一種結構包含：複數個閘極結構，其包含源極和汲極區；接點，其連接至該等源極和汲極區；接點，其連接至與已連接至該等源極和汲極區的該等接點偏離之該等閘極結構；以及互連結構，其與該等閘極結構的該等接點以及該等源極和汲極區的該等接點電接觸。
在本發明的態樣中，一種結構包含：複數個閘極結構，其包含源極和汲極區、閘極接點和從該等閘極接點延伸出來的互連結構；至少一源極和汲極接點，其位於相對於該等閘極接點的一不同高度上；以及一襯墊，其位於該等源極和汲極區、該等閘極接點以及該至少一源極和汲極接點上。
在本發明的態樣中，一種方法包含：形成包含源極和汲極區以及閘極材料的複數個閘極結構；形成包含閘極結構的源極和汲極區之上一犧牲層和一介電蓋的一中間介電層；打開一部分該介電蓋來露出該犧牲層；移除該犧牲層暴露出該源極和汲極區；將該等閘極材料暴露；在該等已暴露的閘極材料與該等已暴露的源極和汲極區上同時形成偏移金屬化部件；以及形成從該等金屬化部件延伸出來的偏移接點。
100‧‧‧結構
110‧‧‧主動區
105‧‧‧基材
150‧‧‧閘極結構
115‧‧‧源極和汲極區
140‧‧‧側壁間隙壁
120‧‧‧襯墊
125‧‧‧非晶矽材料
130‧‧‧中間介電質層
135‧‧‧閘極材料
145‧‧‧覆蓋材料
155‧‧‧溝渠
160‧‧‧介電材料
165‧‧‧STI結構
170‧‧‧光阻
175‧‧‧溝渠
175'‧‧‧溝渠
180‧‧‧犧牲材料
170'‧‧‧光阻
185‧‧‧溝渠
190‧‧‧矽化物襯墊
195‧‧‧金屬材料
200‧‧‧源極和汲極接點
205‧‧‧閘極接點
210‧‧‧蝕刻停止層
215‧‧‧ILD層
220‧‧‧互連結構
225‧‧‧互連結構
利用本發明示範具體實施例的非限制範例，參考提及的許多圖式，從下列詳細描述當中描述本發明。
圖1A至圖1C顯示根據本發明態樣的其他部件之間閘極結構與個別製程。
圖2A和圖2B顯示根據本發明態樣的其他部件之間淺溝渠隔離區與個別製程。
圖3A至圖3D顯示根據本發明態樣的其他部件之間淺溝渠 隔離結構與個別製程。
圖4A至圖4C顯示根據本發明態樣的其他部件之間具有已暴露的非晶矽的結構與個別製程。
圖5A至圖5C顯示根據本發明態樣的其他部件之間具有已暴露的源極和汲極區的結構與個別製程。
圖6A至圖6C顯示根據本發明態樣的其他部件之間填充虛置材料與個別製程。
圖7A至圖7D顯示根據本發明態樣的其他部件之間閘極接點、源極和汲極接點與個別製程。
圖8A至圖8D顯示根據本發明態樣的其他部件之間互連結構與個別製程。
本發明一般係關於半導體結構，尤其關於中段連線結構及其製造方法。在具體實施例內，本文所提供的製程及結構允許該等閘極接點與該等源極和汲極接點彼此偏移。此外，本文所提供的製程及結構允許該等閘極接點與該等源極和汲極接點彼此位於不同高度上。有利地，通過在不同高度上具有偏移的接點，避免在該製程期間，即在該等閘極接點與該等源極和汲極接點的互連結構成形期間，該等閘極結構的該等金屬化部件與該等源極和汲極區的該等金屬化部件之間短路。如此，本文所描述的該等結構與製程提供互連結構給該等閘極接點與該等源極和汲極接點，沒有任何短路問題。
本發明的結構可用許多不同工具以許多方式來製造。一般來說，該等方法與工具用來形成尺寸為微米與奈米等級的結構。用來製造本發明結構的該等方法，即技術，採用積體電路(integrated circuit，IC)技術，例如：這些結構建立在晶圓上，並且通過在晶圓頂部上以光微影蝕刻製程 來製作圖案的材料膜來實現。尤其是，該等結構的製造使用三種基本構件：(i)將材料薄膜沉積在一基材上，(ii)利用光微影蝕刻成像將一製圖光罩應用於該等薄膜頂端上，以及(iii)依照該光罩的選擇來蝕刻該等薄膜。
圖1A至圖1C顯示根據本發明態樣的一傳入結構與個別製程。尤其是，圖1A顯示結構100的頂端視圖，而圖1B顯示在X軸方向內的剖面圖，並且圖1C顯示在Y軸方向內的剖面圖。結構100包含一主動區110，可形成一裝置，例如電晶體。結構100進一步包含由合適半導體材料構成的一基材105，例如基材105可由任何合適的材料構成，包括但不受限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP等等。在具體實施例內，基材105可代表鰭狀結構或平面部件。
在具體實施例內，使用側壁影像轉印(sidewall image transfer，SIT)技術，可形成一鰭狀結構。在SIT技術範例中，例如SiO2這類芯軸材料使用傳統CVD製程沉積於基材105上。在該芯軸材料上形成一抗蝕層，並曝光來形成一圖案(開口)，然後通過該開口執行一反應離子蝕刻，來形成該等芯軸。在具體實施例內，根據該鰭狀結構的所要尺寸，該等芯軸可具有不同寬度及/或間隔。間隙壁形成於該等芯軸的側壁上，其材料較佳與該等芯軸不同，並使用精通技術人士已知的傳統沉積製程來形成。例如該等間隙壁的寬度與該窄鰭狀結構的尺寸匹配。使用對芯軸材料有選擇性的傳統蝕刻製程移除或剝離該等芯軸，然後在該等間隙壁的間隙之內執行蝕刻，以形成該子微影部件。然後可剝離該等側壁間隙壁。
閘極結構150形成於基材105上。如所了解，閘極結構150可為平面閘極結構或finFET閘極結構。在兩案例中，可使用任何已知的閘極成形製程來製造閘極結構150，例如業界內熟知的置換閘極製程。在此方式中，閘極結構150可為置換閘極結構。在具體實施例內，該閘極製程從例如以多晶矽(poly-Si)的虛置閘極(dummy gate)材料形成虛置閘極結構開始。使用例如任何傳統方法，在基材105內該等虛置閘極結構的側邊上形 成源極和汲極(S/D)區域115，例如：S/D區域115可由精通技術人士所了解的離子植入製程、摻雜製程或透過擴散製程來形成，如此不需要進一步解釋就可了解本發明。在進一步具體實施例內，S/D區域115可為該等虛置閘極結構之間在基材105的表面上磊晶生長形成的凸起S/D區域。如此，複數個閘極結構150包含S/D區域115。
側壁間隙壁140，例如低k介電質，可沉積在該虛置閘極材料的該等側壁上。通過傳統CVD製程來沉積側壁間隙壁140，接著進行圖案製作製程，例如非等向性蝕刻製程，來移除該結構水平表面上的任何材料。襯墊120沉積在該等虛置閘極結構的側壁間隙壁140之側壁上以及S/D區域115之上。在具體實施例內，通過化學氣相沉積(CVD)製程沉積襯墊120。襯墊120可由任何合適的材料構成，例如SiN。
圖1B和圖1C顯示沉積在襯墊120之上的一非晶矽(α-Si)材料125。如此，α-Si材料125位於S/D區域115之上。α-Si材料125可通過傳統沉積製程，例如CVD製程來沉積，接著蝕刻。通過反應離子蝕刻(RIE)使用對於α-Si材料125具有選擇性的化學物來蝕刻α-Si材料125。在具體實施例內，α-Si材料125凹陷到例如約10nm-50nm範圍內的高度。一層間介電(interlevel dielectric ILD)層130沉積在α-Si材料125之上的該凹陷內。ILD層130可由CVD製程所沉積的任何合適介電材料所構成，例如氧化物。ILD層130沉積之後接著化學機械拋光(chemical mechanical polishing，CMP)製程。在此方式中，用雙層材料製作ILD層：底部犧牲層，即α-Si材料125，以及頂端介電蓋，即ILD層130。尤其是，ILD層包含閘極結構150的源極和汲極區115之上的一犧牲層和一介電蓋。
將該虛置閘極材料，例如多晶矽，剝離，形成溝渠並露出基材105。使用對該虛置閘極材料有選擇性的傳統蝕刻製程，移除或剝離該等虛置閘極材料芯軸，閘極結構150形成於基材105上的該溝渠之內。在具體實施例內，閘極結構150包括閘極介電材料以及金屬化部件。該等閘極 介電材料可為例如高k閘極介電材料，例如鉿基介電質。在進一步具體實施例內，該等高k介電材料可包括但不受限於：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括以上多層的組合。根據特定應用以及設計參數，該等金屬化部件，即閘極材料135，可包括任何功函數金屬或金屬的任意組合。例如在具體實施例內，閘極材料135可為鎢(W)材料。
在具體實施例內，蝕刻閘極材料135來在閘極結構150內形成凹陷。在此方式中，閘極結構150為凹陷的閘極結構。使用對於閘極材料135有選擇性的蝕刻製程，例如濕蝕刻製程，來蝕刻閘極材料135。例如使用CVD製程接著CMP製程，在閘極材料135之上的該等凹陷之內沉積覆蓋材料145。覆蓋材料145可為任何合適的覆蓋材料，例如SiN。
圖2A和圖2B顯示ILD層130內的淺溝渠隔離(shallow trench isolation，STI)區域的形成。在具體實施例內，使用傳統微影與蝕刻技術，例如RIE製程，在ILD層130內形成溝渠155。例如：ILD層130之上形成的一光阻暴露在能量(光線)之下，來形成一圖案(開口)。使用選擇性化學的蝕刻製程，例如RIE，將用來通過該光阻的該開口，在ILD層130內形成一或多個溝渠155。然後用傳統氧氣灰化製程或其他已知剝除劑移除該光阻。
圖3A至圖3D例示含額外剖面圖的結構100。尤其是，圖3A顯示結構100的頂端視圖，並且圖3B和圖3C顯示在X軸方向內的剖面圖，而圖3D顯示在Y軸方向內的剖面圖。圖3D顯示溝渠155填滿介電材料160來形成STI結構165。在具體實施例內，在其他範例之間，介電材料160可由低k介電材料構成，像是SiOC。通過CVD製程接著CMP製程，進行介電材料160的沉積。
圖4A至圖4C顯示形成於STI結構165和ILD層130之上的光阻170。在具體實施例內，光阻170暴露在能量(光線)之下，來形成一 圖案(開口)。使用含選擇性化學物的蝕刻製程，例如RIE製程，將用來通過光阻170的開口，在ILD層130內形成一或多個溝渠175，露出α-Si材料125。尤其是，圖4C顯示開啟一部分介電蓋，即ILD層130，來露出該犧牲層，即α-Si材料125。如圖4A和圖4C內所示，部分ILD層130保留，相鄰於介電材料160。
圖5A至圖5C顯示移除α-Si材料125，形成溝渠175'以露出源極和汲極(S/D)區115。通過傳統蝕刻製程，例如濕蝕刻製程，可移除α-Si材料125。在具體實施例內，α-Si材料125的蝕刻可使用或不使用光阻170。在具體實施例內，α-Si材料125的蝕刻無方向性，留下部分ILD層130在X軸方向內和Y軸方向內，如圖5A和圖5C內所示。然後用傳統氧氣灰化製程或其他已知剝除劑移除光阻170。
圖6A至圖6C顯示使用犧牲材料180填滿溝渠175'。在具體實施例內，在其他範例之間，犧牲材料180可為SOH、無結晶碳(α-C)或有機平坦化層(organic planarization layer，OPL)。犧牲材料180用來建立供光阻170'沉積的平坦表面，這將用於蝕刻閘極結構150的覆蓋材料145(在後續製程的X軸方向內)。在具體實施例內，光阻170'形成於STI結構165、ILD層130以及犧牲材料180之上。光阻170'暴露在能量(光線)之下，來形成一圖案(開口)。將使用含選擇性化學劑的蝕刻製程，例如RIE，通過該光阻開口來移除覆蓋材料145，因此在X軸方向內形成閘極結構150的閘極材料135之一或多個溝渠185。尤其是，圖6A顯示露出閘極結構150的閘極材料135。通過傳統氧氣灰化製程或其他已知剝除劑可移除光阻170'，而通過選擇性蝕刻可移除犧牲材料180。覆蓋材料145，即該閘極蓋的移除，用於後續至閘極結構150的閘極接點之形成。
圖7A至圖7D顯示根據本發明態樣的其他部件之間源極、汲極和閘極金屬化部件與個別製程。尤其是，矽化物襯墊190沉積在溝渠185內(在閘極結構150，尤其是閘極材料135之上)以及S/D區115之上。 尤其是，圖7B顯示在形成該等金屬化部件之前，在已露出閘極材料135上以及已露出源極和汲極區115上沉積一襯墊190。襯墊190經歷矽化物製程。襯墊190可使用物理氣相沉積(physical vapor deposition，PVD)或CVD製程來沉積。在其他範例之間，襯墊190可為Ti、TiN、TaN、Ru和Co。在該矽化物製程之後，金屬材料195沉積在襯墊190上，來形成源極和汲極接點200以及閘極接點205。在此方式中，利用相同金屬材料195同時形成源極和汲極接點200與閘極接點205。
金屬材料195可通過CVD製程沉積，並且可為任何合適的導電材料。例如，金屬材料195可為鎢(W)、鈷(Co)或銅(Cu)。金屬材料195的沉積接著進行CMP製程。源極和汲極接點200連接至S/D區域115，而閘極接點205則連接至閘極結構150。在此方式中，閘極結構150的閘極接點205包含一襯墊190和一填充材料，即金屬材料195。進一步，襯墊190在S/D區域115、閘極材料135、閘極接點205以及至少源極和汲極接點之一者之上。
如圖7A內所示，源極和汲極接點200都在X軸方向與Y軸方向內偏離閘極接點205。在此方式中，連接至閘極結構150的閘極接點205偏離連接至S/D區域115的源極和汲極接點200。特別是，閘極結構150的閘極接點205在X軸方向和Y軸方向內偏離S/D區域115的源極和汲極接點200。尤其是，圖7B顯示在已露出閘極材料135和已露出S/D區域115上同時形成偏移金屬化部件，即接點200、205。進一步如圖7B所示，源極和汲極接點200位於與閘極接點205不同的高度上。尤其是，源極和汲極接點200位於低於閘極接點205的高度上，如此至少源極和汲極接點200之一者位於相對於閘極接點205不同的高度上。在此方式中，閘極結構150的閘極接點205位於與S/D區域115的源極和汲極接點200不同的高度上。
在具體實施例內，源極和汲極接點200為階梯狀，其上具有介電蓋，即ILD層130。尤其是，該至少一源極和汲極接點200為階梯狀。 在此方式中，襯墊190將直接接觸S/D區域115，例如S/D區域115的矽化物、閘極結構150的側壁間隙壁140以及在源極和汲極接點200之上的該介電蓋底下。尤其是如圖8B內所示，ILD層130在源極和汲極接點200形成該介電蓋。尤其是，該介電蓋包含一氧化物材料，即ILD層130的氧化物，以及襯墊120。
本文內說明的該等結構與製程提供避免較小技術節點內短路之優點。尤其是，通過同時由金屬材料195形成源極和汲極接點200以及閘極接點205，但是在不同高度上並且彼此偏移，來避免短路。
圖8A至圖8D顯示延伸自源極和汲極接點200以及閘極接點205的金屬化部件(例如互連接點結構)之形成。尤其是，在ILD層130和閘極接點205之上沉積一蝕刻停止層210。在具體實施例內，通過CVD製程沉積蝕刻停止層210，並且該層可由氮化物材料構成，例如SiN。通過例如CVD製程在蝕刻停止層210之上沉積一ILD層215。在具體實施例內，ILD層215可由例如氧化物材料構成。接著對ILD層215的沉積進行CMP製程。
使用傳統微影與蝕刻製程，例如RIE製程，可形成延伸自接點200、205的互連結構220、225。例如：ILD層215之上形成的一光阻暴露在能量(光線)之下，來形成一圖案(開口)。使用含選擇性化學物的蝕刻製程，例如反應離子蝕刻(RIE)，將用來通過該光阻的該開口，在ILD層215內形成一或多個溝渠。然後用傳統氧氣灰化製程或其他已知剝除劑移除該光阻。
在移除該光阻之後接著通過傳統沉積製程，例如CVD製程，來沉積導電材料，以形成互連結構220、225。利用傳統CMP製程，可移除ILD層215表面上的任何殘留導電材料。用來形成互連結構220、225的該導電材料可為任何合適的導電材料，例如鎢(W)。在具體實施例內，互連結構220與源極和汲極接點200直接電接觸，而互連結構225則與閘極 接點205直接電接觸。在此方式中，互連結構220、225與閘極結構150的接點以及源極和汲極區(S/D)115的接點電接觸。圖8B顯示形成延伸自該等金屬化部件，即接點200、205，的偏移接點，即互連結構220、225。此外，圖8B顯示複數個閘極結構150，其包含源極和汲極區115、閘極材料135、閘極接點205以及延伸自閘極接點205的互連結構225。
應了解，本文內說明的該等製程以及生成結構將用來在MOL製程期間進一步保護該閘極結構的該閘極金屬。該等生成結構，例如側壁結構，將因此避免與互連或源極/汲極區的其他配線結構發生短路。因此，本文內說明的該等製程與結構將提高產率。
上述該(等)方法用於積體電路晶片製造。生成的積體電路晶片可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成裸晶粒或已封裝形式來散佈。在後者案例中，晶片固定在單晶片封裝內(像是塑膠載體，具有導線黏貼至主機板或其他更高層載體)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中，晶片與其他晶片、離散電路元件以及/或其他信號處理裝置整合成為部分(a)中間產品，像是主機板，或(b)末端產品。末端產品可為包括積體電路晶片的任何產品，範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
許多本發明具體實施例的描述已經為了說明而呈現，但非要將本發明受限在所公布的具體實施例中。在不脫離所描述具體實施例之範疇與精神的前提下，所屬技術領域中具有通常知識者將瞭解許多修正例以及變化例。本文內使用的術語係為了能最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進，或可讓所屬技術領域中具有通常知識者能理解本文所揭示的具體實施例。

Claims (20)

  1. 一種結構，包含：複數個閘極結構，其包含源極區與汲極區；接點，其連接至該等源極和汲極區；接點，其連接至與已連接至該等源極和汲極區的該等接點偏離之該等閘極結構；以及互連結構，其與該等閘極結構的該等接點以及該等源極和汲極區的該等接點電接觸。
  2. 如申請專利範圍第1項所述之結構，其中該等閘極結構的該等接點包含一襯墊以及一填充材料。
  3. 如申請專利範圍第2項所述之結構，其中該襯墊為TiN。
  4. 如申請專利範圍第3項所述之結構，其中該TiN襯墊在該源極和汲極區之上。
  5. 如申請專利範圍第4項所述之結構，其中該填充材料為鈷或鎢。
  6. 如申請專利範圍第1項所述之結構，其中該等閘極結構的該等接點位於與該等源極和汲極區的該等接點不同之高度上。
  7. 如申請專利範圍第1項所述之結構，其中該等閘極結構的該等接點在一X軸方向內偏離該等源極和汲極區的該等接點。
  8. 如申請專利範圍第1項所述之結構，其中該等閘極結構的該等接點在 一Y軸方向內偏離該等源極和汲極區的該等接點。
  9. 如申請專利範圍第1項所述之結構，進一步包含在該等源極和汲極區的該等接點上之一介電蓋。
  10. 如申請專利範圍第9項所述之結構，其中該介電蓋包含氧化物材料以及一襯墊。
  11. 如申請專利範圍第10項所述之結構，其中該襯墊由氮化物材料構成。
  12. 如申請專利範圍第1項所述之結構，其中該等閘極結構為置換閘極結構。
  13. 如申請專利範圍第1項所述之結構，其中該等閘極結構為凹陷閘極結構。
  14. 一種結構，包含：複數個閘極結構，其包含源極和汲極區、閘極接點和從該等閘極接點延伸出來的互連結構；至少一源極和汲極接點，其位於相對於該等閘極接點的一不同高度上；以及一襯墊，其位於該等源極和汲極區、該等閘極接點以及該至少一源極和汲極接點上。
  15. 如申請專利範圍第14項所述之結構，其中該至少一源極和汲極接點在一X軸方向或Y軸方向內偏離該等閘極接點。
  16. 如申請專利範圍第14項所述之結構，其中該至少一源汲和汲極接點為階梯狀。
  17. 如申請專利範圍第16項所述之結構，進一步包含在該至少一源極和汲極接點上之一介電蓋。
  18. 如申請專利範圍第14項所述之結構，其中該襯墊由一TiN材料構成。
  19. 一種方法，包含：形成包含源極和汲極區以及閘極材料的複數個閘極結構；形成包含閘極結構的源極和汲極區之上的一犧牲層和一介電蓋的一中間介電層；打開一部分該介電蓋來露出該犧牲層；移除該犧牲層暴露出該源極和汲極區；將該等閘極材料暴露；在該等已暴露的閘極材料與該等已暴露的源極和汲極區上同時形成偏移金屬化部件；以及形成從該等金屬化部件延伸出來的偏移接點。
  20. 如申請專利範圍第19項所述之方法，進一步包含在形成該等金屬化部件之前，在該等已暴露的閘極材料以及該等已暴露的源極和汲極區上沉積一襯墊。
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