TWI699865B - 中段製程結構 - Google Patents

中段製程結構 Download PDF

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TWI699865B
TWI699865B TW107117560A TW107117560A TWI699865B TW I699865 B TWI699865 B TW I699865B TW 107117560 A TW107117560 A TW 107117560A TW 107117560 A TW107117560 A TW 107117560A TW I699865 B TWI699865 B TW I699865B
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gate
source
drain
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TW201933570A (zh
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臧輝
許國偉
凱斯 陶巴克曼
維拉傑 薩德塞
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明一般關於半導體結構，特別是關於中段製程結構及製造方法。結構包含：包含源極及/或汲極金屬化特徵的複數個閘極結構；在閘極結構的側壁上且由第一材料及第二材料所構成的間隙壁；以及與源極及/或汲極金屬化特徵電性接觸且藉由間隙壁與閘極結構分隔的接觸。

Description

中段製程結構
本發明一般關於半導體結構，特別是關於中段製程結構及製造方法。
隨著半導體製程尺寸持續地降低(例如縮小)，特徵之間的期望間隔(即間距)也變得更小。為此，在較小的技術節點中，由於關鍵尺寸(critical dimension，CD)縮放和製程能力以及用於製造這類結構的材料，後段製程(back end of line，BEOL)及中段製程(middle of line，MOL)金屬化特徵(例如互連)變得更加難以製造。
舉例來說，為了製造用於源極及汲極接觸的互連結構，必須移除與閘極結構相鄰的介電材料。介電材料的去除是藉由蝕刻製程所提供，蝕刻製程也傾向於侵蝕閘極結構的間隙壁材料。亦即，用於閘極結構的間隙壁或側壁的低k介電材料可能在用以形成汲極和源極接觸的開口的下游蝕刻製程中被侵蝕。這種材料的耗損將暴露閘極結構的金屬材料，導致閘極結構的金屬材料與用於形成接觸的金屬材料本身之間發生短路。
在本發明的一態樣中，一結構包含：包含源極及/或汲極金屬化特徵的複數個閘極結構；在閘極結構的側壁上且由第一材料及第二材 料所構成的間隙壁(spacer)；以及與源極及/或汲極金屬化特徵電性接觸且藉由間隙壁與閘極結構分隔的接觸。
在本發明的一態樣中，一結構包含：複數個閘極結構，其包含源極/汲極區域、閘極材料、側壁間隙壁及在閘極材料及側壁間隙壁上的一覆蓋材料；與源極/汲極區域電性接觸的複數個源極/汲極接觸；沿著側壁間隙壁之由頂部材料及底部材料所構成的一襯層；以及延伸至源極/汲極接觸並藉由襯層與閘極金屬分隔的接觸。
在本發明的一態樣中，一方法包含：形成包含源極及/或汲極金屬化特徵的複數個閘極結構；在閘極結構的側壁上形成包含第一材料及第二材料的間隙壁；以及形成與源極及/或汲極金屬化特徵電性接觸並藉由間隙壁與閘極結構分隔的接觸。
100:結構
105:基板
110:閘極結構
112:閘極材料
115:側壁間隙壁
120:S/D區域
125:襯層
130:絕緣體材料
135:凹陷
140:覆蓋材料
142:斜度
150:溝渠
155:襯層
160:金屬填充
165:金屬化特徵
170:凹陷
170’:凹陷
175:氣隙
180:間隙壁材料
182:間隙壁
190:凹陷
195:絕緣體材料
200:金屬化結構
在下面的詳細描述中，將透過本發明的範例性具體實施例的非限制性範例、參考所提到的複數個圖式來描述本發明。
圖1顯示根據本發明態樣之閘極結構及其他特徵及相應的製造程序；圖2顯示根據本發明態樣之閘極結構的凹陷閘極材料及其他特徵及相應的製造程序；圖3顯示根據本發明態樣的凹陷閘極材料上的覆蓋材料及其他特徵及相應的製造程序；圖4顯示根據本發明態樣的源極/汲極金屬化特徵(接觸)及其他特徵及相應的製造程序；圖5顯示根據本發明態樣的凹陷襯層材料及其他特徵及相應的製造程序；圖6顯示根據本發明態樣的襯層材料的凹陷中的間隙壁材 料及其他特徵及相應的製造程序；圖7顯示根據本發明態樣的在源極/汲極金屬化特徵的凹陷中所形成的絕緣體層及其他特徵及相應的製造程序；圖8顯示根據本發明態樣的電性地連接至源極/汲極金屬化特徵的接觸及其他特徵及相應的製造程序；以及圖9顯示根據本發明其他態樣的一替代結構及相應的製造程序。
本發明一般關於半導體結構，特別是關於中段製程結構及製造方法。在具體實施例中，本文所提供的製程及結構使用在閘極結構的側邊上的間隙壁，以避免源極/汲極(S/D)接觸與閘極結構的金屬化發生短路。有利地，間隙壁將提供額外的材料以避免在製造程序期間(亦即在形成源極/汲極接觸的互連結構的期間)發生短路。本文所提供的結構也提供了具有改良的低寄生電容的閘極結構。
本發明的結構可使用多種不同的工具、以多種方式來製造。然而，一般而言，使用方法和工具係用以形成尺寸在微米及奈米尺度的結構。用以製造本發明的結構的方法(即技術)採用自積體電路(integrated circuit，IC)技術。舉例來說，結構係建立於晶圓上並實現於晶圓頂部上由光學微影製程所圖案化的材料薄膜中。特別地，結構的製造使用三個基本的建構部分：(i)在基板上沉積材料的薄膜，(ii)藉由光學微影成像在薄膜頂部施加圖案化光罩，以及(iii)對光罩選擇性地蝕刻薄膜。
圖1顯示根據本發明態樣之一進入結構及相應的製造程序。更特別地，圖1顯示包含由適當半導體材料所構成的基板105的結構100。舉例來說，基板105可由任何合適的材料所構成，其包含但不限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP等。在具體實施例中，基板105可代 表鰭式結構或平面特徵。
在具體實施例中，可使用側壁影像轉移(sidewall image transfer，SIT)技術來製造鰭式結構。在SIT技術的範例中，使用傳統的CVD製程沉積心軸材料(例如SiO2)於基板105上。光阻劑形成於心軸材料上，並對光暴露以形成一圖案(開口)。通過開口執行反應性離子蝕刻，以形成心軸。在具體實施例中，根據所需的鰭式結構尺寸，心軸(mandrel)可具有不同的寬度及/或間隔。間隙壁形成於心軸的側壁上，其材料較佳為不同於心軸的材料，且其使用熟此技藝者所習知的傳統沉積製程來形成。舉例來說，間隙壁可具有與窄鰭式結構的尺寸匹配的寬度。使用對心軸材料具有選擇性的傳統蝕刻製程將心軸移除或剝除。接著，在間隙壁的間隔內執行蝕刻，以形成次微影特徵。接著，可剝除側壁間隙壁。
仍參考圖1，閘極結構110形成於基板105上。應了解到，閘極結構110可為平面閘極結構或鰭式電晶體(finFET)閘極結構。在任一情況下，可使用任何已知的閘極形成製程(例如，本領域中已知的替換閘極製造程序或閘極優先製程)來製造閘極結構110。在具體實施例中，閘極結構110包含閘極介電材料及金屬化特徵。閘極介電材料可例如為高k閘極介電材料，例如鉿基介電質。在其他具體實施例中，高k介電材料可包含但不限於：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3、及包含其多層的組合。根據具體的應用及設計參數，金屬化特徵(即閘極材料112)可包含任何功函數金屬或任何金屬組合。舉例來說，在具體實施例中，閘極材料112可為鎢(W)材料。
仍參考圖1，側壁間隙壁115(例如低k介電質)可沉積於閘極結構110的側壁。側壁間隙壁115可藉由傳統化學氣相沉積(CVD)製程來沉積，並接著進行圖案化製程(例如異向性蝕刻製程)以從結構的水平表面移除任何材料。可使用例如任何傳統方法在基板105中形成源極及汲極區域(S/D)120於閘極結構110的側面(例如側壁間隙壁115的側面)上。舉例來說， S/D區域120可藉由熟此技藝者所習知的離子佈植製程、摻雜製程或透過擴散製程來形成，因此無需進一步解釋來理解本發明。在其他的具體實施例中，S/D區域120可為凸起的S/D區域，其藉由磊晶成長形成於閘極結構110之間的基板105的表面上。
圖1更顯示在閘極結構110之間、特別是在側壁間隙壁115之間形成的溝渠內所沉積的襯層125及絕緣體材料130。在具體實施例中，可藉由CVD製程來沉積襯層125及絕緣體材料130。舉例來說，襯層125可由任何合適的材料(例如SiN)所構成，而絕緣體材料可由氧化物所構成。
在圖2中，藉由蝕刻閘極結構110形成凹陷135。特別地，藉由蝕刻閘極結構110的金屬化特徵(即閘極材料112)、接著蝕刻側壁間隙壁115來形成凹陷135。在具體實施例中，閘極材料112及側壁間隙壁115係凹陷至低於襯層125及絕緣體材料130的表面。舉例來說，閘極結構110可蝕刻約10%至15%的原始高度，例如約30nm至40nm。在具體實施例中，可使用對這類結構的特定材料具有選擇性的化學反應的反應性離子蝕刻(RIE)來蝕刻閘極材料112及側壁間隙壁115。有利地，由於選擇性化學反應，蝕刻製程不需要光罩。
在圖3中，形成覆蓋材料140作為在閘極結構110及側壁間隙壁115上的一層(例如在凹陷中)。以此方式，閘極結構110可包含閘極材料112、側壁間隙壁115及覆蓋材料140。在具體實施例中，可藉由CVD製程將覆蓋材料140沉積於凹陷135內，接著進行化學機械研磨(CMP)製程。應了解到，覆蓋材料140將在後續的源極/汲極接觸或互連形成期間(例如蝕刻製程以形成源極/汲極接觸或互連)提供對閘極結構110的金屬化特徵的保護。覆蓋材料140可例如由SiN構成。
仍參考圖3，藉由移除襯層125及絕緣體材料130來形成溝渠150於閘極結構110之間。在具體實施例中，可藉由傳統RIE製程來移除襯層125及絕緣體材料130。襯層125及絕緣體材料130的蝕刻或移除將暴露S/D區 域120，並形成覆蓋材料140的一斜度142。
圖4顯示根據本發明態樣的源極/汲極金屬化特徵及其他特徵及相應的製造程序。特別地，使用例如物理氣相沉積(PVD)或CVD製程來沉積襯層155於側壁間隙壁115的側壁上。襯層155可為Ti、TiN、TaN、Ru及Co等等。在具體實施例中，襯層155可具有範圍在約2nm至20nm的厚度，其中期望的厚度在約8nm至10nm的範圍；然而此處也考慮其他的尺寸。在具體實施例中，襯層155也將直接接觸S/D區域120(S/D區域的矽化物)。在沉積襯層155之後，在溝渠150內以及在襯層155上沉積金屬填充160，以形成源極/汲極金屬化特徵165。以此方式，複數個閘極結構110可包含源極及/或汲極金屬化特徵165。金屬填充160可藉由CVD製程來沉積，且可為任何合適的導電材料。舉例來說，金屬填充160可為T、Co、或Cu。以此方式，源極及/或汲極金屬化特徵165包含導電填充材料(即金屬填充160)，其與閘極結構110的S/D區域120電性接觸。
在圖5中，從源極及/或汲極金屬化特徵165移除部分的襯層155，以在金屬填充160與覆蓋材料140之間形成凹陷170。在具體實施例中，可藉由濕式蝕刻製程來使襯層155凹陷，其使用化學物質來移除襯層155的材料(對剩餘材料具有選擇性)，例如Ti、TiN、TaN、Ru及Co等。在具體實施例中，凹陷170可具有各種深度。舉例來說，凹陷170的深度可延伸低於閘極結構110的表面，例如低於覆蓋材料140或閘極結構110的金屬材料(即閘極材料112)的表面。在具體實施例中，凹陷170也可在覆蓋材料140的範圍內。
在圖6中，沉積間隙壁材料180於凹陷170內以形成間隙壁182。在具體實施例中，間隙壁材料180與襯層155的材料不同，較佳為更能承受下游蝕刻製程的更加堅固的材料。舉例來說，第二材料或頂部材料(即間隙壁材料180)可為高k介電材料或低k介電材料，其厚度類似於襯層155的厚度，例如2nm至20nm。更特別地，間隙壁材料180可為SiN、Al2O3、或HfO2等等。以此方式，第二或頂部材料為SiN、Al2O3及HfO2的其中一者， 且第一或底部材料為Ti、TiN、TaN、Ru或Co的其中一者。可藉由傳統的CVD製程沉積間隙壁180以填充凹陷170，接著進行CMP製程或其他蝕刻製程，例如回蝕、濕式蝕刻、或乾式蝕刻製程。
在具體實施例中，間隙壁材料180及相應的間隙壁182將用於進一步防止在隨後的MOL蝕刻製程期間暴露閘極結構110。特別地，間隙壁材料180將有效地避免蝕刻製程暴露閘極結構110的閘極金屬(即閘極材料112)，從而避免在閘極金屬及源極/汲極接觸或在MOL製程期間形成的其他金屬化特徵(例如互連)之間發生短路。如圖6所示，襯層材料155及間隙壁材料180可作為閘極結構110的側壁間隙壁115上的間隙壁，且可由第一材料(其為襯層155)及第二材料(其為間隙壁材料180)所構成。或者，襯層材料155連同間隙壁材料180可視為一襯層，其中襯層由沿著側壁間隙壁115的頂部材料(即間隙壁材料180)及底部材料(即襯層材料155)所構成。在具體實施例中，由間隙壁材料180所形成的間隙壁182與閘極結構110上的側壁間隙壁115及覆蓋材料140以及源極及/或汲極金屬化特徵165直接接觸。
圖7顯示形成於源極及/或汲極金屬化特徵165的凹陷190中的絕緣體材料195及其他特徵。更特別地，對金屬填充160進行選擇性蝕刻製程以在間隙壁材料180之間形成凹陷190，並保持由間隙壁材料180所形成的間隙壁182的完整。在具體實施例中，凹陷190將具有在間隙壁182範圍內的一深度，例如較佳在閘極結構110的金屬化特徵(即閘極材料112)之上。以此方式，藉由維持凹陷190在間隙壁材料180所形成的間隙壁182的範圍內的深度，間隙壁182將特別地能夠在隨後的蝕刻製程期間防止覆蓋材料140受到侵蝕。亦即，第二材料或頂部材料(即間隙壁材料180)保護覆蓋材料層140在蝕刻製程期間免於受到侵蝕。絕緣體材料195可沉積在凹陷190內。絕緣體材料195可為由CVD製程所沉積的層間介電材料(例如氧化物)。
在圖8中，金屬化結構200形成於絕緣體材料195中，並作用為與S/D區域120的金屬填充160直接電性接觸的接觸。特別地，金屬化結構 200與源極及/或汲極金屬化特徵165電性接觸，並藉由間隙壁材料180與閘極結構110分隔。以此方式，接觸(即金屬化結構200)延伸至S/D區域120，並藉由襯層材料155及間隙壁材料180所形成的襯層而與閘極材料112分隔。在具體實施例中，金屬化結構200可為由鎢材料所構成的互連結構，其與S/D區域120電性接觸(經由金屬填充160)。金屬化結構200(例如佈線結構或互連結構)可由熟此技藝者所習知的傳統微影、蝕刻及沉積方法來形成。
金屬化結構200可藉由形成光阻劑於絕緣體材料195上來形成，其暴露於能量(光)以形成一圖案(開口)。使用具有選擇性化學反應(例如RIE)的蝕刻製程，以透過光阻劑的開口在絕緣體材料195中形成一或多個溝渠。應理解到，間隙壁材料180將避免蝕刻製程暴露閘極結構110的材料；亦即間隙壁材料180將在蝕刻製程期間提供保護，使得覆蓋材料140及/或側壁間隙壁115及/或閘極材料112在蝕刻製程期間不會受到任何(或很少)侵蝕。因此，針對金屬化結構200所沉積的導電材料不會與閘極結構110的金屬材料(即閘極材料112)接觸。以此方式，避免了短路。
在具體實施例中，可藉由傳統的氧灰化製程或其他已知的去膜劑(stripants)來移除光阻劑，接著藉由傳統沉積製程(例如CVD製程)沉積導電材料。絕緣體材料195的表面上的任何殘留導電材料可透過傳統的化學機械研磨(CMP)製程來移除。
圖9顯示根據本發明其他態樣的一替代結構100’及相應的製造程序。在圖9中，舉例來說，將襯層155凹陷至低於覆蓋材料140，甚至更特別地，凹陷至明顯低於閘極結構110的金屬化特徵(即閘極材料112)的表面，如參考符號170’所示。在具體實施例中，凹陷170’的深度將使得由於夾止現象而將在間隙壁材料180的後續沉積製程中形成氣隙175；亦即，凹陷170’的深度及寬度的組合(即凹陷170’的外觀比)將導致由於夾止現象而在間隙壁材料180的沉積期間於側壁間隙壁115及金屬填充160之間形成氣隙175。以此方式，氣隙介於第一或底部材料(即襯層155)與第二或頂部材料(即 間隙壁材料180)之間。此外，氣隙175低於閘極結構110的閘極材料112的表面，並藉由側壁間隙壁115與閘極材料112分隔。特別地，氣隙175鄰接閘極結構110上的側壁間隙壁115並低於閘極材料112上的覆蓋材料140。在具體實施例中，氣隙175將用以增加結構的寄生電容。結構100’的剩餘部分類似於本文已描述的部分。
現在應理解到，本文所述的製程及所產生的結構將用以在MOL製程期間進一步保護閘極結構的閘極金屬。因此，所產生的結構(例如側壁結構)將避免在源極/汲極區域的互連或其他佈線結構處發生短路。因此，本文描述的製程及結構將提高產率。
上述方法用於積體電路晶片的製造。所產生的積體電路晶片可由製造者以原始晶片的形式(即作為具有多個未封裝晶片的單晶圓)作為裸晶粒分送、或以封裝形式分送。在後者情況中，晶片安裝於單一晶片封裝(例如塑料載體，具有固定至主機板或其他更高階載體的引線)中或安裝於多晶片封裝(如具有表面內連線或埋層內連線的其中一或兩者的陶瓷載體)中。在任何情況下，晶片接著與其他晶片、離散電路元件及/或其他信號處理裝置整合為(a)中間產品(例如主機板)、或(b)終端產品的部分。終端產品可為包含積體電路晶片的任何產品，其範圍從玩具到其他低端應用到具有顯示器、鍵盤或其他輸入裝置、及中央處理器的高級電腦產品。
已出於說明目的提出本發明的各種具體實施例的描述，但其並不意圖為詳盡的或受限於所揭露的具體實施例。在不偏離所述具體實施例的範疇及精神下，許多修改及變化對熟此技藝者而言是明顯的。本文所使用的術語係選擇以最佳地解釋具體實施例的原理、實際應用或針對市場上所發現技術的技術改良、或使其他熟此技藝者能夠理解本文所揭露的具體實施例。
105:基板
110:閘極結構
112:閘極材料
115:側壁間隙壁
120:S/D區域
140:覆蓋材料
160:金屬填充
165:金屬化特徵
180:間隙壁材料
182:間隙壁
195:絕緣體材料
200:金屬化結構

Claims (21)

  1. 一種結構，包含：複數個閘極結構，其各包含一閘極材料、多個源極及/或汲極金屬化特徵，以及直接位於該閘極材料之一頂面上的一漸縮覆蓋層；多個間隙壁，其在該等閘極結構的多個側壁上且由一第一材料及一第二材料所構成，該第一材料直接接觸該等源極及/或汲極金屬化特徵的一全底面；以及多個接觸，其與該等源極及/或汲極金屬化特徵電性接觸且藉由該等間隙壁與該等閘極結構分隔；以及多個側壁間隙壁，直接接觸該閘極材料的兩側壁，其中該第一材料直接接觸該等側壁間隙壁之至少一側壁間隙壁的一側壁，且直接接觸該等源極及/或汲極金屬化特徵的一導電填充材料的兩側壁。
  2. 如申請專利範圍第1項所述的結構，更包含一氣隙，位於該第一材料的一頂面與該第二材料的一底面之間，其中該第一材料的該頂面是位於該閘極材料之該頂面之下，且該等接觸是直接接觸該第二材料之多個側壁，且該等接觸的一底面是直接接觸在該等源極及/或汲極金屬化特徵之內的該導電填充材料的一頂面。
  3. 如申請專利範圍第1項所述的結構，其中該第二材料保護該漸縮覆蓋層在一蝕刻製程期間免受侵蝕。
  4. 如申請專利範圍第3項所述的結構，其中該第二材料為一高k介電材料或一低k介電材料。
  5. 如申請專利範圍第4項所述的結構，其中該第二材料為SiN、Al2O3、及HfO2的其中一者。
  6. 如申請專利範圍第5項所述的結構，其中該第一材料為Ti、TiN、TaN、Ru或Co。
  7. 如申請專利範圍第6項所述的結構，其中該導電填充材料與該等閘極結構的多個源極及汲極區域電性接觸。
  8. 如申請專利範圍第6項所述的結構，其中該等間隙壁是與該等閘極結構上的一側壁結構及該漸縮覆蓋層直接接觸以及與該等源極及/或汲極金屬化特徵直接接觸。
  9. 如申請專利範圍第1項所述的結構，更包含在該第一材料及該第二材料之間的多個氣隙。
  10. 如申請專利範圍第9項所述的結構，其中該等氣隙低於該等閘極結構的該閘極材料的一表面。
  11. 如申請專利範圍第10項所述的結構，其中該等氣隙鄰接在該等閘極結構上的該等側壁間隙壁且低於在該閘極材料上的該漸縮覆蓋層。
  12. 一種結構，包含：複數個閘極結構，其包含多個源極/汲極區域、閘極材料、多個側壁間隙壁及在該閘極材料及該等側壁間隙壁上的一覆蓋材料；複數個源極/汲極接觸，與該等源極/汲極區域電性接觸； 由一頂部材料及一底部材料所構成的一襯層，其沿著該等側壁間隙壁；以及多個接觸，延伸至該等源極/汲極接觸並藉由該襯層與該閘極材料分隔。
  13. 如申請專利範圍第12項所述的結構，其中該底部材料為Ti、TiN、TaN、Ru或Co。
  14. 如申請專利範圍第13項所述的結構，其中該頂部材料為SiN、Al2O3、及HfO2的其中一者。
  15. 如申請專利範圍第14項所述的結構，更包含在該襯層的該頂部材料及該底部材料之間的一氣隙。
  16. 如申請專利範圍第15項所述的結構，其中該氣隙低於該閘極材料的一表面且藉由該等側壁間隙壁與其分隔。
  17. 如申請專利範圍第12項所述的結構，其中該頂部材料由一高k介電質構成。
  18. 如申請專利範圍第12項所述的結構，其中，該襯層延伸於該等源極/汲極接觸之下，使得該底部材料直接接觸該等源極/汲極接觸的一全底面；該等側壁間隙壁直接接觸該閘極材料的兩側壁；以及該底部材料直接接觸該等側壁間隙壁之至少一側壁間隙壁的一側壁，且直接接觸該等源極及/或汲極接觸的一導電填充材料的兩側壁。
  19. 一種製造一半導體結構的方法，包含：形成包含多個側壁間隙壁、閘極材料與多個源極及/或汲極金屬化特徵的複數個閘極結構；形成一漸縮覆蓋層於該等閘極結構之上；在該等閘極結構的多個側壁上形成包含一第一材料及一第二材料的多個間隙壁，該等間隙壁延伸於該等源極及/或汲極金屬化特徵之下，且該第一材料直接接觸且延伸橫跨該等源極及/或汲極金屬化特徵的一底面；以及形成與該等源極及/或汲極金屬化特徵電性接觸並藉由該等間隙壁與凹陷的該等閘極結構分隔的多個接觸；其中該等側壁間隙壁直接接觸該閘極材料的兩側壁；以及該第一材料直接接觸該等側壁間隙壁之至少一側壁間隙壁的一側壁，且直接接觸該等源極及/或汲極金屬化特徵的一導電填充材料的兩側壁。
  20. 如申請專利範圍第19項所述的方法，更包含多個氣隙於該第一材料及該第二材料之間。
  21. 如申請專利範圍第19項所述的方法，其中該第一材料為Ti、TiN、TaN、Ru或Co，且該第二材料為SiN、Al2O3、及HfO2的其中一者。
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