TWI688991B - 接觸結構 - Google Patents

接觸結構 Download PDF

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TWI688991B
TWI688991B TW108104074A TW108104074A TWI688991B TW I688991 B TWI688991 B TW I688991B TW 108104074 A TW108104074 A TW 108104074A TW 108104074 A TW108104074 A TW 108104074A TW I688991 B TWI688991 B TW I688991B
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TW201939583A (zh
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朴燦魯
蔡東辰
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明係關於半導體結構，尤其關於接觸結構及其製造方法。該方法包括：使相鄰閘極結構之間的一隔離區域形成凹陷，並低於源極/汲極金屬化的金屬化超覆層(overburden)；使該金屬化超覆層平坦化至該等相鄰閘極結構之高度；及在該等相鄰閘極結構的側面上形成該源極/汲極金屬化的源極/汲極接點，並延伸至該等結構上方。

Description

接觸結構
本發明係關於半導體結構，尤其關於接觸結構及其製造方法。
中段製程(MOL，middle of line)是決定元件良率的一關鍵因素。該MOL製程包括例如鈷金屬化和源極/汲極接點形成。
然而，隨著技術往小尺寸發展，這對鈷金屬化和源極/漏極接點形成製程帶來了若干挑戰。例如，由於難以控制拋光製程，例如化學機械拋光(CMP，chemical mechanical polishing)，這對鈷金屬化帶來了重大挑戰。尤其是，用於鈷材料的CMP製程選擇性並不高，造成製程控制不良。這種製程控制不良接著導致保護該閘極材料的犧牲披覆材料局部變薄(例如缺乏均勻性)。該製程控制不良也導致該閘極材料連接區(Landing)的犧牲披覆材料穿透。這將暴露該閘極材料，導致與後續形成的源極/汲極接點短路。
在本發明的態樣中，一種方法包括：使相鄰閘極結構之間的一隔離區域形成凹陷，並低於源極/汲極金屬化的金屬化超覆層；使該金屬化超覆層平坦化至該等相鄰閘極結構之高度；及在該等相鄰閘極結構的側面上形成該源極/汲極金屬化的源極/汲極接點，並延伸至該等結構上方。
在本發明的態樣中，一種方法包括：移除閘極結構表面上方及源極/汲極金屬化特徵件的鈷超覆層內的介電材料；在移除該介電材料之後，使該鈷超覆層平坦化至該等閘極結構的一披覆材料；在該披覆材料與該源極/汲極金屬化特徵件上沉積層間介電材料；及在該等閘極結構上方一延伸的側面上，該層間介電材料內形成該源極/汲極金屬化特徵件的源極/汲極接點。
在本發明的態樣中，一種結構包括：複數個閘極結構，其每一者包括一披覆材料；源極與汲極區，其相鄰於該等複數個閘極結構；鈷接點，其介於該等複數個閘極結構之間並延伸至該等源極與汲極區域並與之電接觸；一隔離材料，其介於該等複數個閘極結構的相鄰閘極結構之間；一階梯特徵件，其位於該等相鄰閘極結構的該披覆材料內；介電材料，其位於該階梯特徵件內及該等複數個閘極結構的該披覆材料上方；及源極與汲極接點，其位於該介電材料內並接觸該等鈷接點。
10‧‧‧輸入結構
12‧‧‧基材
14‧‧‧閘極結構
14'‧‧‧相鄰閘極結構
14a‧‧‧側壁空間層
14b‧‧‧高k閘極介電材料
14c‧‧‧閘極材料
14d‧‧‧犧牲披覆材料
16‧‧‧源極/汲極區域
18‧‧‧襯墊層
20‧‧‧隔離區域
20'‧‧‧層間介電層
20a‧‧‧淺溝渠隔離區域
20b‧‧‧襯墊層
22‧‧‧金屬接點材料
22'‧‧‧超覆層
24‧‧‧凹槽
24'‧‧‧階梯特徵件
26‧‧‧源極與汲極接點
後面將利用本發明示範具體實施例的非限制範例、連同參考所示多個圖式，在實施方式中詳細描述本發明。
圖1顯示根據本發明態樣的其他特徵件之間使用閘極結構的一新型結構、及個別製程。
圖2顯示根據本發明態樣的其他特徵之間的閘極結構之間的一凹槽、及個別製程。
圖3顯示根據本發明態樣的其他特徵之間的平坦化閘極結構和接點材料、及個別製程。
圖4顯示根據本發明態樣的其他特徵之間的該等閘極結構上的一層間介電材料、及個別製程。
圖5顯示根據本發明態樣的其他特徵之間的源極與汲極接 點、及個別製程。
本發明係關於半導體結構，尤其關於接觸結構及其製造方法。尤其是，本發明提供一種選擇性移除Co的層間介電材料並且後續通過化學機械拋光(CMP)移除該Co超覆層的方法。有利地，去除Co超覆層的方法將導致最小的披覆層腐蝕。
本發明的該等接觸結構可用許多不同工具以許多方式來製造。一般來說，該等方法與工具用來形成毫米與奈米等級尺寸的結構。用來製造本發明接觸結構的該等方法(即技術)採用積體電路(IC)技術。例如，這些結構建立在晶圓上，並且通過在晶圓頂部上以光微影蝕刻製程所圖案化的材料薄膜來實現。尤其是，該等接觸結構的製造使用三種基本步驟：(i)將材料薄膜沈積在基材上，(ii)利用光微影蝕刻成像將一圖案化光罩應用於該等薄膜頂端上，及(iii)選擇性蝕刻該光罩的該等薄膜。
圖1顯示根據本發明態樣的其他特徵之間使用閘極結構的一新型結構。尤其是，新型結構10包括形成於一底下基材12上的複數個閘極結構14。在具體實施例中，基材12可由任何合適的半導體材料形成，包含但不受限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP、及其他III/V或II/VI族複合半導體。基材12可為由傳統側壁成像技術(SIT，sidewall imaging techniques)所形成平片式結構或鰭式結構的呈現，如此在了解本發明時不需進一步解釋。另外，基材12可為用於平片式或鰭式FET技術的塊狀材料之呈現，例如Si或絕緣體上半導體(SOI，semiconductor on insulator)技術。此外，複數個閘極結構14可由傳統置換閘極製程所形成，如此在了解本發明時不需進一步解釋。
請即重新參考圖1，複數個閘極結構14可包括由例如SiN材料構成的側壁空間層14a。閘極結構14進一步包括側壁空間層14a及溝 渠(由移除偽閘極結構所形成)底部上的一高k閘極介電材料14b。在具體實施例中，高k閘極介電材料14b可為例如鉿基介電質。在進一步具體實施例中，這種高k介電質的範例包括但不受限於：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3、及包括其多層的組合。
一閘極材料(例如摻雜矽)沉積在高k閘極介電材料14b上。此外，閘極結構14可用一犧牲披覆材料14d覆蓋。在具體實施例中，犧牲披覆材料14d可為SiN材料，在後續源極/汲極接點製程期間沉積以保護底下閘極材料14c。源極/汲極區域16形成於閘極結構14的側面上。在具體實施例中，源極/汲極區域16可為凸起的磊晶材料，例如摻雜有雜質的半導體材料，像是Si或SiGe。
源極/汲極區域16可經歷一矽化製程來形成接點。熟習該項技藝者應該了解，該矽化製程始於在完全成形並且圖案化的半導體元件上(例如摻雜或離子植入的源極與汲極區域16)沉積一薄過渡金屬層，例如鎳、鈷或鈦。在沉積該材料之後，將該結構加熱，允許該過渡金屬與該半導體裝置的主動區域(例如源極、汲極、閘極接點區域)內暴露的矽(或如本說明書所描述的其他半導體材料)起反應，以形成一低阻抗過渡金屬矽化物。在反應之後，通過化學蝕刻除去任何殘留的過渡金屬，在該裝置的主動區域中留下矽化物接點。熟習該項技藝者應該了解，當一閘極結構由金屬材料構成時，該元件上將不需要矽化物接點。
圖1進一步顯示形成於閘極結構14和源極/汲極區域16上的一襯墊層18。在具體實施例中，襯墊層18為一可通過電漿增強氣相沉積(PEVD，Plasma Enhanced Vapor Deposition)製程所沉積的TiN襯墊。襯墊層18將沉積在側壁空間層14a、犧牲披覆材料14d和源極與汲極區域16上。複數個閘極結構14之間的殘留空間可填入金屬接點材料22。例如，金屬接點材料22可為通過傳統沉積製程所沉積的鈷(Co)，例如化學氣相沉積(CVD)製程。在具體實施例中，如圖1所示，該沉積製程將導致金屬接點材料22 的超覆層22'，例如閘極結構14上的金屬材料。
一隔離區域(層間介電材料)20形成於兩相鄰閘極結構14'之間(延伸入閘極結構14上方的超覆層22')。在具體實施例中，相鄰閘極結構14'可為偽閘極結構。隔離區域20可包括例如在置換閘極結構14、14'之前形成的一淺溝渠隔離區域20a。隔離區域20可由含例如SiN所構成的一襯墊層20b之氧化物材料所構成。
在具體實施例中，隔離區域20可通過熟習該項技藝者熟知的傳統微影、蝕刻與沉積方法來形成。例如，金屬接點材料22上形成的一光阻暴露在能量(光線)下形成一圖案(開口)。使用例如反應性離子蝕刻(RIE，reactive ion etching)之選擇性化學的蝕刻製程將用於通過該光阻的該開口，在金屬接點材料22內形成一或多個溝渠。然後用傳統氧灰化製程或其他已知剝離劑移除該光阻。緊接在該光阻移除之後，用例如化學氣相沉積(CVD)製程的任何傳統沉積製程沉積襯墊層20b和絕緣體材料。利用傳統化學機械拋光(CMP，chemical mechanical polishing)製程可移除金屬接點材料22表面上的任何殘留材料。
在圖2中，通過選擇性蝕刻製程，移除(凹陷)一部分隔離區域20。更具體地，選擇性蝕刻製程可為低或零偏壓CF4、CHF3、CH2F2、CH3F電漿或具有氣體混合物的電漿，其選擇性蝕刻或凹陷隔離區域20的材料，例如SiO2和SiN材料，以形成凹槽24。在具體實施例中，該蝕刻製程也將移除一部分犧牲披覆材料14d，這有助於產生凹槽24。在具體實施例中，凹槽24低於犧牲披覆材料14d的表面，例如約低於5nm至約30nm的範圍。然而，應注意，該選擇性蝕刻製程將不暴露任何底下的閘極材料14c。
如圖3的進一步顯示，金屬接點材料22與襯墊層18經過拋光製程，止於犧牲披覆材料14d。在更具體的具體實施例中，金屬接點材料22與襯墊層18進行一選擇性CMP製程，其不會侵蝕犧牲披覆材料14d。 如此，犧牲披覆材料14d將留在閘極材料14c上面，避免材料暴露並導致在後續源極/汲極接點製程中短路。
在圖4中，層間介電層20'沉積在犧牲披覆材料14d上以及凹槽24的殘留部分內。在具體實施例中，層間介電層20'為通過傳統沉積方法沉積的氧化物材料，例如SiO2。例如，通過一CVD製程來沉積層間介電層20'。如圖4所示，該凹槽內的層間介電層20'形成具有相鄰閘極結構14'的階梯特徵件24'。
圖5顯示層間介電層20'中的源極與汲極接點26，其延伸到金屬接點材料22(例如，Co)並與之接觸。在具體實施例中，源極與汲極接點26可為任何適當的材料，包括例如鎢或鋁，內襯有TiN、Ta、TaN等。源極與汲極接點26可通過傳統微影、蝕刻、沉積和平坦化製程來形成。例如，在層間介電層20'上形成的一光阻暴露於能量(光)之下，以形成圖案(開口)，在源極/汲極區域16上方對準並暴露金屬接點材料22。使用選擇性化學蝕刻製程(例如RIE)將用來通過該光阻的該開口，在層間介電層20'內形成一或多個溝渠。然後用傳統氧灰化製程或其他已知剝離劑移除該光阻。緊接在該光阻移除之後，用任何傳統沉積製程(例如CVD製程)沉積該導電材料。利用傳統化學機械拋光(CMP，chemical mechanical polishing)製程可移除層間介電層20'表面上的任何殘留材料。
上述該(等)方法用於積體電路晶片製造。結果積體電路晶片可由業者以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、如同一裸晶粒或已封裝形式來流通。在後者案例中，晶片固定在單晶片封裝內(像是塑膠載體，具有導線黏貼至主機板或其他更高層載體)或固定在多晶片封裝內(像是具有一或兩表面具有表面互連或掩埋式互連的陶瓷載體)。然後在任何案例中，晶片與其他晶片、離散電路元件及/或其他信號處理裝置整合成為(a)中間產品，像是主機板，或(b)末端產品。末端產品可為包括積體電路晶片的任何產品，範圍從玩具與其他低階應用到具有顯示器、鍵盤或其 它輸入裝置及中央處理器的進階電腦產品。
本發明的各種具體實施例的描述已為了說明而呈現，但沒有意圖將本發明受限在所揭露的形式。在不悖離所描述具體實施例之範疇與精神的前提下，熟習該項技藝者將瞭解許多修正例及變化例。本說明書內使用的術語係為了能最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進，或讓熟習該項技藝者理解本說明書所揭示的具體實施例。
12‧‧‧基材
14‧‧‧閘極結構
14a‧‧‧側壁空間層
14b‧‧‧高k閘極介電材料
14c‧‧‧閘極材料
14d‧‧‧犧牲披覆材料
16‧‧‧源極/汲極區域
18‧‧‧襯墊層
20'‧‧‧層間介電層
20a‧‧‧淺溝渠隔離區域
20b‧‧‧襯墊層
22‧‧‧金屬接點材料
26‧‧‧源極與汲極接點

Claims (25)

  1. 一種半導體結構的製造方法，包括：使相鄰閘極結構之間的一隔離區域形成凹陷，並低於源極/汲極金屬化的金屬化超覆層；使該金屬化超覆層平坦化至該等相鄰閘極結構之高度；及在該等相鄰閘極結構的側面上形成該源極/汲極金屬化的源極/汲極接點，並延伸至該等相鄰閘極結構上方。
  2. 如申請專利範圍第1項所述之方法，其中凹陷該隔離區域為一選擇性蝕刻製程，其並不會侵蝕該源極/汲極金屬化的該金屬化超覆層。
  3. 如申請專利範圍第2項所述之方法，其中該金屬化超覆層為鈷。
  4. 如申請專利範圍第3項所述之方法，其中該選擇性蝕刻為一低或零偏壓CF4、CHF3、CH2F2、CH3F電漿或具有選擇性蝕刻該鈷的該隔離區域之氣體混合物的電漿。
  5. 如申請專利範圍第2項所述之方法，其中該凹陷部分移除該相鄰閘極結構的一披覆材料。
  6. 如申請專利範圍第1項所述之方法，其中該平坦化為鈷超覆層的一化學機械拋光(CMP)，其止於該相鄰閘極結構與其他閘極結構上的一披覆材料上。
  7. 如申請專利範圍第6項所述之方法，其中該CMP選擇用於該披覆材料。
  8. 如申請專利範圍第7項所述之方法，其中該披覆材料為保護底下閘極材料的一氮化物材料。
  9. 如申請專利範圍第7項所述之方法，其中該形成該等源極/汲極接點包括：將介電材料沉積於該凹槽內及該相鄰閘極結構和該其他閘極結構上；在該介電材料內形成開口，暴露該相鄰閘極結構與該其他閘極結構之間的該源極/汲極金屬化；及將金屬材料沉積於該開口內，接觸該源極/汲極金屬化。
  10. 一種半導體結構的製造方法，包括：移除閘極結構表面上方及源極/汲極金屬化特徵件的鈷超覆層內的介電材料；在移除該介電材料之後，使該鈷超覆層平坦化至該等閘極結構的一披覆材料；在該披覆材料與該源極/汲極金屬化特徵件上沉積層間介電材料；及在該等閘極結構上方一延伸的側面上，在該層間介電材料內形成該源極/汲極金屬化的源極/汲極接點。
  11. 如申請專利範圍第10項所述之方法，其中該移除介電材料為一選擇性蝕刻製程。
  12. 如申請專利範圍第11項所述之方法，其中該選擇性蝕刻製程為一低或零偏壓CF4、CHF3、CH2F2、CH3F電漿或具有氣體混合物的電漿，其 選擇性蝕刻該介電材料至低於該等閘極結構的該披覆材料之一表面之下。
  13. 如申請專利範圍第10項所述之方法，其中該平坦化為該鈷超覆層的一化學機械拋光(CMP)，其止於該等閘極結構的該披覆材料上。
  14. 如申請專利範圍第13項所述之方法，其中該CMP選擇用於該披覆材料。
  15. 如申請專利範圍第13項所述之方法，其中該披覆材料為保護底下閘極材料的一氮化物材料。
  16. 如申請專利範圍第10項所述之方法，其中該層間介電材料的沉積為沉積於該披覆材料內形成的一階梯特徵件內。
  17. 如申請專利範圍第16項所述之方法，其中在該介電材料的該移除期間，通過凹陷相鄰閘極結構之間的一部分披覆材料以形成該階梯特徵件。
  18. 如申請專利範圍第17項所述之方法，其中該凹陷為低於該披覆材料頂端約5nm至約30nm。
  19. 如申請專利範圍第10項所述之方法，其中該介電材料為一選擇性移除至鈷材料的氧化物材料。
  20. 一種半導體結構，包括：複數個閘極結構，其每一者包括一披覆材料；源極與汲極，其相鄰於該等複數個閘極結構；鈷接點，其位於該等複數個閘極結構之間並延伸至該等源極與汲極區域並與之電接觸；一隔離材料，其位於該等複數個閘極結構的相鄰閘極結構之間；一階梯特徵件，其位於該等相鄰閘極結構的該披覆材料內；介電材料，其位於該階梯特徵件內以及該等複數個閘極結構的該披覆材料上方；及源極與汲極接點，其位於該介電材料內並接觸該等鈷接點。
  21. 如申請專利範圍第20項所述之結構，其中該隔離材料向上延伸至該等複數個閘極結構的該披覆材料上方。
  22. 如申請專利範圍第20項所述之結構，其中該隔離材料向下延伸至一基板內的一淺溝槽隔離區。
  23. 如申請專利範圍第20項所述之結構，其中該隔離材料係由具有一內襯的氧化物所構成。
  24. 如申請專利範圍第20項所述之結構，其中該階梯特徵件是透過將該隔離材料選擇性蝕刻或凹槽化所形成。
  25. 如申請專利範圍第20項所述之結構，其中在該階梯特徵件內的該介電材料直接接觸該隔離材料。
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