CN110246804B - 接触结构 - Google Patents

接触结构 Download PDF

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CN110246804B
CN110246804B CN201910112883.8A CN201910112883A CN110246804B CN 110246804 B CN110246804 B CN 110246804B CN 201910112883 A CN201910112883 A CN 201910112883A CN 110246804 B CN110246804 B CN 110246804B
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source
gate structure
capping
metallization
drain
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CN110246804A (zh
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朴灿鲁
蔡东辰
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Lattice Core Usa Inc
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Abstract

本发明涉及接触结构。本公开涉及半导体结构，并且更特别地，涉及接触结构以及制造方法。所述方法包括：使位于邻近栅极结构之间并且位于源极/漏极金属化的金属化覆盖层下方的隔离区凹陷；将所述金属化覆盖层平面化至所述邻近栅极结构的水平；以及形成在所述邻近栅极结构的侧面上并且在所述邻近栅极结构上方延伸的到所述源极/漏极金属化的源极/漏极接触。

Description

接触结构
技术领域
本公开涉及半导体结构，并且更特别地，涉及接触结构以及制造方法。
背景技术
中段制程(MOL)工艺是器件产量的一个关键的决定因素。MOL工艺包括例如钴金属化和源极/漏极接触形成。
然而，随着技术向下缩小，钴金属化和源极/漏极接触形成工艺提出了若干挑战。例如，由于难以控制抛光工艺，例如，化学机械抛光(CMP)，钴金属化提出了重大挑战。具体地，用于钴材料的CMP工艺不具有高选择性，这导致不良的工艺控制。这种不良的工艺控制进而导致保护栅极材料的牺牲帽盖材料的局部变薄(例如，缺乏均匀性)。不良的工艺控制还可导致牺牲帽盖材料的穿通，落在栅极材料上。这将暴露栅极材料，导致随后形成的源极/漏极接触短路。
发明内容
在本公开的方面，一种方法包括：使位于邻近栅极结构之间并且位于源极/漏极金属化的金属化覆盖层下方的隔离区凹陷；将所述金属化覆盖层平面化至所述邻近栅极结构的水平；以及形成在所述邻近栅极结构的侧面上并且在所述邻近栅极结构上方延伸的到所述源极/漏极金属化的源极/漏极接触。
在本公开的方面，一种方法包括：去除位于栅极结构的表面上方和位于源极/漏极金属化特征的钴覆盖层内的电介质材料；在所述去除所述电介质材料之后，将所述钴覆盖层平面化至所述栅极结构的帽盖材料；在所述帽盖材料和所述源极/漏极金属化特征上沉积层间电介质材料；以及在所述层间电介质材料内并在所述栅极结构的侧面上形成在所述栅极结构上方延伸的到所述源极/漏极金属化特征的源极/漏极接触。
在本公开的方面，一种结构包括：多个栅极结构，所述多个栅极结构中的每一个包括帽盖材料；与所述多个栅极结构邻近的源极和漏极区；位于所述多个栅极结构之间以及延伸到所述源极和漏极区并且与所述源极和漏极区电接触的钴接触；位于所述多个栅极结构的邻近栅极结构之间的隔离材料；位于所述邻近栅极结构的所述帽盖材料中的台阶特征；位于所述台阶特征中且位于所述多个栅极结构的所述帽盖材料上方的电介质材料；以及位于所述电介质材料中且接触钴接触的源极和漏极接触。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本公开的方面的除了其他特征之外的具有栅极结构的输入结构以及相应的制造工艺。
图2示出了根据本公开的方面的除了其他特征之外的栅极结构之间的凹部以及相应的制造工艺。
图3示出了根据本公开的方面的除了其他特征之外的平面化的栅极结构和接触材料以及相应的制造工艺。
图4示出了根据本公开的方面的除了其他特征之外的位于栅极结构之上的层间电介质材料以及相应的制造工艺。
图5示出了根据本公开的方面的除了其他特征之外的源极和漏极接触以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更特别地，涉及接触结构以及制造方法。更具体地，本公开提供了一种对Co具有选择性地去除层间电介质材料并随后通过化学机械抛光(CMP)去除Co覆盖层(overburden)的方法。有利地，去除Co覆盖层的方法将导致最小的帽盖侵蚀。
本公开的接触可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的接触结构的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，接触结构的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1示出了根据本公开的方面的除了其他特征之外的具有栅极结构的输入结构。更具体地，输入结构10包括形成在下方的衬底12上的多个栅极结构14。在实施例中，衬底12可以是任何合适的半导体材料，包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和其他III/V或II/VI化合物半导体。衬底12可以代表平面结构或由常规侧壁成像技术(SIT)形成的鳍结构，使得在此不需要进一步解释来理解本公开。此外，衬底12可以代表用于平面或finFET技术的例如Si的体材料或绝缘体上半导体(SOI)技术。另外，多个栅极结构14可以通过常规的替代栅极工艺形成，使得在此不需要进一步说明以理解本公开。
仍然参考图1，多个栅极结构14可以包括由例如SiN材料构成的侧壁隔离物14a。栅极结构14还包括位于侧壁隔离物14a上和位于沟槽(通过去除虚设栅极结构形成)的底部上的高k栅极电介质材料14b。在实施例中，作为示例，高k电介质栅极材料14b可以是基于铪的电介质。在另外的实施例中，这种高k电介质的示例包括但不限于：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其的多层的组合。
例如掺杂的多晶硅的栅极材料14c沉积在高k电介质栅极材料14b之上。另外，栅极结构14可以被牺牲帽盖材料14d覆盖。在实施例中，牺牲帽盖材料14d可以是SiN材料，其被沉积以在随后的源极/漏极接触制造工艺期间保护下方的栅极材料14c。源极/漏极区16形成在栅极结构14的侧面上。在实施例中，源极/漏极区16可以是升高的外延材料，例如掺杂有杂质的半导体材料，诸如Si或SiGe。
源极/漏极区16可以经历用于接触形成的硅化工艺。如本领域技术人员应理解的，硅化物工艺开始于在完全形成和图案化的半导体器件(例如，掺杂或离子注入的源极和漏极区16)之上沉积薄的过渡金属层(例如，镍、钴或钛)。在沉积材料之后，加热该结构，允许过渡金属与半导体器件的有源区(例如，源极、漏极、栅极接触区)中暴露的硅(或如本文所述的其他半导体材料)反应，形成低电阻过渡金属硅化物。在反应之后，通过化学蚀刻去除任何剩余的过渡金属，在器件的有源区中留下硅化物接触。本领域技术人员应该理解，当栅极结构由金属材料构成时，器件上不需要硅化物接触。
图1还示出了在栅极结构14和源极/漏极区16上形成的衬里18。在实施例中，衬里18是TiN衬里，其可以通过等离子体增强气相沉积(PEVD)工艺沉积。衬里18将被沉积在侧壁隔离物14a、牺牲帽盖材料14d以及源极和漏极区16之上。多个栅极结构14之间的剩余空间可以用金属接触材料22填充。例如，金属接触材料22可以是钴(Co)，其通过例如化学气相沉积(CVD)工艺的常规沉积工艺沉积。在实施例中，如图1所示，沉积工艺将导致金属接触材料22的覆盖层22’，例如栅极结构14上方的金属材料。
隔离区域(层间电介质材料)20形成在两个邻近的栅极结构14’之间(延伸到栅极结构14上方的覆盖层22’中)。在实施例中，邻近栅极结构14’可以是虚设栅极结构。隔离区20可以包括例如在替代栅极结构14、14’之前形成的浅沟槽隔离区20a。隔离区20可以由氧化物材料构成，其中衬里20b例如由SiN构成。
在实施例中，隔离区20可以通过本领域技术人员已知的常规光刻、蚀刻和沉积方法形成。例如，在金属接触材料22之上形成的抗蚀剂暴露于能量(光)以形成图案(开口)。例如反应离子蚀刻(RIE)的具有选择性化学(chemistry)的蚀刻工艺将用于通过抗蚀剂的开口在金属接触材料22中形成一个或多个沟槽。然后，抗蚀剂可以通过常规的氧灰化工艺或其他已知的剥离剂被去除。在去除抗蚀剂之后，衬里20b和绝缘体材料可以通过例如化学气相沉积(CVD)工艺的任何常规的沉积工艺沉积。金属接触材料22表面上的任何残余材料可以通过常规化学机械抛光(CMP)工艺去除。
在图2中，隔离区20的部分通过选择性蚀刻工艺被去除(被凹陷)。更具体地，选择性蚀刻工艺可以是低或零偏置的CF4、CHF3、CH2F2、CH3F等离子体或具有上述气体的混合物的等离子体，其选择性地蚀刻隔离区20的材料或使隔离区20的材料凹陷，以形成凹部24，该隔离区20的材料例如SiO2和SiN材料。在实施例中，蚀刻工艺还将去除牺牲帽盖材料14d的部分，这有助于凹部24。在实施例中，凹部24位于牺牲帽盖材料14d的表面下方，例如，大约在5nm至约30nm的范围内。然而，应该注意，选择性蚀刻工艺将不会暴露下方栅极材料14c的任何部分。
如图3中进一步所示，金属接触材料22和衬里18经历抛光工艺，其在牺牲帽盖材料14d上停止。在更具体的实施例中，金属接触材料22和衬里18经历选择性CMP工艺，其不会侵蚀牺牲帽盖材料14d。以这种方式，牺牲帽盖材料14d将保留在栅极材料14c之上，防止其被暴露并防止其在随后的源极/漏极收缩(contract)制造工艺中导致短路。
在图4中，层间电介质层20’沉积在牺牲帽盖材料14d之上和凹部24的剩余部分之内。在实施例中，层间电介质层20’是通过常规沉积方法沉积例如SiO2的氧化物材料。例如，层间电介质层20’可以通过CVD工艺沉积。如图4所示，凹部内的层间电介质层20’形成与邻近栅极结构14’的台阶特征24’。
图5示出了层间电介质层20’中的源极和漏极接触26，其延伸到金属接触材料22(例如，Co)并与之接触。在实施例中，源极和漏极接触26可以是被加衬有TiN、Ta、TaN等的任何适当的材料，该材料包括例如钨或铝。源极和漏极接触26可以通过常规的光刻、蚀刻、沉积和平坦化工艺形成。例如，在层间电介质层20’上形成的抗蚀剂暴露于能量(光)以形成图案(开口)，该图案(开口)与源极/漏极区16之上的金属接触材料22对准并暴露该金属接触材料22。例如RIE的具有选择性化学的蚀刻工艺将用于通过抗蚀剂的开口在层间电介质层20’中形成一个或多个沟槽。然后，抗蚀剂可以通过常规的氧灰化工艺或其他已知的剥离剂去除。在去除抗蚀剂之后，可以通过例如CVD工艺的任何常规的沉积工艺沉积导电材料。层间电介质层20’表面上的任何残余材料可通过常规化学机械抛光(CMP)工艺去除。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种用于制造半导体结构的方法，包括：
使位于邻近栅极结构之间的隔离区域、所述邻近栅极结构的边缘上的帽盖材料部分地凹陷以位于源极/漏极金属化的金属化覆盖层下方；
将所述金属化覆盖层平面化至所述邻近栅极结构的水平，同时使得所述帽盖材料和所述邻近栅极结构之间的所述隔离区域的经凹陷的部分保持位于所述源极/漏极金属化的所述金属化覆盖层下方；以及
形成在所述邻近栅极结构的侧面上并且在所述邻近栅极结构上方延伸的到所述源极/漏极金属化的源极/漏极接触。
2.根据权利要求1所述的方法，其中所述隔离区的所述凹陷是选择性蚀刻工艺，其不侵蚀所述源极/漏极金属化的所述金属化覆盖层。
3.根据权利要求2所述的方法，其中所述金属化覆盖层是钴。
4.根据权利要求3所述的方法，其中所述选择性蚀刻是选择性地将所述隔离区蚀刻到所述钴的低或零偏置CF4、CHF3、CH2F2、CH3F等离子体或具有上述气体的混合物的等离子体。
5.根据权利要求2所述的方法，其中所述凹陷部分地去除所述邻近栅极结构的帽盖材料。
6.根据权利要求1所述的方法，其中所述平面化是所述金属化覆盖层的化学机械抛光CMP，其在所述邻近栅极结构和其他栅极结构上的所述帽盖材料上停止，其中所述金属化覆盖层是钴。
7.根据权利要求6所述的方法，其中所述CMP对所述帽盖材料是选择性的。
8.根据权利要求7所述的方法，其中所述帽盖材料是保护下方的栅极材料的氮化物材料。
9.根据权利要求7所述的方法，其中所述源极/漏极接触的所述形成包括：
在凹部中并且在所述邻近栅极结构和所述其他栅极结构上方沉积电介质材料；
在所述电介质材料中形成开口，以暴露位于所述邻近栅极结构和所述其他栅极结构之间的所述源极/漏极金属化；以及
在所述开口内沉积接触所述源极/漏极金属化的金属材料。
10.一种用于制造半导体结构的方法，包括：
通过以下步骤在电介质材料和栅极结构的帽盖材料中形成凹部：
去除位于所述栅极结构的表面上方和位于源极/漏极金属化特征的钴覆盖层内的所述电介质材料；
去除位于所述栅极结构的邻近栅极结构上方和之间的衬里材料；以及
部分去除所述栅极结构的所述邻近栅极结构的所述帽盖材料的边缘；
在所述去除所述电介质材料、所述衬里材料和所述帽盖材料的所述边缘之后，将所述钴覆盖层平面化至所述栅极结构的未被去除的所述帽盖材料；
在所述帽盖材料和所述源极/漏极金属化特征上沉积层间电介质材料；以及
在所述层间电介质材料内并在所述栅极结构的侧面上形成在所述栅极结构上方延伸的到所述源极/漏极金属化特征的源极/漏极接触。
11.根据权利要求10所述的方法，其中所述电介质材料的所述去除是选择性蚀刻工艺。
12.根据权利要求11所述的方法，其中所述选择性蚀刻工艺是选择性地将所述电介质材料蚀刻到所述栅极结构的所述帽盖材料的表面下方的低或零偏置CF4、CHF3、CH2F2、CH3F等离子体或具有上述气体的混合物的等离子体。
13.根据权利要求10所述的方法，其中所述平面化是所述钴覆盖层的化学机械抛光CMP，其在所述栅极结构的所述帽盖材料上停止。
14.根据权利要求13所述的方法，其中所述CMP对所述帽盖材料是选择性的。
15.根据权利要求13所述的方法，其中所述帽盖材料是保护下方的栅极材料的氮化物材料。
16.根据权利要求10所述的方法，其中所述层间电介质材料的所述沉积是在所述帽盖材料中形成的台阶特征内的沉积。
17.根据权利要求16所述的方法，其中所述台阶特征是通过在所述电介质材料的所述去除期间使所述邻近栅极结构之间的所述帽盖材料的部分凹陷来形成。
18.根据权利要求17所述的方法，其中所述凹陷在所述帽盖材料的顶部下方5nm至30nm。
19.根据权利要求10所述的方法，其中所述电介质材料是氧化物材料，其被选择性地去除到钴材料。
20.一种半导体结构，包括：
多个栅极结构，所述多个栅极结构中的每一个包括帽盖材料；
与所述多个栅极结构邻近的源极和漏极区；
位于所述多个栅极结构之间以及延伸到所述源极和漏极区并且与所述源极和漏极区电接触的钴接触；
位于所述多个栅极结构的邻近栅极结构之间的隔离材料；
位于所述邻近栅极结构的所述帽盖材料中的台阶特征，其中，所述台阶特征的底表面和与所述台阶特征邻近的所述隔离材料的顶表面共面，其中，所述台阶特征通过以下方式形成：在将所述钴接触平面化至所述邻近栅极结构的水平之前使位于所述邻近栅极结构之间的所述隔离材料、所述邻近栅极结构的边缘上的所述帽盖材料部分地凹陷以位于所述钴接触下方；
位于所述台阶特征中且位于所述多个栅极结构的所述帽盖材料上方的电介质材料；以及
位于所述电介质材料中且接触所述钴接触的源极和漏极接触。
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