CN102148236A - 半导体元件及其制造方法 - Google Patents
半导体元件及其制造方法 Download PDFInfo
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- CN102148236A CN102148236A CN2010102214191A CN201010221419A CN102148236A CN 102148236 A CN102148236 A CN 102148236A CN 2010102214191 A CN2010102214191 A CN 2010102214191A CN 201010221419 A CN201010221419 A CN 201010221419A CN 102148236 A CN102148236 A CN 102148236A
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
本发明一实施例提供一种半导体元件及其制作方法,该半导体元件包括:一半导体基底;一栅极堆叠,位于该半导体基底之上,该栅极堆叠包括一栅极介电层及一栅极电极;一间隙壁,形成于该栅极堆叠的侧壁上,其中该间隙壁的一顶表面高于该栅极堆叠的一顶表面;以及一保护层,位于该栅极堆叠之上,且至少部分填充由位于该栅极堆叠的该顶表面上的该间隙壁所围绕的一空间。本发明增加所生产的半导体元件的整体合格率,且半导体元件具有更高的可靠度。
Description
技术领域
本发明涉及具有升高结构(elevated structure)的半导体元件及其制作方法。
背景技术
随着半导体元件的集成程度(degree of integration)的增加,集成电路中的尺寸与线宽持续地缩小化。因此,半导体元件的制造变得更为复杂与严苛。例如,当进行光刻工艺以图案化晶片上的电路时,对不准(misalignment)的机率会因尺寸的缩小而增加,因而可能形成出不想要的图案。
图1显示半导体元件100。半导体元件100包括基底110、多晶硅栅极120、间隙壁125、硅化层121、及介电层150。当间隙壁125的高度等于或低于栅极120时,硅化层121常具有蘑菇形状(mushroom shape),并可突出于栅极120的边界,如图1所绘。因此,由于在源极/漏极区115上形成接触开口的光刻工艺期间发生对不准,源极/漏极区115上的接触金属160(例如是钨或铜)可能于位置129通过硅化物层121而与栅极120形成短路。栅极120与源极/漏极区接点(例如,接触金属160)之间的这种短路增加缺陷单元的数量。另外,这样的短路增加制作总成本,因需重工以修复这些具有缺陷的单元,并消耗额外的材料,例如光致抗蚀剂与化学溶剂。短路问题因硅化层121(其用以增加栅极120的导电度)而更为严重,因硅化层121倾向向外突出至间隙壁125的顶部,并当光刻对不准(photolithographic misalignment)发生时,与接触金属160形成不想要的短路。栅极120也可为金属栅极,在此情形下,金属栅极120上不形成有硅化层。然而,若发生光刻对不准,也很可能发生短路。
发明内容
为了解决现有技术的问题,本发明一实施例提供一种半导体元件,包括:一半导体基底;一栅极堆叠,位于该半导体基底之上,该栅极堆叠包括一栅极介电层及一栅极电极;一间隙壁,形成于该栅极堆叠的侧壁上,其中该间隙壁的一顶表面高于该栅极堆叠的一顶表面;以及一保护层,位于该栅极堆叠之上,且至少部分填充由位于该栅极堆叠的该顶表面上的该间隙壁所围绕的一空间。
本发明一实施例提供一种半导体元件的制造方法,包括:于一半导体基底的一顶表面中的一有源区上形成一栅极堆叠;于该栅极堆叠的侧壁上形成一间隙壁;移除该栅极堆叠的一顶部部分以使该间隙壁的一顶表面高于一最终栅极堆叠的一顶表面,其中该最终栅极堆叠为移除该顶部部分后的该栅极堆叠;以及于该最终栅极堆叠上形成一保护层以至少部分填充由位于该最终栅极堆叠的该顶表面上的该间隙壁所围绕的一空间。
本发明一实施例提供一种半导体元件,包括:一半导体基底,该半导体基底的一顶表面上具有至少一有源区;一栅极堆叠,形成于该有源区上,该有源区还包括紧邻该栅极堆叠的源极/漏极区;一间隙壁,形成于该栅极堆叠的侧壁上;一升高接触结构,自该源极/漏极区向上延伸,该升高接触结构具有一顶表面,高于该栅极堆叠的一顶表面;以及一保护层,位于该栅极堆叠及该间隙壁之上,且至少部分填充形成于该升高接触结构与该栅极堆叠的该顶表面之间的一空间。
本发明一实施例提供一种半导体元件的制造方法,该半导体元件形成自一栅极置换结构,该栅极置换结构包括位于一半导体基底的一顶表面上的一有源区上的一栅极堆叠、位于该栅极堆叠的侧壁上的一间隙壁、以及位于该基底上且围绕该栅极堆叠与该间隙壁的一介电层,该有源区还包括紧邻该栅极堆叠的源极/漏极区,该方法包括:于该半导体基底的该顶表面上的该源极/漏极区上的该介电层中形成一接触开口;于该接触开口中填充一导电材料;于填充于该接触开口中的该导电材料上形成一导电升高结构,使该导电升高结构的一顶表面高于该栅极堆叠的一顶表面;以及于该栅极堆叠及该间隙壁上形成一保护层以至少部分填充形成于该导电升高结构的该顶表面与该栅极堆叠的该顶表面之间的一空间。
在本发明中,即使是当对不准发生时,短路问题仍可避免,因而增加所生产的半导体元件的整体合格率。另外,根据本发明而制造的半导体元件具有更高的可靠度,这是因为具有缺陷的单元的形成已显著地减少。
附图说明
图1显示一半导体元件的剖面图。
图2A-图2E显示根据本发明一实施例的半导体元件的工艺剖面图。
图3A-图3D显示根据本发明另一实施例的半导体元件的工艺剖面图。
图4A-图4E显示根据本发明又一实施例的半导体元件的工艺剖面图。
图5显示图2A-图2E中所示的工艺的方法流程图。
图6显示图4A-图4E中所示的工艺的方法流程图。
其中,附图标记说明如下:
100~半导体元件;
110~基底;
115~源极/漏极区;
120~栅极;
121~硅化层;
125~间隙壁;
129~位置;
150~介电层;
160~接触金属;
200~半导体元件;
210~基底;
220、220a、320~栅极堆叠;
223~栅极介电层;
225、225a~栅极电极;
230、230a~间隙壁;
240~保护层;
250、450~介电层;
260~接触洞;
267a、267b~底部部分;
287~有源区;
293~硅化区;
296~虚置层;
297、397a、397b~衬层;
298、299、410~源极/漏极区;
327~虚置栅极;
329~硬掩模;
400~半导体元件;
455~接触开口;
460~接触金属;
470~升高结构;
S510、S520、S530、S540、S610、S620、S630、S640、S650、S660~步骤。
具体实施方式
以下,将详细讨论本发明实施例的形成与使用方式。然而应注意的是,实施例提供许多可应用于广泛应用面的发明特点。所讨论的特定实施例仅为举例说明制作与使用本发明实施例的特定方式,不可用以限制本发明实施例的范围。另外,当述及一第一材料层位于一第二材料层上或之上时,包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
图2A-图2E显示根据本发明一或更多实施例的半导体元件200的工艺剖面图。图5显示图2A-图2E中所示的工艺的方法流程图。工艺细节将参照图2A-图2E及图5作说明。
在步骤S510中(图5),于基底210上形成栅极堆叠220。基底210例如为硅基底。或者,基底210可包括锗(Ge)、硅锗(SiGe)、砷化镓、或其他适合的半导体材料。另外,可于基底210中形成浅沟槽绝缘(STI)区(未显示)以隔离基底210中的有源区(active regions)。隔离结构(例如,浅沟槽绝缘区)可由氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐(fluoride-doped silicate)、及/或任何其他低介电常数材料所制成。基底210可还包括其他结构或特征,例如各种掺杂区、埋藏层(buried layer)、及/或外延层(epitaxy layer)。此外,基底210可为绝缘层上覆半导体,例如是绝缘层上覆硅(SOI)。在其他例子中,基底210可包括掺杂外延层、梯度半导体层(gradient semiconductor layer)、及/或可还包括覆盖于不同类型的半导体层上的半导体层,例如硅锗层上覆硅层。
形成于基底210上的栅极堆叠220包括栅极介电层223(其可包括高介电常数介电层)、界面层(interfacial layer)、及/或前述的组合。在一或更多实施例中,高介电常数材料层包括在栅极介电层223中,其例如由氮化硅、氮氧化硅、氧化铪、氧化硅铪(HfSiO)、氮氧化硅铪、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、氧化锆铪(HfZrO)、金属氧化物、金属氮化物、金属硅酸盐(metal silicates)、过渡金属氧化物(transition metal-oxides)、过渡金属氮化物、过渡金属硅酸盐、金属氮氧化物、金属铝酸盐(metal aluminates)、锆硅酸盐(zirconium silicate)、锆铝酸盐、氧化锆、氧化钛、氧化铝、氧化锆-氧化铝合金(HfO2-A12O3alloy)、其他适合的高介电常数材料、及/或前述的组合所形成。高介电常数介电层的厚度例如介于约5至约40的范围之内。
在一些实施例中,栅极介电层223也可包括界面层(未显示)以减少栅极介电层223与基底210之间的伤害。界面层例如包括氧化硅,其形成于基底210上并具有约5至约10的厚度。栅极介电层223可借由原子层沉积(ALD)或其他适合的技术而形成于界面层上。
栅极堆叠220还包括形成于栅极介电层223上的栅极电极225。栅极电极225的厚度例如介于约10至约1000之间。栅极电极225可由多晶硅及/或金属形成。在一或更多实施例中,栅极电极225可包括Al、AlTi、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN、及/或其他适合的导电材料。栅极电极225可借由化学气相沉积、物理气相沉积、溅镀、电镀、原子层沉积、及/或其他适合的工艺而形成。
如图2A所示,栅极堆叠220可例如借由光刻工艺而图案化。具体来说,例如借由旋转涂布法将光致抗蚀剂层(未显示)沉积于用以形成栅极堆叠220的材料层上,光致抗蚀剂层用以形成预期的栅极堆叠220的图案,例如借由曝光、显影、干燥、蚀刻、及其他适合的工艺。在一或更多实施例中,进行蚀刻工艺以移除除了显示于图2A中的栅极堆叠220的预期图案以外的材料层。若有需要,这样的蚀刻工艺可进行多次。然而,栅极的图案化不限于使用干式光刻工艺,而可借由浸润式光刻(immersion lithography)、电子束光刻、或其他适合的工艺而进行。因此,可获得如图2A所示的栅极堆叠图案。
在一或更多实施例中,可进一步于栅极堆叠220之上形成硬掩模(未显示)。硬掩模可包括氮化硅、氮氧化硅、碳化硅、或其他适合的材料。硬掩模可借由沉积工艺或任何适合的方法而形成,并可用作图案化栅极堆叠220时的掩模。
请参照图2B及图5,于栅极堆叠220的侧壁上形成间隙壁230,如步骤S520。间隙壁230例如为介电材料,其不具有或仅具有预定数量的杂质于其中。在一或更多实施例中,间隙壁230可由氮化硅所形成。间隙壁230的其他例子包括氮氧化物。在其他实施例中,间隙壁230为碳化硅。并且,间隙壁230可包含杂质或掺杂物,例如硼、碳、氟、或前述的组合。
间隙壁230可借由使用适合的方法而形成。首先,于栅极堆叠220及基底210上沉积用以形成间隙壁230的材料层,例如可借由等离子体辅助化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、次大气压化学气相沉积(sub-atmospheric chemical vapor deposition,SACVD)、原子层沉积(ALD)、及其相似方法而形成。可将用以形成间隙壁230的材料层形成为具有任何适合的厚度,例如介于约50至约400之间。
另外,将所沉积用以形成间隙壁230的材料层图案化以形成与栅极堆叠220的侧壁接触或紧邻的间隙壁230。图案化可借由适合的技术进行,例如湿式蚀刻工艺、干式蚀刻工艺、或前述的组合。在一或更多实施例中,形成间隙壁230的图案化工艺是借由各向异性干式蚀刻工艺而进行。在蚀刻工艺之后所留下的用以形成间隙壁230的沉积材料层因而形成了间隙壁230,如图2B所示。
虽然图2B于栅极堆叠220的侧壁上仅显示单层的间隙壁,若有需要,可借由适合的技术形成多层的间隙壁/衬层(spacers/liners)。例如,可紧邻间隙壁230而形成第二间隙壁(未显示)以保护间隙壁230免于受到后续的湿式蚀刻及/或清洗工艺的影响,或可重新建立可能于后续工艺中受损的间隙壁。所述额外的间隙壁(未显示)可由氮化硅、氮氧化物、碳化硅、或前述的组合而形成。额外的间隙壁可使用常用的技术而形成,例如等离子体辅助化学气相沉积、低压化学气相沉积、次大气压化学气相沉积、原子层沉积、及其相似工艺。
并且,可于形成间隙壁230之前,将衬层297(仅显示于图2B,并为简化附图而于其他附图中省略)形成于栅极堆叠220与后续形成的间隙壁230之间以避免栅极堆叠220露出,并保护栅极堆叠220免于在后续工艺期间受到伤害或损失。这样的衬层可例如由氧化硅、氮氧化物、氮化硅、氮化硼硅(silicon boron nitride)、或氮化硼而形成。衬层297的厚度例如介于约15至约100之间。
在以上的叙述中,栅极电极225是于间隙壁230形成之前形成,即依照图2A-图2B所示的顺序,为所知的先栅极工艺(gate-first process)。在另一实施例中,采栅极最后工艺(gate-last process),进行相同或相似于先栅极工艺的步骤以形成虚置栅极(dummy gate),例如虚置多晶硅,及间隙壁230(以图2A-图2B所示的顺序)。之后,以适合的金属或导电材料取代虚置栅极以获得栅极电极225。
另外,可使用栅极堆叠220及间隙壁230为掩模,于基底210的有源区(active area)287中形成源极/漏极区298及299。因此,有源区287包括栅极堆叠220及紧邻栅极堆叠220的源极/漏极区298及299。例如,源极/漏极区298及299的形成可借由进行离子注入或扩散工艺而达成。取决于半导体元件的形式,源极/漏极区可掺杂以p型掺杂物(例如硼、或BF2)、n型掺杂物(例如磷或砷)、及/或前述的组合。此外,虽为简洁而省略于此,可在形成间隙壁230之前,于基底210中形成轻掺杂源极/漏极(LDD)区(未显示)。轻掺杂源极/漏极区可借由一或更多的注入工艺而形成于基底210中,例如是离子注入工艺。
图2B显示源极/漏极区298及299,其形成是下列步骤的结果。在第一步骤的离子注入中,使用较薄的间隙壁(未显示)为掩模,并于第二步骤中,移除并重新将较薄的间隙壁建构为较厚的间隙壁(标记为230)。较厚间隙壁230部分覆盖于先前所形成的源极/漏极区298、299之上。然而,不排除其他在此所讨论的配置方式。
请参照图2C及图5,进行栅极堆叠220的顶部部分的移除(步骤S530)。此移除工艺可选择性地使栅极电极225的顶部部分凹下,而使最终的栅极电极225a的顶表面低于间隙壁230的顶表面一预定距离。栅极电极225a的顶表面与间隙壁230的顶表面之间的距离可取决于适于避免栅极电极225a与将形成的源极/漏极接点之间发生短路的长度。在一或更多实施例中,该距离可例如为约20纳米或更多。
移除步骤S530可例如以干式蚀刻工艺进行。在一或更多实施例中,在使栅极堆叠220下凹的工艺之前,可于源极/漏极区289、299上形成虚置层(dummy layer)296以保护源极/漏极区289、299免受蚀刻工艺影响。这样的虚置层296在一或更多实施例中为一介电层,在此也称为“虚置层间介电层(dummy ILD)”,并可包括(但不限于)氧化硅、氮化硅、氮氧化硅、旋转涂布玻璃(spin-on glass)、氟化氧化硅玻璃(FSG)、掺碳氧化硅、聚亚酰胺(polyimide)、其他适合的介电材料、及/或前述的组合。在一些实施例中,虚置层296为光致抗蚀剂层。虚置层296可具有适合的厚度,例如约4000接着,可以化学机械研磨(CMP)将虚置层296平坦化直至栅极堆叠220的顶表面露出。最终结构在一或更多实施例中称为置换栅极结构(replacement gate structure)。在使栅极堆叠220下凹以形成栅极堆叠220a之后,以任何适合的工艺移除虚置层296,例如借由干式蚀刻工艺。
之后,根据一或更多实施例,可进行硅化工艺(例如,自对准硅化)或任何适合的方法以于栅极电极225a及/或源极/漏极区298、299的顶表面提供硅化区以作为接点结构(contact feature)。例如,于露出的栅极电极225a及/或源极/漏极区298、299之上毯覆式沉积金属层(未显示),并接着进行退火步骤以于栅极电极225a及/或源极/漏极区298、299之上形成金属硅化层(在图2C中仅显示位于栅极电极225a上的硅化区293)。接着,例如借由湿式化学蚀刻移除任何未反应的金属。既然栅极电极225a局限于间隙壁230所定义的边界之中,硅化区293也局限于这样的边界之中,并避免突出至间隙壁230的顶部,与图1所示的结构不同。
请参照图2D及图5,于栅极电极225a、间隙壁230、及基底210上沉积保护层(protection layer)240,于步骤S540。具体而言,保护层240是形成在由间隙壁230与栅极电极225a所界定的凹陷之中。在一或更多实施例中,保护层240可为蚀刻停止层(ESL),其例如由氮化硅、氮氧化硅、氧化硅、及/或其他具有适当高含量硅的适合的材料所形成。在一实施例中,保护层240为包括氮化硅的蚀刻停止层。保护层240由任何适合的工艺沉积,包括化学气相沉积工艺,并使其具有足够的厚度以保护栅极电极225a免于接触或暴露于对不准的接触洞。在一实施例中,保护层240具有约200的厚度。在一或更多实施例中,保护层2401沉积成在栅极电极225a上的厚度大于在源极/漏极区298、299上的厚度。
在步骤S540之后,进行制造半导体元件的进一步步骤,包括层间介电层沉积、接触洞的形成、及内连线的形成。例如,请参照图2E,于图2D的结构上形成介电层250(例如,层间介电层),并接着(选择性)借由化学机械研磨工艺将其平坦化。接着,可借由光刻工艺及后续的蚀刻工艺形成每一源极/漏极区的接触洞(contact hole)260,其穿过介电层250以到达相应的源极/漏极区。如图2E所示,源极/漏极区299的接触洞为光刻工艺期间所发生的对不准所形成。
请参照图2E,应注意的是,根据一或更多实施例,即使当对不准在形成源极/漏极接触洞260时发生,栅极电极225a仍受到间隙壁230的升高部分及/或形成于“栅极洞穴(gate cave)”中的保护层240所保护,其中栅极洞穴介于间隙壁230之间,并位于栅极电极225a之上。具体而言,由于接触洞260的对不准,当蚀刻介电层250以形成接触洞260时,保护层240也将被蚀刻。若蚀刻工艺进行足够长的时间,间隙壁230也可能被蚀刻。然而,穿过保护层240及/或间隙壁230的蚀刻比穿过介电层250的蚀刻还要慢得多。因此,接触洞260将具有阶梯式的底部(step-wise bottom),如图2E中的底部部分267a及267b所示。当蚀刻停止时(即,当相应的源极/漏极区299于接触洞260的较低底部部分267a露出时),接触洞260的较高底部部分267b仍由于保护层240及/或间隙壁230的厚度而与栅极电极225a隔有间隔(向上隔开),因而避免栅极电极225a与后续将填于接触洞260中的导电材料(例如,金属)发生短路。上述的蚀刻效应可借由适当地选择及/或改变蚀刻配方(etch recipes)及/或借由适当地选择蚀刻选择比及/或间隙壁230及/或保护层240的厚度、及/或介电层250而达成。
在上述的一或更多的实施例中,即使是当对不准发生时,短路问题仍可避免,因而增加所生产的半导体元件的整体合格率。另外,根据一或更多所揭示实施例而制造的半导体元件具有更高的可靠度,这是因为具有缺陷的单元的形成已显著地减少。
图3A-图3D显示根据本发明另一实施例的半导体元件的工艺剖面图。应注意的是,为了简化,图2A-图2E与图3A-图3D中的相似元件将采用相似的标记标示。
请参照图3A,于基底210上形成栅极堆叠320,且于栅极堆叠320的侧壁上形成间隙壁230。在一或更多实施例中,栅极堆叠320包括栅极介电层223、栅极电极225、选择性的虚置栅极327、及选择性的硬掩模(hard mask)329。
在所说明的特定实施例中,栅极堆叠320包括虚置栅极327及硬掩模329。虚置栅极327(若包括于栅极堆叠320中)可例如由硅、多晶硅、非晶硅、及其他具有所需蚀刻速率的材料所形成,其中所需的蚀刻速率需与栅极电极225与间隙壁230的蚀刻速率有所区别。虚置栅极327可由任何适合的方法形成,例如沉积(如CVD与ALD)、光刻图案化(photolithography patterning)、蚀刻工艺(如干式蚀刻及湿式蚀刻)、及/或前述的组合。硬掩模329(若包括于栅极堆叠320中)例如由氮化硅、氮氧化硅、碳化硅、或其他适合的材料所形成。另外,硬掩模329可由沉积工艺或任何其他适合的方法所形成。在沉积用以形成栅极介电层223、栅极电极225、及虚置栅极327、及/或硬掩模329的材料层之后,进行栅极图案化工艺,例如借着使用硬掩模层为蚀刻掩模,并借着蚀刻以获得栅极堆叠220的预定图案,如图3A所示。
在一或更多实施例中,在栅极堆叠320图案化之后,形成间隙壁230,其接触或紧邻栅极堆叠320的侧壁。如先前所解释,间隙壁230可形成为包括多层的间隙壁/衬层。另外,可使用栅极堆叠320及间隙壁230为掩模,于基底210中形成源极/漏极区(未显示)。此外,在形成间隙壁230之前,可于基底210中形成轻掺杂源极/漏极区(未显示)。如此处所揭示,间隙壁230可重新建构以部分覆盖于已形成的源极/漏极区之上。
在形成间隙壁230之前,可于栅极堆叠320与间隙壁230之间形成衬层397a(仅显示于图3A中,并为简化而于其他附图中省略)以避免栅极堆叠320露出,并保护栅极堆叠320免于在后续工艺期间受到伤害或损失。也可于栅极电极255与虚置栅极327之间、及/或于硬掩模329与虚置栅极327之间、及/或于栅极电极255与硬掩模329之间(若省略虚置栅极327)形成相似的衬层397b(仅显示于图3A中,并为简化而于其他附图中省略)以简化工艺的控制。这样的衬层可例如由氧化硅、氮氧化物、氮化硅、氮化硼硅、或氮化硼所形成。每一衬层的厚度例如介于约15至约100之间。
在一些实施例中,一或更多的衬层397a、397b及虚置栅极327被省略。
请参照图3B,进行移除步骤以自栅极堆叠320移除硬掩模329与虚置栅极327,使栅极电极225的顶表面露出,且低于间隙壁230的顶表面一预定距离。在一或更多实施例中,该距离取决于选择将移除的虚置栅极327与硬掩模的厚度。可适当地决定栅极电极225的顶表面与间隙壁230的顶表面之间的距离以避免栅极电极225与将要形成的源极/漏极接点之间发生短路。在一或更多实施例中,该距离至少为200,且可例如介于约200至约450之间。
在移除步骤中,可例如借由湿式蚀刻工艺、干式蚀刻工艺、其他移除工艺、及/或前述的组合来移除硬掩模329及虚置栅极327。在一或更多实施例中,可借由分别的多个蚀刻工艺来移除硬掩模329及虚置栅极327。例如,进行干式蚀刻工艺以移除硬掩模329,接着可进行使用适合蚀刻剂的湿式蚀刻工艺来移除虚置栅极327。在其他例子中,可如图2C所示,先形成一虚置层(未显示)以保护源极/漏极区,接着再进行回蚀刻工艺(etch back process)以移除硬掩模329,且与硬掩模层329一起,移除与硬掩模329等高的间隙壁230的较高部分。在回蚀刻工艺之后,可接着移除虚置层。间隙壁230所留下的较低部分于图3B中标示为230a。回蚀刻工艺于虚置栅极327露出时停止。所露出的虚置栅极327将如上所述蚀刻移除。
在一或更多实施例中,在移除硬掩模329及虚置栅极327之后,可进行硅化工艺(例如,自对准硅化)或任何适合的方法以于栅极电极225及源极/漏极区(未显示)的顶表面上提供硅化区以如上述作为接触结构。应再次注意的是,位于栅极电极225上的硅化区(未显示)局限在由间隙壁230a所界定的边界之中,且免于突出至间隙壁230a的顶部,不同于图1所示的结构。
请参照图3C,如上所述,于栅极电极225、间隙壁230a、及基底210之上沉积保护层240。在一或更多实施例中,保护层240可为蚀刻停止层,其例如由氮化硅、氮氧化硅、及/或其他适合的材料形成。接着,请参照图3D,沉积介电层250,并接着形成源极/漏极区的接触孔260。如图3D所示,虽然源极/漏极区的接触孔260可能为因对不准而形成的有缺陷的孔洞,仍可借由升高的间隙壁230a及/或如此处所揭示的保护层240而避免短路问题。在一或更多实施例中,将保护层240沉积成在栅极电极225上的厚度大于在源极/漏极区上的厚度,进一步确保短路可被避免。
图4A-图4E显示根据本发明又一实施例的半导体元件的工艺剖面图。此实施例还参照图6作说明。
请参照图4A及图6,形成半导体元件400,其包括基底210,其上具有栅极介电层223、栅极电极225、及间隙壁230,如步骤S610。基底210包括源极/漏极区410。另外,第一介电层450形成于基底210之上。在一或更多实施例中,第一介电层450可为层间介电层,其由氧化硅、氮化硅、氮氧化硅、旋转涂布玻璃、氟化氧化硅玻璃、掺碳氧化硅(例如,SiCOH)、聚亚酰胺、其他适合的介电材料、及/或前述的组合所形成。在一或更多实施例中,于基底210、栅极电极225、及间隙壁230之上沉积用以形成第一介电层450的材料层,并接着以化学机械研磨薄化直至基底210上的栅极电极225与间隙壁230的顶表面露出,如图4A所示,如步骤S620。显示于图4A中的最终结构于一或更多实施例中称作置换栅极结构。
请参照图4B及图6,于每一源极/漏极区410上的第一介电层450中形成接触开口455,如步骤S630。在一例子中,栅极电极225为金属栅极,包含Al、AlTi、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN、及/或其他适合的材料,而间隙壁230由氮化硅、碳化硅、氮氧化硅、及/或其他适合的材料所形成。可例如借由干式蚀刻工艺选择性蚀刻第一介电层450以形成接触开口455,而不对栅极电极225与间隙壁320造成伤害。在一或更多实施例中,借着使用适当的蚀刻气体(例如,BP、CH2F2、CH3F、CF4、O2及He),进行等离子体离子蚀刻工艺以形成接触开口455。在形成接触开口455之后,可如上述进行硅化工艺以于源极/漏极区410上提供硅化区(未显示)。
请参照图4C及图6,于接触开口455中实施金属化工艺,如步骤S640。即,借由任何适合的沉积工艺(例如,蒸镀或溅镀方法,如铜镶嵌工艺)而将选自铝、铜、钨、任何适合的导电材料、及/或前述的组合的接触金属460填入接触开口455中。源极/漏极区410上的硅化区与接触金属460之间形成良好的接触。在一或更多实施例中,可接着进行湿式或干式蚀刻以移除在不希望沉积有金属的表面上的金属原子,例如是在第一介电层450上。
请参照图4D及图6,借由任何适合的方法,例如选择性金属成长工艺(selective metal growth process),而于接触金属460上选择性形成导电材料的升高结构470,如步骤S650。升高结构470可由任何适合的导电材料所形成。在一或更多实施例中,升高结构470可由金属覆盖材料(metal cappingmaterial)(例如,磷化钴钨(CoWP)及钨)所形成,其厚度为约20纳米至约50纳米。例如,可借由选择性金属成长工艺而于接触金属460上沉积CoWP层。在一或更多实施例中,可于接触金属460上喷涂含有钴、钨、及磷的溶液,其例如来自硫酸钴(cobalt sulfate)、次磷酸二氢钠(sodium hypophosphate)、及钨酸铵(ammonium tungstate)。若有需要,可预先涂布例如包含Pd的籽晶溶液(seeding solution)以促进接触金属460上的CoWP的形成。升高结构470可形成至预定的厚度,使升高结构470的顶表面高于栅极电极225的顶表面。可适当地决定升高结构470的厚度以避免栅极电极225与将要形成的源极/漏极内连线之间发生短路。在一或更多实施例中,该厚度例如介于约50至约450之间。例如,升高结构470形成作具有250的厚度。
请参照图4E及图6,于栅极电极225、间隙壁230、及升高结构470上形成保护层240,如步骤S660。在一或更多实施例中,保护层240沉积成在栅极电极225上的厚度大于在源极/漏极区410上的厚度。在一或更多实施例中,进一步于保护层240上沉积第二介电层250(例如,层间介电层),形成源极/漏极区的接触洞260,其穿过介电层250及保护层240,以及于接触洞260中进一步填充接触金属(未显示)以通过接触金属460及导电性升高结构470而与源极/漏极区410电性接触。如图4E所示,源极/漏极区410的接触洞260为由对不准所形成的有缺陷的孔洞。
如图4E所示,接触洞260的形成停止于当升高结构470露出时。接着于接触洞260中所填充的导电材料(例如,金属)可借着形成于栅极电极255的顶部上且位于由升高结构470所界定的边界中的部分的保护层240而免于与栅极电极225形成短路。如上所述,保护层240可为蚀刻停止层,其例如由氮化硅、氮氧化硅、及/或其他适合的材料所形成。保护层240沉积为具有足够的厚度以保护栅极电极225免于接触对不准的接触洞260。在一例子中,保护层240具有介于约50与约500之间的厚度。在一或更多实施例中,保护层240具有约200的厚度。
虽然本发明已以数个优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (14)
1.一种半导体元件,包括:
一半导体基底;
一栅极堆叠,位于该半导体基底之上,该栅极堆叠包括一栅极介电层及一栅极电极;
一间隙壁,形成于该栅极堆叠的侧壁上,其中该间隙壁的一顶表面高于该栅极堆叠的一顶表面;以及
一保护层,位于该栅极堆叠之上,且至少部分填充由位于该栅极堆叠的该顶表面上的该间隙壁所围绕的一空间。
2.如权利要求1所述的半导体元件,其中该保护层覆盖该栅极堆叠及至少一部分的该间隙壁。
3.一种半导体元件的制造方法,包括:
于一半导体基底的一顶表面中的一有源区上形成一栅极堆叠;
于该栅极堆叠的侧壁上形成一间隙壁;
移除该栅极堆叠的一顶部部分以使该间隙壁的一顶表面高于一最终栅极堆叠的一顶表面,其中该最终栅极堆叠为移除该顶部部分后的该栅极堆叠;以及
于该最终栅极堆叠上形成一保护层以至少部分填充由位于该最终栅极堆叠的该顶表面上的该间隙壁所围绕的一空间。
4.如权利要求3所述的半导体元件的制造方法,还包括:
在移除该栅极堆叠的该顶部部分之前,于该半导体基底上及该间隙壁与该栅极堆叠的周围形成一虚置层以保护源极/漏极区,其中所述源极/漏极区形成于该有源区中且邻接该栅极堆叠;
在移除该栅极堆叠的该顶部部分之后,移除该虚置层以露出所述源极/漏极区;以及
在露出的所述源极/漏极区上进行一硅化工艺,该硅化工艺于该最终栅极堆叠、该间隙壁、及硅化的该源极/漏极区上形成该保护层之前进行。
5.如权利要求3所述的半导体元件的制造方法,其中
该栅极堆叠包括一栅极电极及一虚置栅极,该虚置栅极定义该栅极堆叠的该顶部部分;以及
该移除步骤包括移除该虚置栅极。
6.如权利要求5所述的半导体元件的制造方法,其中该栅极堆叠还包括至少一衬层,至少位于任意两个(i)该虚置栅极、(ii)该栅极电极、及(iii)该间隙壁之间的一界面以促进该虚置栅极的移除。
7.如权利要求5所述的半导体元件的制造方法,其中
该栅极堆叠还包括一硬掩模,位于该虚置栅极的一顶部上;以及
该移除步骤包括在移除该虚置栅极之前,移除该硬掩模。
8.如权利要求7所述的半导体元件的制造方法,其中
该硬掩模向上突出于该间隙壁之上;以及
在移除该硬掩模期间,该硬掩模及该间隙壁的一较高部分同时被移除,直至该虚置栅极露出。
9.如权利要求8所述的半导体元件的制造方法,其中该栅极堆叠还包括至少一衬层,至少位于任意两个(i)该虚置栅极、(ii)该栅极电极、(iii)该间隙壁、及(iv)该硬掩模之间的一界面以促进至少一该虚置栅极及该硬掩模的移除。
10.如权利要求3所述的半导体元件的制造方法,还包括:
在形成该保护层之前,在(a)形成于该有源区中且紧邻该栅极堆叠的源极/漏极区上,及在(b)该最终栅极堆叠的该顶表面上进行一硅化工艺;
其中由该硅化工艺所造成形成于该最终栅极堆叠的该顶表面上的一硅化区局限于由该间隙壁所围绕的该空间之中。
11.一种半导体元件,包括:
一半导体基底,该半导体基底的一顶表面上具有至少一有源区;
一栅极堆叠,形成于该有源区上,该有源区还包括紧邻该栅极堆叠的源极/漏极区;
一间隙壁,形成于该栅极堆叠的侧壁上;
一升高接触结构,自该源极/漏极区向上延伸,该升高接触结构具有一顶表面,高于该栅极堆叠的一顶表面;以及
一保护层,位于该栅极堆叠及该间隙壁之上,且至少部分填充形成于该升高接触结构的该顶表面与该栅极堆叠的该顶表面之间的一空间。
12.如权利要求11所述的半导体元件,其中该升高接触结构包括
一接触金属,直接电性接触该源极/漏极区,且与该栅极堆叠等高;以及
一金属层,成长于该接触金属之上以定义出该升高接触结构的该顶表面。
13.一种半导体元件的制造方法,该半导体元件形成自一栅极置换结构,该栅极置换结构包括位于一半导体基底的一顶表面上的一有源区上的一栅极堆叠、位于该栅极堆叠的侧壁上的一间隙壁、以及位于该基底上且围绕该栅极堆叠与该间隙壁的一介电层,该有源区还包括紧邻该栅极堆叠的源极/漏极区,该方法包括:
于该半导体基底的该顶表面上的该源极/漏极区上的该介电层中形成一接触开口;
于该接触开口中填充一导电材料;
于填充于该接触开口中的该导电材料上形成一导电升高结构,使该导电升高结构的一顶表面高于该栅极堆叠的一顶表面;以及
于该栅极堆叠及该间隙壁上形成一保护层以至少部分填充形成于该导电升高结构的该顶表面与该栅极堆叠的该顶表面之间的一空间。
14.如权利要求13所述的半导体元件的制造方法,还包括:
于该保护层上形成一介电层;
进行一蚀刻步骤以形成一进一步接触开口,该进一步接触开口穿过该介电层,其中该蚀刻步骤停止于当该导电升高结构的该顶表面露出,而不到达该栅极堆叠的该顶表面;以及
于该进一步接触开口中填充一进一步导电材料,且不与该栅极堆叠形成短路。
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CN110246804A (zh) * | 2018-03-07 | 2019-09-17 | 格芯公司 | 接触结构 |
CN110246804B (zh) * | 2018-03-07 | 2024-03-12 | 格芯美国公司 | 接触结构 |
CN113161352A (zh) * | 2020-01-23 | 2021-07-23 | 南亚科技股份有限公司 | 半导体元件及其制备方法 |
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US9601587B2 (en) | 2017-03-21 |
US20110193144A1 (en) | 2011-08-11 |
US8946828B2 (en) | 2015-02-03 |
US20150129990A1 (en) | 2015-05-14 |
CN102148236B (zh) | 2013-04-24 |
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