CN110071091B - 接触结构 - Google Patents

接触结构 Download PDF

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CN110071091B
CN110071091B CN201810472293.1A CN201810472293A CN110071091B CN 110071091 B CN110071091 B CN 110071091B CN 201810472293 A CN201810472293 A CN 201810472293A CN 110071091 B CN110071091 B CN 110071091B
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contact
gate structure
source
sidewall material
upper sidewall
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CN110071091A (zh
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舒杰辉
吴旭升
黄海苟
张宏光
刘佩
L·埃科诺米可斯
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Lattice Core Usa Inc
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Abstract

本发明涉及接触结构。本公开涉及半导体结构，更特别地，涉及位于有源栅极结构之上的接触以及制造方法。所述结构包括：由位于侧壁材料之间的导电材料构成的有源栅极结构；位于所述侧壁材料上方的上侧壁材料，所述上侧壁材料与所述侧壁材料的材料不同；以及与所述有源栅极结构中的所述导电材料电接触的接触结构。所述接触结构位于所述侧壁材料之间和所述上侧壁材料之间。

Description

接触结构
技术领域
本公开涉及半导体结构，更特别地，涉及接触结构和制造方法。
背景技术
随着半导体工艺继续向下缩小，例如，缩放，特征之间的期望间隔(即，栅距(pitch))也变小。为此，在较小的技术节点中，由于关键尺寸(CD)缩放和处理能力以及用于制造这种结构的材料，制造例如互连的后段制程(BEOL)和中段制程(MOL)金属化特征甚至变得更加困难。
例如，为了制造用于有源栅极接触和源极/漏极接触的互连结构，有必要去除栅极结构上方和邻近栅极结构的电介质材料。该电介质材料的去除通过蚀刻工艺来提供，该蚀刻工艺也倾向于侵蚀栅极结构中的隔离物材料。也就是，在用于形成接触的开口的下游蚀刻工艺中，用于栅极结构的隔离物或侧壁的低k电介质材料可被侵蚀掉。这种侧壁材料的损失将暴露栅极结构中的金属材料，导致栅极结构中的金属材料与用于形成接触的金属材料本身之间的短路。
发明内容
在本公开的一方面，一种结构包括：由位于侧壁材料之间的导电材料构成的有源栅极结构；位于所述侧壁材料上方的上侧壁材料，所述上侧壁材料与所述侧壁材料的材料不同；以及与所述有源栅极结构中的所述导电材料电接触的接触结构，所述接触结构位于所述侧壁材料之间和所述上侧壁材料之间。
在本公开的一方面，一种结构包括：形成在衬底上的下侧壁材料；位于所述下侧壁材料上方的上侧壁材料，所述上侧壁材料具有不同于所述下侧壁材料的蚀刻选择性；位于所述下侧壁材料之间的有源栅极结构；以及与所述有源栅极结构电接触的接触结构。所述接触结构从所述上侧壁材料之间延伸并到所述上侧壁材料上方的层间电介质材料中。
在本公开的一方面，一种方法包括：在半导体衬底上形成栅极结构；形成与所述栅极结构邻近的接触材料；使所述接触材料凹陷以形成凹腔；在所述凹腔的侧壁上形成隔离物；在所述隔离物之上用电介质材料填充所述凹腔；以及平坦化所述电介质材料。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本公开的方面的除了其他特征之外的具有源极/漏极区域的有源栅极结构以及相应的制造方法。
图2示出了根据本公开的方面的除了其他特征之外的位于邻近有源栅极结构之间的凹陷的绝缘体材料(例如，形成腔结构)以及相应的制造方法。
图3示出了根据本公开的方面的除了其他特征之外的位于腔结构内的导电填充材料以及相应的制造方法。
图4示出根据本公开的方面的除了其他特征之外的导电填充材料的凹陷以形成扩大的腔结构以及相应的制造方法。
图5示出了根据本公开的方面的除了其他特征之外的对图4的腔进行加衬的侧壁材料以及相应制造方法。
图6示出了根据本公开的方面的除了其他特征之外的填充扩大的腔结构的绝缘体材料以及相应的制造方法。
图7A和7B示出了根据本公开的方面的除了其他特征之外的用于有源栅极结构和源极/漏极区域的接触开口以及相应的制造方法。
图8A和8B示出了根据本公开的方面的除了其他特征之外的填充接触开口的接触材料以及相应的制造方法。
具体实施方式
本公开涉及半导体结构，更特别地，涉及接触结构和制造方法。更具体地，本公开提供了位于有源栅极之上以及在实施例中的位于源极/漏极区域之上的接触结构。有利地，形成接触结构的方法避免了源极/漏极接触与栅极金属化特征之间的短路。而且，本文公开的方法提供了稳健的集成方案，以在有源栅极之上做接触，特别是在较小的技术节点中。
在实施例中，接触结构可以通过在具有源极/漏极区域的半导体衬底上形成栅极结构来制造出。源极/漏极接触层邻近栅极结构形成，该栅极结构被凹陷以在源极/漏极区域之上形成腔结构。例如HfO2的内部隔离物材料形成在腔结构的侧壁上。然后用电介质材料(例如，SiC)填充腔结构，接着平坦化电介质材料。在用于源极/漏极区域和有源栅极的电介质材料中形成接触开口，接着在接触开口内进行金属填充工艺。在实施例中，形成在接触开口的侧壁上的内部隔离物材料(例如，HfO2)将防止接触与有源栅极的金属化之间短路。
本公开的结构可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的结构的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，结构的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1示出了根据本公开的方面的除了其他特征之外的具有源极/漏极区域的有源栅极结构以及相应的制造方法。特别地，结构10包括形成在衬底14上的多个栅极结构12。在实施例中，栅极结构12可以是例如由金属材料和电介质材料构成的有源金属栅极结构。在实施例中，例如导电材料的金属材料可以是钨以及依赖于有源栅极结构的期望特性和/或性能的其他功函数金属。电介质材料可以是高k电介质材料。在实施例中，作为示例，高k电介质栅极材料可以是基于铪的电介质。在另外的实施例中，这种高k电介质的实例包括但不限于：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其多层的组合。
在实施例中，栅极结构12可以是形成在平面衬底14或由衬底14构成的鳍状结构上的替代栅极结构。在实施例中，替代栅极制造方法是公知的，使得关于本领域普通技术人员的理解不需要进一步的解释。衬底14可以是包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其他III/V或II/VI化合物半导体的任何半导体材料。
鳍结构可以使用已知的侧壁成像转移(SIT)技术来制造。在SIT技术中，例如，使用常规的沉积、光刻和蚀刻工艺在衬底14上形成芯轴(mandrel)。在芯轴材料上形成抗蚀剂，该抗蚀剂被曝光以形成图案(开口)。通过开口执行反应离子蚀刻以形成芯轴。在实施例中，依赖于鳍结构之间的期望尺寸，芯轴可具有不同的宽度和/或间隔。在芯轴的侧壁上形成隔离物，该隔离物优选为不同于芯轴的材料，并且为使用本领域技术人员已知的常规沉积方法形成。例如，隔离物的宽度可以与鳍结构的尺寸相匹配。使用对芯轴材料有选择性的常规蚀刻工艺去除或剥离芯轴。然后在隔离物的间隔内执行蚀刻以形成亚光刻特征。然后可以剥离侧壁隔离物。在实施例中，宽的鳍结构也可以在这个或其他图案化工艺期间或者通过其他常规的图案化工艺形成，如本公开所考虑的。
仍然参考图1，有源栅极结构12包括位于金属材料之上的覆盖材料16。覆盖材料16可以是例如使用例如化学气相沉积(CVD)的常规沉积工艺沉积的氮化物材料，接着进行用于替代栅极工艺的平坦化工艺。在使用先栅(gate first)工艺的实施例中，沉积工艺之后可以进行图案化工艺以一起图案化栅极材料和覆盖材料。在实施例中，覆盖材料16可以是包括SiN的其他材料或对后续蚀刻工艺有抵抗力的其他材料。
在有源栅极结构12和覆盖材料16的侧面上提供侧壁或隔离物18。隔离物18可以具有约5nm至约10nm的厚度以及具有在例如栅极结构12中的导电材料的金属材料上方延伸的高度。隔离物18可以由例如SiOCN、SiOC、SiCN等的任何低k电介质材料构成。在后栅(gatelast)实施例(例如，替代栅极工艺)中，在有源栅极结构之前，通过例如CVD的常规沉积工艺形成隔离物18。可以使用常规沉积工艺沉积侧壁，接着进行图案化工艺，即，各向同性蚀刻工艺。
源极和漏极区域20邻近有源栅极结构12形成。在实施例中，源极和漏极区域20可以是用常规的离子注入工艺或掺杂工艺形成的平面的或升高的外延半导体区域。可以在源极和漏极区域20上形成硅化物接触22(区域)。如本领域技术人员应该理解的，硅化物工艺开始于在完全形成并图案化的半导体器件(例如，掺杂或离子注入的源极和漏极区域以及相应的器件)之上沉积薄的过渡金属层，例如，镍、钴或钛。在沉积材料之后，加热该结构，允许过渡金属与半导体器件的有源区(例如，源极、漏极、栅极接触区域)中的暴露的硅(或本文所述的其他半导体材料)反应，形成低电阻过渡金属硅化物。在该反应之后，通过化学蚀刻去除任何剩余的过渡金属，在器件的有源区中留下硅化物接触22。
在实施例中，在栅极结构12之间提供层间电介质材料24。层间电介质材料24可以是能够经历例如化学机械抛光(CMP)的平坦化工艺的TEOS。STI结构26也可以邻近鳍结构设置，例如，在鳍结构的端部。使用本领域公知的常规光刻、蚀刻和沉积工艺在衬底14中形成STI结构26。在实施例中，STI结构26可以端到端地(end-to-end)分隔开鳍结构。
在图2中，去除层间电介质材料24以暴露源极和漏极区域20的硅化物接触22，从而形成腔结构27。在实施例中，可以通过使用抗蚀剂叠层28的常规蚀刻工艺去除层间电介质材料24。例如，将形成在图1限定的结构之上的抗蚀剂叠层28暴露于能量(光)以形成图案(开口)。使用具有对层间电介质材料24具有选择性化学(chemistry)的例如反应离子蚀刻(RIE)的蚀刻工艺，通过穿过抗蚀剂叠层28的开口去除绝缘体材料(例如，层间电介质材料24)，以形成腔27。蚀刻工艺将暴露源极和漏极区域20的硅化物接触22。
在图3中，通过常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂叠层，然后进行导电填充工艺。在实施例中，导电填充工艺包括使用例如化学气相沉积(CVD)或镀覆工艺的常规沉积工艺将导电材料30沉积在腔结构27中。在实施例中，导电材料30将与源极和漏极区域20的硅化物接触22自对准并直接接触。
导电材料30可以是用在半导体制造工艺中的任何互连材料。例如，导电材料30可以是钨材料；尽管在本文中也考虑其他材料，诸如钴、铝等。包括结构的上部的任何残余材料可以通过常规化学机械抛光(CMP)工艺去除(例如，被平坦化)。
如图4所示，使导电材料30和隔离物18的一部分凹陷以形成扩大的腔结构32。如图4所示，扩大的腔结构32的下部将保持在栅极结构12的高度之上，例如，保持在栅极结构12中的导电材料的高度之上。更具体地，导电材料30和隔离物18的部分将被凹陷至覆盖材料16的范围内的高度。在实施例中，可以通过各向异性蚀刻去除导电材料30，接着对例如隔离物材料的隔离物18进行各向同性蚀刻。
图5示出了对例如扩大的腔结构的腔结构32进行加衬的侧壁材料(例如，内部隔离物材料)34。在实施例中，侧壁材料34可以是高k电介质材料，例如，HfO2或其他高k电介质。可选地，侧壁材料34可以是例如TiO2或Al2O3的金属氧化物。在任何这些情况下，本领域技术人员应该认识到，侧壁材料34将具有对诸如SiN和SiO2的低k材料的蚀刻选择性。由于隔离物18和覆盖材料16由这种低k材料构成，所以如本文所述，使用例如HfO2的侧壁材料34为下游接触部形成过程提供了好处。
在实施例中，侧壁材料34可以通过例如CVD或ALD的常规沉积工艺毯式沉积至约5nm至约10nm的厚度；尽管在本文中也考虑其他厚度。在实施例中，侧壁材料34的厚度应该基本上等于侧壁隔离物18的厚度。在沉积工艺之后，侧壁材料34将经历各向异性蚀刻工艺，留下位于腔结构32的侧壁上的侧壁材料。值得注意的是，侧壁材料34为下伏的导电材料30提供蚀刻选择性，因为在蚀刻侧壁材料34期间，凹陷的深度没有改变。
图6示出了形成在侧壁材料34上的绝缘体材料36，该绝缘体材料36进一步填充腔结构32的剩余部分。在实施例中，绝缘体材料36是SiC材料；尽管在本文中也考虑其他低k电介质材料。例如，绝缘体材料36可以例如是SiCN或SiOC。以这种方式，在高k或金属氧化物侧壁材料34与绝缘体材料36之间存在蚀刻选择性。在实施例中，绝缘体材料36可以通过常规CVD工艺沉积，接着进行平坦化工艺。在实施例中，平坦化工艺可以去除在图5中描述的蚀刻工艺期间的隔离物18的可能已被损坏的任何侧壁材料。
图7A和7B分别示出了用于有源栅极结构12和源极/漏极区域20的接触开口38a、38b。在实施例中，在形成接触开口38a、38b之前，在材料34和绝缘体材料36以及图6中示出的结构的其他暴露表面之上沉积层间电介质材料40。在实施例中，然后通过常规的光刻和蚀刻工艺形成接触开口38a、38b。在实施例中，接触开口38a形成在隔离物18的上表面下方并且将暴露栅极结构12中的金属材料(图7B)；而接触开口38b将暴露将要形成至源极/漏极区域20的接触的导电材料30(图7A)。
应该认识到，在形成接触开口38a期间，将去除覆盖材料16，从而暴露栅极结构12中的金属材料。并且，由于隔离物18位于栅极结构12中的金属材料上方，该金属材料现在将位于隔离物18下方并且位于侧壁材料34下方。以这种方式，隔离物18和在侧壁材料34下方将防止接触材料与用于源极/漏极区域20的接触材料短路。
本领域技术人员应该认识到，侧壁材料34(例如，高k电介质材料或金属氧化物)将对绝缘体材料36(以及隔离物18的侧壁材料)具有蚀刻选择性。因此，材料34将在此蚀刻工艺期间保护隔离物18，使得在形成源极/漏极接触开口38b时，栅极结构12中的金属材料将不会暴露。由此注意，本领域普通技术人员现在应该理解，沉积在源极/漏极接触开口38b中的接触材料不会与栅极结构12中的金属材料短路。类似地，沉积到用于有源栅极结构12的开口38a中的接触材料将不会与用于源极/漏极区域20的接触材料中的金属材料短路。因此，使用该材料将防止接触到栅极短路。
图8A和8B示出了填充接触开口38a、38b的接触金属材料42。在实施例中，接触金属材料42可以是钨或例如铝等的其他接触材料。可以使用例如CVD、原子层沉积(ALD)或镀覆工艺的常规沉积工艺在接触开口38a、38b内沉积接触金属材料42。以这种方式，接触金属材料42将形成位于隔离物18的侧壁材料之间并且位于上侧壁材料34之间的、与有源栅极结构12直接电接触的接触结构。类似地，接触金属材料42将位于上侧壁材料34之间、与源极/漏极区域20的硅化物22直接电接触。作为示例，在沉积工艺之后，可以使用CMP工艺去除任何残余的金属材料。
如现在应该理解的那样，图8A示出了通过导电材料30和硅化物部分22与源极和漏极区域20接触的接触材料42；而在图8B中，接触材料42与栅极结构12接触。在这两种表示中，接触材料42位于侧壁材料18之间并位于上侧壁材料34之间。另一方面，(i)源极和漏极区域20、导电材料30和硅化物部分22位于侧壁材料18之间，以及(ii)栅极结构12位于侧壁材料18之间。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (14)

1.一种半导体结构，包括：
由位于侧壁材料之间的导电材料构成的有源栅极结构；
位于所述侧壁材料上方的上侧壁材料，所述上侧壁材料与所述侧壁材料的材料不同；以及
与所述有源栅极结构中的所述导电材料电接触的接触结构，所述接触结构位于所述侧壁材料之间和所述上侧壁材料之间,
其中所述上侧壁材料将用于所述有源栅极结构的所述接触结构与所述有源栅极结构的源极/漏极区域的接触结构分隔开,
其中所述源极/漏极区域的所述接触结构的下部位于所述侧壁材料之间，并且所述源极/漏极区域的所述接触结构的上部位于所述上部侧壁材料之间并直接接触所述上侧壁材料的整个侧表面。
2.根据权利要求1所述的半导体结构，其中所述侧壁材料是低k电介质材料，并且所述上侧壁材料具有不同于所述低k电介质材料的蚀刻选择性。
3.根据权利要求2所述的半导体结构，其中所述上侧壁材料是高k电介质材料。
4.根据权利要求2所述的半导体结构，其中所述上侧壁材料是金属氧化物材料。
5.根据权利要求1所述的半导体结构，其中所述源极/漏极区域的所述接触结构通过所述上侧壁材料与所述有源栅极结构的所述导电材料分隔开。
6.根据权利要求5所述的结构，其中所述上侧壁材料被定位和构造成防止所述源极/漏极区域的所述接触结构与所述有源栅极结构中的所述导电材料之间短路。
7.一种半导体结构，包括：
形成在衬底上的下侧壁材料；
位于所述下侧壁材料上方的上侧壁材料，所述上侧壁材料具有不同于所述下侧壁材料的蚀刻选择性；
位于所述下侧壁材料之间的有源栅极结构；以及
与所述有源栅极结构电接触的接触结构，所述接触结构从所述上侧壁材料之间延伸并到所述上侧壁材料上方的层间电介质材料中，
其中所述上侧壁材料将用于所述有源栅极结构的所述接触结构与所述有源栅极结构的源极/漏极区域的接触结构分隔开，
所述源极/漏极区域的所述接触结构的下部位于所述下侧壁材料之间，并且所述源极/漏极区域的所述接触结构的上部位于所述上侧壁材料之间，直接接触所述上侧壁材料的整个侧表面并且延伸到所述层间电介质材料中；以及
所述源极/漏极区域的所述接触结构通过所述上侧壁材料与所述有源栅极结构分隔开。
8.根据权利要求7所述的结构，其中所述下侧壁材料是低k电介质材料并且所述上侧壁材料是高k电介质材料。
9.根据权利要求7所述的结构，其中所述下侧壁材料是低k电介质材料并且所述上侧壁材料是金属氧化物材料。
10.根据权利要求7所述的结构，其中所述上侧壁材料被定位并构造成防止所述源极/漏极区域的所述接触结构与所述有源栅极结构之间的短路。
11.一种用于制造半导体结构的方法，包括：
在半导体衬底上形成栅极结构；
形成与所述栅极结构邻近的接触材料；
使所述接触材料凹陷以形成凹腔；
在所述凹腔的侧壁上形成隔离物；
在所述隔离物之上用电介质材料填充凹腔；
平坦化所述电介质材料；
去除所述电介质材料以形成在所述栅极结构的源极/漏极区域之上的第一腔和所述栅极结构之上的第二腔；以及
沉积导电材料以在所述凹腔和所述第一腔中形成所述源极/漏极区域的接触结构和在所述第二腔中形成所述栅极结构的接触结构，
其中，所述隔离物将用于所述栅极结构的所述接触结构与所述源极/漏极区域的所述接触结构分隔开，
其中，所述源极/漏极区域的所述接触结构的上部位于所述隔离物之间，直接接触所述隔离物的整个侧表面并且延伸到所述电介质材料中。
12.根据权利要求11所述的方法，其中所述电介质材料和所述隔离物具有不同的蚀刻选择性。
13.根据权利要求12所述的方法，其中所述电介质材料是SiC并且所述隔离物是HfO2。
14.根据权利要求11所述的方法，其中所述隔离物位于所述栅极结构的有源区上方，并且将所述第二腔中的所述导电材料与所述凹腔分隔开。
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