CN110098174B - 帽结构 - Google Patents

帽结构 Download PDF

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CN110098174B
CN110098174B CN201811633460.2A CN201811633460A CN110098174B CN 110098174 B CN110098174 B CN 110098174B CN 201811633460 A CN201811633460 A CN 201811633460A CN 110098174 B CN110098174 B CN 110098174B
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semiconductor structure
gate
capping
cap
conductive gate
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CN110098174A (zh
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高金晟
D·耶格
张志强
M·阿奎利诺
P·卡彭特
洪浚植
M·鲁特科夫斯基
黄海苟
高明·哈
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Lattice Core Usa Inc
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Abstract

本发明涉及一种帽结构。本公开涉及半导体结构，更特别地，涉及帽结构以及制造方法。该结构包括：由导电栅极材料构成的栅极结构；位于栅极结构上、在导电栅极材料上方延伸的侧壁隔离物；以及位于导电栅极材料上并且在栅极结构上的侧壁隔离物之上延伸的帽盖材料。

Description

帽结构
技术领域
本公开涉及半导体结构，更特别地，涉及帽结构以及制造方法。
背景技术
随着半导体工艺继续向下缩放，例如，缩小，特征之间的期望的间距(即，栅距(pitch))也变得更小。为此，在较小的技术节点中，由于临界尺寸(CD)缩放和处理能力以及用于制造这种结构的材料，制造后段制程(BEOL)和中段制程(MOL)金属化特征(例如，互连)变得更加困难。
例如，为了制造用于源极和漏极接触的互连结构，必须去除与栅极结构相邻的电介质材料。通过蚀刻工艺提供电介质材料的去除，该蚀刻工艺也倾向于侵蚀栅极结构的隔离物材料。也就是说，用于栅极结构的隔离物或侧壁的低k电介质材料可以在用于形成漏极和源极接触的开口的下游蚀刻工艺中被侵蚀掉。这种材料损失将暴露栅极结构的金属材料，导致栅极结构的金属材料与用于形成接触的金属材料本身之间短路。
发明内容
在本发明的方面，一种结构包括：由导电栅极材料构成的栅极结构；位于栅极结构上、在导电栅极材料上方延伸的侧壁隔离物；以及位于导电栅极材料上并且在栅极结构上的侧壁隔离物之上延伸的帽盖材料。
在本发明的方面，一种结构包括：由导电栅极材料构成的栅极结构；位于栅极结构上的侧壁隔离物；位于侧壁隔离物上的蚀刻停止层；以及位于导电栅极材料上并且悬在侧壁隔离物之上的T形双层帽。
在本公开的方面，一种方法包括：在衬底上形成由导电栅极材料构成的栅极结构；在导电栅极材料上形成帽盖材料；在栅极结构和帽盖材料上形成侧壁隔离物；使帽盖材料凹陷到侧壁隔离物下方；以及在第一帽盖材料上形成第二帽盖材料，该第二帽盖材料悬在侧壁隔离物之上。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本公开的方面的除了其他特征之外的栅极结构以及相应的制造工艺。
图2示出了根据本公开的方面的除了其他特征之外的位于栅极结构之上的凹陷的帽盖材料以及相应的制造工艺。
图3A示出了根据本公开的方面的除了其他特征之外的位于栅极结构之上的扩大的凹部以及相应的制造工艺。
图3B示出了可选实施例，其中CESL未被蚀刻或被凹陷。
图4示出了根据本公开的方面的除了其他特征之外的位于凹陷内的填充材料以及相应的制造工艺。
图5示出了根据本公开的方面的除了其他特征之外的具有平坦化表面的填充材料以及相应的制造工艺。
图6示出了根据本公开的方面的除了其他特征之外的与栅极结构邻近的接触开口以及相应的制造工艺。
图7示出了根据本公开的方面的除了其他特征之外的位于接触开口中的接触以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更特别地，涉及帽结构以及制造方法。更具体地，本公开涉及稳健的(robust)双层T形牺牲帽以及制造方法。有利地，通过实施本文所述的方法和结构，帽结构将在下游蚀刻工艺期间保护栅极结构的低k隔离物，从而防止金属栅极材料和源极/漏极接触之间的短路。
在实施例中，帽结构可以是氮化物材料的T形牺牲帽，其将在下游蚀刻工艺期间保护栅极结构的低k隔离物。在可选实施例中，T形牺牲帽可以是在下游蚀刻工艺期间将保护栅极结构的低k隔离物的其他材料。例如，T形牺牲帽由表现出抵抗蚀刻工艺的SiOC构成，该蚀刻工艺例如为HF蚀刻工艺。在另外的实施例中，T形牺牲帽可以由氮化物和SiOC的双层构成。
本公开的结构可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的结构的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，该结构的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1示出了根据本公开的方面的结构和相应的制造工艺。结构10包括形成在衬底14上的多个栅极结构12和虚设(dummy)栅极结构12a。虚设栅极结构12a设置在例如衬底14的鳍结构的边缘。在实施例中，栅极结构12可以是由金属材料和电介质材料构成的例如金属栅极结构。在实施例中，依赖于栅极结构的期望特性和/或性能，例如金属材料的导电材料可以是钨和其他功函数金属。电介质材料可以是高k电介质材料。在实施例中，作为示例，高k电介质栅极材料可以是基于铪的电介质。在另外的实施例中，这种高k电介质的示例包括但不限于：Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其的多层的组合。
在实施例中，栅极结构12可以是形成在平面衬底14上或形成在由衬底14构成的鳍结构上的替代栅极结构。如已知的，替代栅极制造工艺是众所周知的，使得不需要进一步说明使本领域普通技术人员理解以实施该结构。衬底14可以是任何半导体材料，包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和其他III/V或II/VI化合物半导体。
可以使用已知的侧壁成像转移(SIT)技术来制造鳍结构。在SIT技术中，例如，使用常规的沉积、光刻和蚀刻工艺在衬底14上形成芯轴(mandrel)。在芯轴材料上形成抗蚀剂，并将该抗蚀剂暴露于光以形成图案(开口)。通过开口执行反应离子蚀刻以形成芯轴。在实施例中，依赖于鳍结构之间的期望尺寸，芯轴可具有不同的宽度和/或间隔。隔离物形成在芯轴的侧壁上，该隔离物优选地是与芯轴不同的材料，以及该隔离物使用本领域技术人员已知的常规沉积工艺形成。例如，隔离物可以具有与鳍结构的尺寸匹配的宽度。使用对芯轴材料有选择性的常规的蚀刻工艺去除或剥离芯轴。然后在隔离物的间隔内执行蚀刻以形成亚光刻特征。然后可以剥离侧壁隔离物。在实施例中，宽鳍结构也可以在该图案化工艺或其他图案化工艺期间形成，或者通过其他常规图案化工艺形成，如本公开所预期的。
仍然参考图1，栅极结构12(和虚设栅极结构12a)包括位于金属材料上的帽盖材料16。该帽盖材料16可以是例如使用例如化学气相沉积(CVD)的常规沉积工艺沉积的氮化物材料，然后进行图案化工艺。在实施例中，帽盖材料16可以是其他材料，包括SiN或其他抵抗后续蚀刻工艺的材料。侧壁或隔离物18设置在栅极结构12、12a和帽盖材料16的侧面上。侧壁18具有在例如导电材料的栅极材料上方延伸的高度。侧壁18也可以由任何低k电介质材料构成，例如，SiOCN。在实施例中，侧壁18通过例如CVD的常规的沉积工艺形成，然后进行常规的图案化工艺，即，各向同性蚀刻工艺。
源极和漏极区域20邻近栅极结构12形成，其中在邻近的栅极结构12当中共享源极或漏极。在实施例中，源极和漏极区域20通过常规的离子注入工艺或掺杂工艺形成。硅化物接触20a(区域)可以形成在源极区域和漏极区域20上。如本领域技术人员应该理解的，硅化物工艺开始于在完全形成和图案化的半导体器件(例如，掺杂或离子注入的源极和漏极区域以及相应的器件)上沉积薄的过渡金属层，例如，镍、钴或钛。在沉积材料之后，加热上述结构允许过渡金属与半导体器件的有源区域(例如，源极、漏极、栅极接触区域)中暴露的硅(或如本文所述的其他半导体材料)反应，从而形成低电阻过渡金属硅化物。在该反应之后，通过化学蚀刻去除任何剩余的过渡金属，从而在器件的有源区域中留下硅化物接触20a。
接触蚀刻停止层(CESL)22设置在邻近的扩散部(例如，源极/漏极区域)之间。CESL22可以包括氮化物或比形成在CESL 22的顶部上以及形成在邻近的栅极结构12之间的例如SiO2的层间电介质材料24更硬(更耐受)蚀刻的氮化物或任何其他材料。在实施例中，层间电介质材料24可以是TEOS，其可以经受平坦化工艺，例如，化学机械抛光(CMP)。层间电介质材料24的厚度可为约100nm至约500nm；尽管基于特定技术节点考虑了其他尺寸，例如，110nm。
在图2中，帽盖材料16在侧壁18之间凹陷。在实施例中，凹部26可以通过使用例如不需要掩模的选择性蚀刻工艺来提供。帽盖材料16可以凹陷到侧壁18的顶表面下方，更具体地，可以去除帽盖材料16的高度的约2/3的帽盖材料16。本领域技术人员应该认识到，本文考虑了其他凹陷深度。例如，可以去除多于或少于2/3的帽盖材料16，注意到，帽盖材料16仍然应该存在于栅极结构12、12a中的金属材料之上，以提供关于后续下游工艺的保护。可以实施不同的氮化物RIE以具有不同的形状，并因此具有关于帽盖材料16的不同的凹陷深度。
如图3A所示，侧壁18和可选的CESL 22可以凹陷到与帽盖材料16相同的水平。在实施例中，可以通过选择性蚀刻工艺而不需要掩模使侧壁18和CESL 22凹陷。在实施例中，蚀刻工艺导致扩大的凹部26’。蚀刻工艺可以是远程等离子体辅助干法蚀刻工艺，其涉及同时暴露于H2、NF3和NH3等离子体副产物。在这种类型的蚀刻工艺中，氢和氟物种(species)的远程等离子体激发允许无等离子体损伤(plasma-damage-free)的衬底处理。这种类型的蚀刻对于氧化硅层也很大程度上是保形的和选择性的，但是不容易蚀刻其他材料，例如，多晶等。
图3B示出了可选实施例，其中CESL 22未被蚀刻或被凹陷。在这种情况下，产生了较小的凹部26”，其中图4-7的步骤可以直接跟随其后。也就是说，如图4所示的材料28可以沉积在由CESL 22限定的较小的凹部26”中(也如图3B所示)，然后进行图5-7所示的其余工艺。
在图4中，使用例如常规的沉积工艺将材料28沉积在凹部26’内。在实施例中，材料28可以是SiOC或抵抗后续蚀刻工艺以及更具体地为在下游HF和其他蚀刻化学(chemistry)期间具有抵抗力的其他材料。例如，材料28可以是SPARC k4.9。优选地，材料28可以是在沉积工艺中不在帽中形成缝的材料。在实施例中，可以使用常规CVD工艺将材料28沉积至约20至约100nm的厚度，更优选地，约40nm的厚度。层间电介质材料30(例如，SiO2)可以沉积在材料28上，然后进行CMP工艺。在实施例中，层间电介质材料30可以是TEOS。
如图5所示，层间电介质材料30(在该图中未示出)和材料28经受平坦化工艺，例如，CMP或非选择性回蚀刻工艺。在实施例中，平坦化工艺将在层间电介质材料24的高度处停止在材料28上。以这种方式，作为示例，形成由氮化物和SiOC构成的T形牺牲帽32。然而，应该认识到，T形牺牲帽32可以是单一材料或多种材料，其中顶部材料对另外的下游化学耐蚀刻。如另外注意的，T形牺牲帽32将悬在侧壁18和CESL 22之上。
在图6中，在栅极结构12、12a之间去除层间电介质材料24以形成接触开口34。在实施例中，层间电介质材料24可以通过对层间电介质材料24的材料具有选择性的常规RIE工艺去除。例如，在层间电介质材料24上形成的抗蚀剂暴露于能量(光)以形成图案(开口)。使用选择性化学的蚀刻工艺(例如，反应离子蚀刻(RIE))将用于通过抗蚀剂的开口在层间电介质材料24中形成一个或多个接触开口34。然后可以通过常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂。
如图6所示，T形牺牲帽32，更具体地，T形牺牲帽32中的材料层28将在该蚀刻工艺期间保护侧壁18，使得栅极结构12的金属材料不会暴露。以这种方式，用于源极/漏极区域的接触材料将不会与栅极结构12中的金属材料短路。
如图7所示，在去除抗蚀剂之后，可以通过例如化学气相沉积(CVD)的任何常规沉积工艺在接触开口34内沉积接触材料36。在实施例中，接触材料36可以是在半导体制造方法中使用的任何接触材料，诸如钨、铝等。可以通过常规的化学机械抛光(CMP)工艺去除位于绝缘体材料表面上的任何残留材料。以这种方式，在后续的接触形成步骤中，用于源极/漏极区域的接触材料36将不会与栅极结构12中的金属材料短路。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种半导体结构，包括：
由导电栅极材料构成的栅极结构；
位于所述栅极结构上的、在所述导电栅极材料上方延伸的侧壁隔离物，
第一帽盖材料，其直接位于所述导电栅极材料上并且包括位于所述栅极结构上的所述侧壁隔离物之间的凹陷部分；以及
第二帽盖材料，其位于所述第一帽盖材料的所述凹陷部分内并且在所述栅极结构上的所述侧壁隔离物的顶表面之上延伸且与所述顶表面直接接触。
2.根据权利要求1所述的半导体结构，其中所述第二帽盖材料是T形的。
3.根据权利要求2所述的半导体结构，其中所述第二帽盖材料是顶部材料，所述顶部材料抵抗蚀刻化学并且悬在所述侧壁隔离物之上。
4.根据权利要求3所述的半导体结构，其中所述顶部材料是SiOC。
5.根据权利要求3所述的半导体结构，其中所述顶部材料悬在所述侧壁隔离物和位于所述侧壁隔离物上的蚀刻停止材料之上。
6.根据权利要求3所述的半导体结构，其中所述顶部材料是SiOC，以及所述第一帽盖材料是直接接触所述导电栅极材料且位于所述侧壁隔离物之间的底部材料并且是氮化物材料。
7.根据权利要求1所述的半导体结构，还包括与所述栅极结构邻近的接触，所述接触至少通过所述侧壁隔离物和悬在所述侧壁隔离物之上的所述第二帽盖材料而与所述栅极结构的所述导电栅极材料分离。
8.根据权利要求1所述的半导体结构，其中所述第二帽盖材料与层间电介质材料是共平面的。
9.一种半导体结构，包括：
由导电栅极材料构成的栅极结构；
位于所述栅极结构上并且具有在所述导电栅极材料的顶表面上方延伸的顶表面的侧壁隔离物；
位于所述侧壁隔离物上在与所述导电栅极材料相反的一侧的蚀刻停止层；以及
位于所述导电栅极材料上的T形双层帽，所述T形双层帽包括被定位在所述侧壁隔离物内并具有比所述侧壁隔离物的顶表面低的凹陷部分的第一帽盖材料和位于所述凹陷部分内并直接接触所述侧壁隔离物且悬在所述侧壁隔离物之上的第二帽盖材料。
10.根据权利要求9所述的半导体结构，其中所述第二帽盖材料是抵抗蚀刻化学的顶部材料。
11.根据权利要求10所述的半导体结构，其中所述顶部材料悬在所述侧壁隔离物和所述蚀刻停止层两者之上。
12.根据权利要求10所述的半导体结构，其中所述顶部材料由SiOC构成。
13.根据权利要求12所述的半导体结构，其中所述第一帽盖材料是所述T形双层帽中的底部材料并且位于所述侧壁隔离物之间且与所述导电栅极材料直接接触。
14.根据权利要求13所述的半导体结构，其中所述底部材料是氮化物。
15.根据权利要求9所述的半导体结构，还包括被形成为与所述栅极结构邻近的源极和漏极接触，所述源极和漏极接触至少通过所述侧壁隔离物和所述T形双层盖的顶部部分与所述导电栅极材料分离。
16.根据权利要求15所述的半导体结构，其中将所述导电栅极材料与所述源极和漏极接触分离的所述T形双层帽的所述顶部部分悬在所述侧壁隔离物之上。
17.根据权利要求15所述的半导体结构，其中所述源极和漏极接触通过所述侧壁隔离物的侧面上的所述蚀刻停止层与所述导电栅极材料分离。
18.一种用于制造半导体结构的方法，包括：
在衬底上形成由导电栅极材料构成的栅极结构；
在所述导电栅极材料上形成第一帽盖材料；
在所述栅极结构和所述第一帽盖材料上形成侧壁隔离物；
使所述第一帽盖材料凹陷到所述侧壁隔离物下方，以形成位于所述栅极结构上的所述侧壁隔离物之间的凹陷部分；以及
在所述第一帽盖材料上在所述凹陷部分内形成第二帽盖材料，所述第二帽盖材料悬在所述侧壁隔离物之上并且与所述侧壁隔离物的顶表面直接接触。
19.根据权利要求18所述的方法，其中所述第二帽盖材料被回蚀刻或被平坦化以悬在所述侧壁隔离物之上，从而形成由所述第一帽盖材料和所述第二帽盖材料构成的T形帽盖结构。
20.根据权利要求19所述的方法，其中所述第一帽盖材料是氮化物材料，以及所述第二帽盖材料是抗蚀刻材料，所述抗蚀刻材料是与所述氮化物材料不同的材料。
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