TW201933612A - 接觸結構 - Google Patents

接觸結構 Download PDF

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TW201933612A
TW201933612A TW107112104A TW107112104A TW201933612A TW 201933612 A TW201933612 A TW 201933612A TW 107112104 A TW107112104 A TW 107112104A TW 107112104 A TW107112104 A TW 107112104A TW 201933612 A TW201933612 A TW 201933612A
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Taiwan
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contact
item
sidewall
gate structure
source
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TW107112104A
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TWI729283B (zh
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舒傑輝
吳旭升
黃海茍
張宏光
劉佩
雷亞提斯 艾可納米克斯
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美商格芯（美國）集成電路科技有限公司
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    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract

本發明係關於半導體結構，尤其係關於主動閘極結構上方的接點及其製造方法。所述半導體結構包括：一主動閘極結構，其由位於側壁材料之間的導電材料組成；一上側壁材料，其在該側壁材料上方，該上側壁材料係不同於該側壁材料；及一接觸結構，其係電接觸該主動閘極結構之導電材料。該接觸結構係位於該側壁材料之間及該上側壁材料之間。

Description

接觸結構
本發明係關於半導體結構，尤其係關於接觸結構及其製造方法。
隨著半導體製程持續縮減(如縮小)尺寸，特徵之間所需的間隔(即是腳距)也變得更小。為此，在該等較小的技術節點中，由於關鍵尺寸(Critical dimension，CD)縮放和製程能力，以及用於製造這樣結構的該等材料，使得製造內連線的後段(Back end of the line，BEOL)和中段(Middle of the line，MOL)金屬化特徵變得越來越困難。
例如，為了製造用於主動閘極接點和源極/汲極接點的內連線結構，有必要去除該等閘極結構上方及與其緊鄰的介電材料。去除該介電材料係透過往往也會侵蝕該閘極結構之間隙層材料的蝕刻製程提供。亦即，用於該閘極結構之間隙層或側壁的低k值介電材料可在用於形成該等接觸開口的下游蝕刻製程中侵蝕掉。側壁材料之這種損失將暴露出該閘極結構之金屬材料，從而導致該閘極結構之金屬材料與用於形成該接點本身的金屬材料之間短路。
在本發明之態樣中，一種結構包含：一主動閘極結構，其由位於側壁材料之間的導電材料組成；一上側壁材料，其在該側壁材料上方，該上側壁材料係不同於該側壁材料；及一接觸結構，其係電接觸該主動閘極結構之導電材料，該接觸結構係位於該側壁材料之間及該上側壁材料之間。
在本發明之態樣中，一種結構包含：一下側壁材料，其形成在一基材上；一上側壁材料，其在該下側壁材料上方，該上側壁材料具有不同於該下側壁材料的一蝕刻選擇性；一主動閘極結構，其位於該下側壁材料之間；及一接觸結構，其係電接觸該主動閘極結構。該接觸結構從該上側壁材料之間延伸到該上側壁材料上方的一層間介電材料中。
在本發明之態樣中，一種方法包含：在一半導體基材上形成一閘極結構；緊鄰該閘極結構形成一接觸材料；使該接觸材料凹陷以形成一凹部空腔；在該凹部空腔之側壁上形成一間隙層；在該間隙層上方採用一介電材料填充該凹部空腔；及平坦化該介電材料。
本發明係關於半導體結構，尤其係關於接觸結構及其製造方法。更具體而言，本發明提供主動閘極上方的接觸結構，以及具體實施例中的源極/汲極區。有利地係，形成該等接觸結構之方法可避免源極/汲極接點與閘極金屬化特徵之間短路。此外，特別是在較小的技術節點中，本說明書所揭示的該等方法提供穩健的積體化方案，以產生主動閘極上方的接點。
在具體實施例中，該等接觸結構可透過在具有源極/汲極區的半導體基材上形成閘極結構製造。一源極/汲極接觸層係緊鄰凹陷以形成該等源極/汲極區上方的空腔結構的閘極結構形成。內部間隙層材料(例如，HfO2 )係形成在該等空腔結構之該等側壁上。該等空腔結構隨後係採用介電材料(例如，SiC)填充，接著平坦化該介電材料。接觸開口係形成在用於該源極/汲極區和主動閘極的介電材料中，接著係該等接觸開口內進行金屬填充製程。在具體實施例中，形成在該接觸開口之該等側壁上的內部間隙層材料(例如，HfO2 )將防止該等接點與該等主動閘極之金屬化之間短路。
本發明之該等結構可使用多種不同的工具以多種方式製造。不過，一般來說，該等方法和工具係用於形成具有微米和奈米等級尺寸的電路。用於製造本發明之結構的該等方法(即技術)，已從積體電路(Integrated circuit，IC)技術導入。例如，該等結構係建構在晶圓上，並且係在晶圓上方透過光微影成像製程圖案化的材料薄膜中實現。特別是，該結構之製造使用三種基本建構模塊：(i)在基材上沉積材料薄膜、(ii)透過光微影成像在該等薄膜上方施加圖案化光罩，及(iii)對該光罩選擇性蝕刻該等薄膜。
圖1除了其他特徵之外顯示根據本發明之態樣之具有源極/汲極區的主動閘極結構、及各個製程。特別是，結構10包括複數個形成在基材14上的閘極結構12。在具體實施例中，該等閘極結構12可為例如由金屬材料和介電材料組成的主動金屬閘極結構。在具體實施例中，依該等主動閘極結構之該等所需特性及/或性能而定，該金屬材料(例如，導電材料)可為鎢及其他功函數金屬。該介電材料可為高k值介電材料。在具體實施例中，例如，該高k值閘極介電材料可為基於鉿的介電體。在進一步具體實施例中，這種高k值介電體之範例包括但不限於：Al2 O3 、Ta2 O3 、TiO2 、La2 O3 、SrTiO3 、LaAlO3 、ZrO2 、Y2 O3 、Gd2 O3 以及包括其多層的組合。
在具體實施例中，該等閘極結構12可為形成在平面基材14上的替換閘極結構或由基材14組成的鰭狀結構。在具體實施例中，該替換閘極製程已習知，使得熟習該項技藝者無需進一步解說就能理解。基材14可為包括但不限於Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其他III/V族或II/VI族化合物半導體的任何半導體材料。
該(等)鰭狀結構可使用已知的側壁成像轉移(Sidewall imaging transfer，SIT)技術製造。在該SIT技術中，例如，半導體陰極金屬芯(mandrel)係使用習知沉積、微影和蝕刻製程形成在基材14上。光阻劑係形成在該半導體陰極金屬芯材料上，並且曝光以形成圖案(開口)。反應性離子蝕刻係穿越該等開口進行，以形成該等半導體陰極金屬芯。在具體實施例中，依該等鰭狀結構之間的該等所需尺寸而定，該等半導體陰極金屬芯可具有不同的寬度及/或間隔。間隙層係形成在該等半導體陰極金屬芯之側壁上，最好為不同於該等半導體陰極金屬芯的材料，並且係使用熟習該項技藝者已知的習知沉積製程形成。例如，該等間隙層可具有匹配該等鰭狀結構之該等尺寸的寬度。該等半導體陰極金屬芯係使用對半導體陰極金屬芯材料具有選擇性的習知蝕刻製程去除或剝離。然後在該等間隙層之間隔內進行蝕刻，以形成該等亞微影特徵。然後可剝離該等側壁間隙層。在具體實施例中，如本發明所考慮，該等寬鰭狀結構也可在此或其他圖案化製程期間或透過其他習知圖案化製程形成。
請再參考圖1，該等主動閘極結構12包括一在所述金屬材料上方的覆蓋材料16。覆蓋材料16可為氮化物材料，例如使用化學氣相沉積(Chemical vapor deposition，CVD)等習知沉積製程沉積，接著係用於替換閘極製程的平坦化製程。在使用閘極第一製程的具體實施例中，該沉積製程接著可為圖案化製程，以圖案化該閘極材料和該覆蓋材料。在具體實施例中，覆蓋材料16可為包括SiN的其他材料或可耐受後續蝕刻製程的其他材料。
側壁或間隙層18係在該等主動閘極結構12和覆蓋材料16之該等側面上提供。該等間隙層18可具有約5 nm至約10 nm之厚度，以及在該金屬材料(例如，閘極結構12之導電材料)上方延伸的高度。該等間隙層18可由SiOCN、SiOC、SiCN等任何低k值介電材料組成。在閘極最後具體實施例(例如，替換閘極製程)中，該等間隙層18係在主動閘極結構之前，透過習知沉積製程(如CVD)形成。該等側壁可使用習知沉積製程沉積，接著係圖案化製程，即等向性蝕刻製程。
源極與汲極區20係緊鄰該等主動閘極結構12形成。在具體實施例中，該等源極與汲極區20可為採用習知離子植入製程或摻雜製程形成的平面或昇起式磊晶半導體區。矽化物接點22 (區域)可形成在該等源極與汲極區20上。如熟習該項技藝者應可理解，該矽化物製程開始於在完全形成和圖案化的半導體裝置(例如，已摻雜或離子植入的源極與汲極區和各個裝置)上方沉積例如鎳、鈷或鈦的薄過渡金屬層。在沉積該材料之後，加熱該結構使得該過渡金屬與該半導體裝置之該等主動區(例如，源極、汲極、閘極接觸區)中所暴露出的矽(或如本說明書所說明的其他半導體材料)起反應，從而形成低電阻過渡金屬矽化物。在該反應後，任何殘留的過渡金屬皆係透過化學蝕刻去除，從而在該裝置之該等主動區中留下矽化物接點22。
在具體實施例中，層間介電材料24係在該等閘極結構12之間提供。層間介電材料24可為可經歷例如化學機械拋光(Chemical mechanical polishing，CMP)的平坦化製程的四乙氧基矽烷(TEOS)。淺溝槽隔離(STI)結構26也可緊鄰該等鰭狀結構(例如，在該等鰭狀結構之端部)提供。該等STI結構26係使用技藝中已習知的習知微影、蝕刻和沉積製程形成在基材14中。在具體實施例中，該等STI結構26可端對端隔開該等鰭狀結構。
在圖2中，去除層間介電材料24以暴露出該等源極與汲極區20之矽化物接點22，從而導致空腔結構27。在具體實施例中，層間介電材料24可透過使用光阻堆疊28的習知蝕刻製程去除。例如，形成在圖1中所定義的該等結構上方的光阻堆疊28係暴露於能量(光)，以形成圖案(開口)。將使用對層間介電材料24具有選擇性化學性質的例如反應性離子蝕刻(Reactive ion etching，RIE)的蝕刻製程，透過穿越光阻堆疊28之該等開口去除該絕緣材料(例如，層間介電材料24)形成空腔27。該蝕刻製程將暴露出該等源極與汲極區20之矽化物接點22。
在圖3中，該光阻堆疊係透過習知氧氣灰化製程或其他已知剝離劑去除，接著係導電填充製程。在具體實施例中，該導電填充製程包含使用例如化學氣相沉積(CVD)或電鍍製程的習知沉積製程，在空腔結構27中沉積導電材料30。在具體實施例中，導電材料30將自動對準，並且直接接觸該等源極與汲極區20之矽化物接點22。
導電材料30可為半導體製程中所使用的任何內連線材料。例如，導電材料30可為鎢材料；儘管本說明書也考慮鈷、鋁等其他材料。包括該結構之上部分的任何殘留材料可透過習知化學機械拋光(CMP)製程去除(例如，平坦化)。
如圖4所示，導電材料30和該等間隙層18之各部分為凹陷，以形成擴大空腔結構32。如圖4所示，擴大空腔結構32之下部分將維持在該等閘極結構12 (如該等閘極結構12之導電材料)之高度上方。更具體而言，導電材料30和該等間隙層18之各部分將凹陷到覆蓋材料16之範圍內的高度。在具體實施例中，導電材料30可透過異向性蝕刻去除，接著等向性蝕刻該等間隙層18 (例如，間隙層材料)。
圖5顯示內裡例如擴大空腔結構的空腔結構32的側壁材料34 (例如，內部間隙層材料)。在具體實施例中，側壁材料34可為高k值介電材料(例如，HfO2 或其他高k值介電體)。或者，側壁材料34可為例如TiO2 或Al2 O3 的金屬氧化物。在任何這些情境下，熟習該項技藝者應明白，側壁材料34將具有對例如SiN和SiO2 的低k值材料的蝕刻選擇性。由於該等間隙層18和覆蓋材料16係由這種低k值材料組成，因此使用側壁材料34 (例如，HfO2 )可為如本說明書所說明的下游接觸形成製程提供優勢。
在具體實施例中，側壁材料34可透過例如CVD或原子層沉積(Atomic layer deposition，ALD)的習知沉積製程覆蓋沉積成約5 nm至約10 nm之厚度；儘管本說明書也考慮其他厚度。在具體實施例中，側壁材料34之厚度應實質等於該等側壁間隙層18之厚度。在該沉積製程後，側壁材料34將經歷各向異性蝕刻製程，使得該側壁材料留在該等空腔結構32之該等側壁上。值得注意的是，由於該凹部深度在蝕刻側壁材料34期間沒有變化，因此側壁材料34提供對底層導電材料30的蝕刻選擇性。
圖6顯示形成在側壁材料34上的絕緣材料36，其進一步填充該等空腔結構32之剩餘部分。在具體實施例中，絕緣材料36為SiC材料；儘管本說明書考慮其他低k值介電材料。例如，絕緣材料36可為例如SiCN或SiOC。如此，高k值或金屬氧化物側壁材料34與絕緣材料36之間存在蝕刻選擇性。在具體實施例中，絕緣材料36可透過習知CVD製程沉積，接著係平坦化製程。在具體實施例中，該平坦化製程可去除可能已在圖5中所說明的該等蝕刻製程期間可能已損壞的該等間隙層18之任何側壁材料。
圖7A和圖7B分別顯示用於該等主動閘極結構12和該等源極/汲極區20的接觸開口38a、38b。在具體實施例中，在形成該等接觸開口38a、38b之前，一層間介電材料40係沉積在圖6所示材料34和絕緣材料36以及該結構之其他暴露表面上方。在具體實施例中，該等接觸開口38a、38b隨後係透過習知微影和蝕刻製程形成。在具體實施例中，接觸開口38a係形成在該等間隙層18之上部表面下方，並且將暴露出該等閘極結構12之金屬材料(圖7B)；然而，接觸開口38b將暴露出將形成到該等源極/汲極區20的接點的導電材料30 (圖7A)。
應明白，在形成接觸開口38a期間，將去除覆蓋材料16，從而暴露出閘極結構12之金屬材料。而且，由於間隙層18係在該等閘極結構12之金屬材料上方，因此該金屬材料現將在該等間隙層18下方，並且在側壁材料34下方。如此，該等間隙層18和在側壁材料34下方兩者將防止該接觸材料與用於該等源極/汲極區20的接觸材料之短路。
熟習該項技藝者應明白，側壁材料34 (例如，高k值介電材料或金屬氧化物)將對絕緣材料36 (及該等間隙層18之側壁材料)具有蝕刻選擇性。因此，材料34將在此蝕刻製程期間保護該等間隙層18，使得該等閘極結構12之金屬材料不會在形成源極/汲極接觸開口38b時暴露出。如所提及，熟習該項技藝者現應理解，沉積在該等源極/汲極接觸開口38b中的接觸材料不會與該等閘極結構12之金屬材料短路。同樣地，沉積在用於該等主動閘極結構12的該等開口38a中的接觸材料不會與用於該等源極/汲極區20的接觸材料之金屬材料短路。因此，使用該材料將防止接點與閘極短路。
圖8A和圖8B顯示填充該等接觸開口38a、38b的接觸金屬材料42。在具體實施例中，接觸金屬材料42可為鎢或其他接觸材料(如鋁等)。接觸金屬材料42可使用CVD、原子層沉積(ALD)或電鍍製程等習知沉積製程，沉積在該等接觸開口38a、38b內。如此，接觸金屬材料42將形成位於該等間隙層18之側壁材料與上側壁材料34之間，與該等主動閘極結構12直接電接觸的接觸結構。同樣地，接觸金屬材料42將位於上側壁材料34之間，與源極/汲極區20之矽化物22直接電接觸。作為範例，在該沉積製程後，任何殘留金屬材料皆可使用CMP製程去除。
因此，如現應理解，圖8A顯示藉由導電材料30和矽化物部分22與該等源極與汲極區20接觸的接觸材料42；然而，在圖8B中，接觸材料42係接觸該等閘極結構12。在這兩種表示中，接觸材料42皆係在側壁材料18與上側壁材料34兩者之間。另一方面，(i)該等源極與汲極區20、導電材料30和矽化物部分22係在側壁材料18之間，及(ii)閘極結構12係在側壁材料18之間。
如前述的(該等)方法係用於製造積體電路晶片。該等所得到的積體電路晶片可由該製造者以原始晶圓形式(即作為具有多個未封裝晶片的單晶圓)、作為裸晶粒或以封裝形式流通。在該後者情況下，該晶片係以單晶片封裝(例如具有貼附於母板或其他更高層載體的引線的塑料載體)或以多晶片封裝(例如具有表面內連線或掩埋式內連線任一者或兩者的陶瓷載體)進行封固。在任何情況下，該晶片隨後與其他晶片、分立電路元件及/或其他信號處理裝置整合成為(a)中間產品(例如母板)或(b)最終產品之一部分。該最終產品可為包括積體電路晶片的任何產品，範圍從玩具和其他低端應用到具有顯示器、鍵盤或其他輸入裝置和中央處理器的進階電腦產品皆包括。
本發明之該等各種具體實施例之該等說明已為了例示之目的而進行描述，但不欲為全面性或限於所揭示的該等具體實施例。許多修飾例和變化例對熟習該項技藝者而言應為顯而易見，而不悖離該等所說明的具體實施例之範疇與精神。本說明書所使用的術語係選擇以最佳解說該等具體實施例之該等原理、對市場中所發現的技術的實際應用或技術改進，或讓其他熟習該項技藝者能理解本說明書所揭示的該等具體實施例。
10‧‧‧結構
12‧‧‧閘極結構
14‧‧‧基材
16‧‧‧覆蓋材料
18‧‧‧側壁間隙層
20‧‧‧源極/汲極區
22‧‧‧矽化物接點
24、40‧‧‧層間介電材料
26‧‧‧淺溝槽隔離(STI)結構
27‧‧‧空腔
28‧‧‧光阻堆疊
30‧‧‧導電材料
32‧‧‧擴大空腔結構
34‧‧‧側壁材料
36‧‧‧絕緣材料
38a‧‧‧接觸開口
38b‧‧‧源極/汲極接觸開口
42‧‧‧接觸材料
在接下來的實施方式中，藉由本發明之示例性具體實施例之非限制性範例，參考該等所提及複數個圖式說明本發明。
圖1除了其他特徵之外顯示根據本發明之態樣之具有源極/汲極區的主動閘極結構、及各個製程。
圖2除了其他特徵之外顯示根據本發明之態樣之相鄰主動閘極結構之間的凹陷絕緣材料(例如，形成一空腔結構)、及各個製程。
圖3除了其他特徵之外顯示根據本發明之態樣之該空腔結構內的導電填充材料、及各個製程。
圖4除了其他特徵之外顯示根據本發明之態樣之形成擴大空腔結構的導電填充材料之凹部、及各個製程。
圖5除了其他特徵之外顯示根據本發明之態樣之內裡圖4所示空腔的側壁材料、及各個製程。
圖6除了其他特徵之外顯示根據本發明之態樣之填充該擴大空腔結構的絕緣材料、及各個製程。
圖7A和圖7B除了其他特徵之外顯示根據本發明之態樣之用於該主動閘極結構和該等源極/汲極區的接觸開口、及各個製程。
圖8A和圖8B除了其他特徵之外顯示根據本發明之態樣之填充該等接觸開口的接觸材料、及各個製程。

Claims (20)

  1. 一種結構包含： 一主動閘極結構，其由位於側壁材料之間的導電材料組成； 一上側壁材料，其在該側壁材料上方，該上側壁材料係不同於該側壁材料；及 一接觸結構，其係電接觸該主動閘極結構之導電材料，該接觸結構係位於該側壁材料之間及該上側壁材料之間。
  2. 如申請專利範圍第1項所述之結構，其中該側壁材料係一低k值介電材料，並且該上側壁材料具有不同於該低k值介電材料的一蝕刻選擇性。
  3. 如申請專利範圍第2項所述之結構，其中該上側壁材料係一高k值介電材料。
  4. 如申請專利範圍第2項所述之結構，其中該上側壁材料係一金屬氧化材料。
  5. 如申請專利範圍第2項所述之結構，其中該上側壁材料將用於該主動閘極結構的接觸結構與該主動閘極結構之一源極/汲極區之接觸結構隔開。
  6. 如申請專利範圍第5項所述之結構，其中該源極/汲極區之接觸結構之一下部分係位於該側壁材料之間，並且該源極/汲極區之接觸結構之一上部分係位於該上側壁材料之間。
  7. 如申請專利範圍第6項所述之結構，其中該源極/汲極區之接觸結構係透過該上側壁材料與該主動閘極結構之導電材料隔開。
  8. 如申請專利範圍第7項所述之結構，其中該上側壁材料係定位和構造成防止該源極/汲極區之接觸材料與該主動閘極結構之導電材料之間短路。
  9. 一種結構包含： 一下側壁材料，其形成在一基材上； 一上側壁材料，其在該下側壁材料上方，該上側壁材料具有不同於該下側壁材料的一蝕刻選擇性； 一主動閘極結構，其位於該下側壁材料之間；及 一接觸結構，其係電接觸該主動閘極結構，該接觸結構從該上側壁材料之間延伸到該上側壁材料上方的一層間介電材料中。
  10. 如申請專利範圍第9項所述之結構，其中該下側壁材料係一低k值介電材料，並且該上側壁材料係一高k值介電材料。
  11. 如申請專利範圍第9項所述之結構，其中該下側壁材料係一低k值介電材料，並且該上側壁材料係一金屬氧化材料。
  12. 如申請專利範圍第9項所述之結構，其中該上側壁材料將用於該主動閘極結構的接觸結構與該主動閘極結構之一源極/汲極區之接觸結構隔開。
  13. 如申請專利範圍第12項所述之結構，其中： 該源極/汲極區之接觸結構之一下部分係位於該下側壁材料之間，並且該源極/汲極區之接觸結構之一上部分係位於該上側壁材料之間且延伸到該層間介電材料中；及 該源極/汲極區之接觸結構係透過該上側壁材料與該主動閘極結構隔開。
  14. 如申請專利範圍第13項所述之結構，其中該上側壁材料係定位和構造成防止該源極/汲極區之接觸材料與該主動閘極結構之間短路。
  15. 一種方法，包含： 在一半導體基材上形成一閘極結構； 緊鄰該閘極結構形成一接觸材料； 使該接觸材料凹陷以形成一凹部空腔； 在該凹部空腔之側壁上形成一間隙層； 在該間隙層上方採用一介電材料填充該凹部空腔；及 平坦化該介電材料。
  16. 如申請專利範圍第15項所述之方法，更包含去除該介電材料以在該閘極結構之源極/汲極區上方形成一空腔，及在該凹部空腔中沉積導電材料。
  17. 如申請專利範圍第15項所述之方法，更包含去除該介電材料以在該閘極結構上方形成一空腔，及在與該閘極結構上方直接電接觸的空腔中沉積導電材料。
  18. 如申請專利範圍第17項所述之方法，其中該介電材料和該間隙層具有不同的蝕刻選擇性。
  19. 如申請專利範圍第18項所述之方法，其中該介電材料係SiC，並且該內部間隙層係HfO2 。
  20. 如申請專利範圍第17項所述之方法，其中該間隙層係在該閘極結構之一主動區上方，並且將該空腔中的導電材料與該凹部空腔隔開。
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