TWI783606B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

Info

Publication number
TWI783606B
TWI783606B TW110128302A TW110128302A TWI783606B TW I783606 B TWI783606 B TW I783606B TW 110128302 A TW110128302 A TW 110128302A TW 110128302 A TW110128302 A TW 110128302A TW I783606 B TWI783606 B TW I783606B
Authority
TW
Taiwan
Prior art keywords
isolation
fin
layer
dielectric
base
Prior art date
Application number
TW110128302A
Other languages
English (en)
Other versions
TW202217977A (zh
Inventor
鄭嶸健
江國誠
朱熙甯
陳冠霖
王志豪
程冠倫
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202217977A publication Critical patent/TW202217977A/zh
Application granted granted Critical
Publication of TWI783606B publication Critical patent/TWI783606B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本文揭露了半導體結構及其製造方法。根據本揭露，示例性的半導體結構包括具有p型井(p-type well)或n型井(n-type well)的基板；第一基部在p型井上方；第二基部在n型井上方；第一多個通道構件在第一基部上方；第二多個通道構件在第二基部上方；隔離部件，設置在第一基部和第二基部之間；以及基板中的深隔離結構，設置在隔離部件下方。

Description

半導體裝置及其形成方法
本發明實施例是關於半導體裝置，特別是關於具有隔離結構之半導體裝置及其製造方法。
半導體積體電路(integrated circuit,IC)工業經歷了指數型成長。IC材料與設計的技術進步已產出數代的IC，其中每一代都比上一代具有更小且更複雜的電路。在IC的發展過程，功能密度(即每單位晶片區域互連裝置的數量)已大量增加，而幾何大小(即可以使用製程產出的最小組件(或線))已縮小。這種微縮化製程一般藉由提高生產效率與降低相關成本以提供效益。這種微縮化也增加了IC製程與製造的複雜性。
舉例來說，隨著積體電路(integrated circuit,IC)技術朝著更小的技術節點發展，已經引入了多閘極金屬氧化物半導體場效應電晶體(multi-gate metal-oxide-semiconductor field effect transistor,multi-gate MOSFET)(或多閘極裝置multi-gate devices)，藉由以下方式改善閘極控制：增加閘極通道耦合(gate-channel coupling)、降低關閉狀態電流(off-state current)以及降低短通道效應(short-channel effects,SCEs)。多閘極裝置通常是指具有設置在通道區 域的一側以上的閘極結構或其一部分的裝置。鰭式場效應電晶體(fin-like field effect transistors,FinFETs)和多橋通道(multi-bridge-channel,MBC)電晶體是多閘極裝置的示例，這些裝置已成為高性能和低漏電流(leakage)應用的流行和有希望的(promising)候選。鰭式場效應電晶體(FinFET)具有超過一側被閘極包繞抬升的(elevated)通道(例如，閘極包繞從基板延伸半導體材料的「鰭」的頂部和側壁)。多橋通道(MBC)電晶體的閘極結構可以延伸，部分或全部圍繞通道區域，以提供對兩側或更多側通道區域的接觸。由於多橋通道(MBC)電晶體的閘極結構環繞通道區域，因此MBC電晶體也可以稱為環繞閘極電晶體(surrounding gate transistor,SGT)或全繞式閘極(gate-all-around,GAA)電晶體。
儘管具有片狀通道構件的多橋通道(MBC)電晶體通常提供優異的閘極控制和驅動電流，但是它們較寬的片狀通道構件會增加裝置寬度。這種增加裝置寬度可能使它們在高封裝密度應用如記憶體應用的吸引力降低。提高多橋通道(MBC)電晶體封裝密度的措施，在形成隔離結構以隔離不同裝置區域的過程中可能面臨挑戰。儘管現有的半導體裝置已經大致能滿足其預期目的，但並非在所有方面都令人滿意。
本發明實施例提供一種半導體裝置包括：基板，包括p型井或n型井；第一基部，在p型井上方；第二基部，在n型井上方；多個第一通道構件，在第一基部上方；多個第二通道構件，在第二基部上方；隔離部件，設置在第一基部和第二基部之間；以及深隔離結構，設置在隔離部件下方的該基板中。
本發明實施例提供一種半導體裝置包括：基板，包括p型井或n型 井；第一基部，在p型井上方；第二基部，在n型井上方；第一n型磊晶部件，在第一基部上方；第一p型磊晶部件，在第二基部上方；第一隔離部件，設置在第一基部和第二基部之間；以及深隔離結構，設置在第一隔離部件正下方的該基板中。
本發明實施例提供一種半導體裝置的形成方法，包括：接收工件，工件包括第一鰭狀結構，在基板的p型井區域上方；以及第二鰭狀結構，在基板的n型井區域上方，第一鰭狀結構和第二鰭狀結構被接面溝槽間隔開；將接面溝槽進一步延伸到基板中以形成深凹穴；形成深隔離部件在深凹穴中，以及隔離部件在接面溝槽中；以及形成介電鰭在隔離部件上，使得介電鰭設置在第一鰭狀結構和第二鰭狀結構之間。
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128:方框
200:工件、裝置
202:基板
202P:p型井區域
202N:n型井區域
204,250:堆疊
206:犧牲層
206T:頂犧牲層
208:通道層
210,246,247:遮罩層
211:鰭狀結構
211B:基部
211T:頂部
212,212J,222,222J,266:溝槽
214:襯層
216:凹穴
218:隔離部件
218J:接面隔離部件
220:深隔離部件
224:第一層
226:第二層
230,230J:介電鰭
232:被覆層
234:第三層
236:第四層
240:帽層
242:介電層
244:電極
248:遮罩
252:間隔物
254:凹槽、溝槽
258:間隔部件
260N:n型源極/汲極部件
260P:p型源極/汲極部件
262:蝕刻停止層
264:介電層
267:界面層
268:介電層
269:電極層
270,270-1,270-2,270-3,270-4:閘極結構
272,274:蓋層
276:閘極切割部件
2020:井接面
2080:通道構件
302,304,306,308:多橋通道電晶體
H1,H2:高度
S1,S2:間隔
W1,W2,W3:寬度
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可任意地放大或縮小單元的尺寸，以清楚地表現出本發明實施例的特徵。
第1圖根據本揭露的一個或多個面向，繪示出形成半導體裝置的方法的流程圖。
第2-23圖根據本揭露的一個或多個面向，繪示出在第1圖的方法中各個製造階段期間的工件的局部透視圖或剖面圖。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及/或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
另外，當使用「約」、「近似」和類似的用語描述數字或數字範圍時，所屬技術領域中具有通常知識者可以理解，考慮製造中固有產生的變異，此類用語用於涵蓋在合理範圍內的數字，合理範圍內包含所描述的數字。例如，數字的數量或範圍涵蓋了包括所描述數字的合理範圍，例如在所描述數字的+/- 10%之內，此合理範圍是基於製造相關部件已知的製造公差，而該部件具有與該數字相關聯的特徵。例如所屬技術領域中具有通常知識者已知與沉積材料層相關的製造公差為+/- 15%，材料層為「約5nm」涵蓋4.25nm至5.75nm的尺寸範圍。此外，本發明實施例可能在各種範例中重複元件符號以及/或字母。如此重 複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
本揭露大致上關於用於減少塊體漏電流(bulk leakage)的隔離結構，特別是關於設置在井接面上的深隔離結構。
為了改善驅動電流以滿足設計需求，多橋通道(MBC)電晶體可以包括薄而寬的奈米級通道構件。這樣的多橋通道(MBC)電晶體也可以被稱為奈米片電晶體。儘管奈米片電晶體能夠提供令人滿意的驅動電流和通道控制，但它們更寬的奈米片通道構件可能使進一步單元微縮化成為挑戰。在一些示例性的結構中，可以實現魚骨結構(fish-bone structures)或叉片結構(fork-sheet structures)以減少單元尺寸。在魚骨結構(fish-bone structures)或叉片結構(fork-sheet structures)中，通道構件的相鄰堆疊可以被介電鰭(dielectric fins)(或混合鰭，hybrid fins)隔開。由於通道構件的堆疊的一端與介電鰭接觸，因此包繞在通道構件的堆疊周圍的閘極結構不在通道構件和介電鰭之間延伸。每個介電鰭設置在隔離部件上，例如淺溝槽隔離(shallow trench isolation,STI)部件。淺溝槽隔離(shallow trench isolation,STI)部件也可以設置在n型井和p型井之間的接面上以降低塊體漏電流(bulk leakage)。
本揭露提供了一種深隔離結構，該深隔離結構設置在n型裝置下方的p型井和p型裝置下方的n型井之間的井接面。在一些實施例中，深隔離結構的形成包括沿著井接面的凹口的形成。凹口可以底切(undercut)n型裝置和p型裝置的主動區域。在至少一些實施例中，n型裝置和p型裝置可以是魚骨式(fish-bone)或叉片式(fork-sheet)電晶體。深度隔離結構可以更好地阻擋n型井和p型井之間的塊體漏電流(bulk leakage)路徑。
現在將參考附圖，更詳細地描述本揭露的各個面向。第1圖繪示出半導體裝置的形成方法100的流程圖。方法100僅為示例，且不意圖將本揭露作出除了方法100中明確記載之外的限制。
可以在方法100之前、期間以及/或之後，可提供額外的步驟，且對於所述方法附加的實施例，可以替換、刪去或移動所描述的一些步驟。為了簡單起見，本文沒有詳細描述所有步驟。下面結合第2-23圖描述方法100。第2-23圖根據方法100的實施例，繪示出不同製造階段的工件200的局部剖面圖。因為半導體裝置將由工件200形成，所以根據上下文需要，工件200可以被稱為半導體裝置200。儘管在圖中繪示出包括魚骨式(fish-bone)或叉片式(fork-sheet)電晶體的實施例，但本揭露不限於此，且可以應用於其他多閘極裝置例如多橋通道(MBC)電晶體或鰭式場效應電晶體(FinFET)。遍及第2-23圖中，X方向、Y方向和Z方向彼此垂直且被一致地使用。另外，在本揭露全文中，相似的元件符號用於代表相似的部件。
參照第1和2圖。方法100包括方框102，在方框102中接收工件200。如第2圖所示，工件200包括基板202和設置在基板202上的堆疊204。在一實施例中，基板202可以為矽(Si)基板。在一些其他實施例中，基板202可以包括其他半導體材料，例如鍺(Ge)、矽鍺(SiGe)或III-V族半導體材料。示例III-V半導體材料可以包括砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)、磷化砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、磷化銦鎵鎵(GaInP)和砷化銦鎵(InGaAs)。基板202可以包括多個n型井區域和多個p型井區域。在所描繪的實施例中，基板202包括p型井區域202P(或p井區202P)和n型井區域202N(或n井區202N)。如第2圖所示，p井區202P和n井 區202N沿著井接面結2020彼此介面。p井區202P可以摻雜有p型摻雜劑(即硼(B))，n井區202N可以摻雜有n型摻雜劑(即磷(P)或砷(As))。p井區202P和n井區202N可以使用離子佈植或熱擴散來形成。
仍然參考第2圖，堆疊204可以包括被多個犧牲層206交錯的多個通道層208。通道層208和犧牲層206可以具有不同的半導體組成。在一些實施方式中，通道層208由矽(Si)形成，且犧牲層206由矽鍺(SiGe)形成。在這些實施方式中，犧牲層206中額外的鍺含量允許犧牲層206選擇性去除或凹陷，而不會對通道層208造成實質性損害。在第2圖所示的一些實施例中，工件200還包括設置在堆疊204上的頂犧牲層206T。頂犧牲層206T比其他犧牲層206厚，在製造過程中，起到保護堆疊204不受損壞的作用。頂犧牲層206T、犧牲層206和通道層208可以使用磊晶製程來沉積。堆疊204可以藉由磊晶沉積使用化學氣相沉積(CVD)沉積技術(例如，氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空CVD(ultra-high vacuum CVD,UHV-CVD))、分子束磊晶(molecular beam epitaxy,MBE)及/或其他合適的製程。犧牲層206和通道層208一個接一個地交替沉積，以形成堆疊204。第2圖繪示出三(3)層的犧牲層206和三(3)層的通道層208被交替地且垂直地設置，這僅出於示例性的目的，且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。層的數目取決於半導體裝置200期望的通道構件的數目。在一些實施例中，通道層208的數目在1至6之間。
參照第1和3圖，方法100包括方框104，在方框104中，圖案化堆疊204和基板202以形成被溝槽212或接面溝槽212J分開的鰭狀結構211。為了圖案化堆疊204和基板202，沉積第一硬遮罩層210在頂犧牲層206T上方。然後，圖案化第一硬遮罩層210作為蝕刻遮罩，用來圖案化頂犧牲層206、堆疊204和一部分 的基板202。在一些實施例中，沉積第一硬遮罩層210可以使用化學氣相沉積(CVD)、電漿化學氣相沉積(plasma-enhanced CVD,PECVD)，原子層沉積(atomic layer deposition,ALD)，電漿增強原子層沉積(plasma-enhanced ALD,PEALD)或合適的沉積方法。第一硬遮罩層210可以是單層或多層。當第一硬遮罩層210是多層時，第一硬遮罩層210可以包括墊氧化物和墊氮化物層。在替代實施例中，第一硬遮罩層210可以包括矽(Si)。圖案化鰭狀結構211可以使用適當的製程，包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般來說，雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程將微影和自對準(self-aligned)製程相結合，允許創造出例如間距(pitch)小於使用單個直接微影製程可獲得的。舉例來說，在一個實施例中，使用微影製程圖案化形成在基板上方的材料層。使用自對準製程形成墊片在圖案化材料層旁邊。然後去除材料層，接著可以使用剩餘的間隔物或心軸來圖案化第一硬遮罩層210，然後可以將圖案化的第一硬遮罩層210作為蝕刻遮罩來蝕刻堆疊204和基板202，形成鰭狀結構211。蝕刻製程可以包括乾蝕刻、濕蝕刻、反應離子蝕刻(reactive ion etching,RIE)及/或其他合適的製程。
如第3圖所示，每個鰭狀結構211包括由基板202的一部分形成的基部211B和由堆疊204形成的頂部211T。頂部211T設置在基部211B上方。鰭狀結構211從基板202沿著Y方向縱向延伸，且沿著Z方向垂直地延伸。沿著X方向，鰭狀結構211被溝槽212和接面溝槽212J分開。相較於溝槽212，接面溝槽212J設置在井接面2020上且沿著井接面2020。在第3圖所示的一些實施例中，接面溝槽212J寬於沿X方向的溝槽212，提供更大的間距。如第3圖所示，接面溝槽212J定義第一間隔S1，溝槽212定義第二間隔S2。第一間隔S1大於第二間隔S2。在一些 情況下，第一間隔S1在約20nm至約30nm之間，第二間隔S2在約10nm至約20nm之間。較寬的接面溝槽212J允許井接面2020的任一側上的主動區域，例如鰭狀結構211，被進一步間隔開以減少塊體漏電流(bulk leakage)。
參照第1和4圖。方法100包括方框106，在方框106中，形成襯層214沿著鰭狀結構211的側壁。襯層214用於保護鰭狀結構211的側壁在方框108(將在之後描述)期間不被損壞。在形成襯層214的一示例製程中，保形地沉積介電材料在工件200上方，包括在溝槽212和接面溝槽212J上，藉由原子層沉積(ALD)、化學氣相沉積(CVD)或低壓化學氣相沉積(LPCVD)。用於襯層214的介電材料可以包括氧化矽、氮化矽、氧氮化矽(silicon oxynitride)、氧碳化矽(silicon oxycarbide)、碳氮化矽(silicon carbonitride)、氧碳氮化矽(silicon oxycarbonitride)或其組合。然後，非等向性地回蝕沉積的介電材料，形成襯層214。在一些實施例中，回蝕可以包括的乾蝕刻製程，使用一種或多種含氟氣體例如四氟化碳(CF4)、六氟化硫(SF6)或三氟化氮(NF3)。如第4圖所示，由於接面溝槽212J中的第一間隔S1較大，所以接面溝槽212J的底表面上的介電材料被去除以露出基板202。即為，襯層214僅襯在接面溝槽212J的側壁上。較小的溝槽212的第二間隔S2，防止介電材料從其底表面去除。
參照第1和5圖，方法100包括方框108，在方框108中，接面溝槽212J延伸到基板202中以形成深凹穴(deep pocket)216。由於溝槽212被襯層214保護，接面溝槽212J露出基板202的底表面，因此方框108的操作向下蝕刻接面溝槽212J露出的基板202。蝕刻露出的基板202延伸接面溝槽212J向下到基板202中，形成深凹穴216。深凹穴216也可以被稱為凹口(notch)。方框108的蝕刻可以使用趨於非等向性的乾蝕刻製程或趨於等向性的濕蝕刻製程來執行。一示例 性的選擇性濕蝕刻製程可以包括使用乙二胺鄰苯二酚(EDP)、氫氧化四甲基銨(TMAH)、硝酸(HNO3)、氫氟酸(HF)、氨(NH3)、氟化銨(NH4F)或合適的濕蝕刻劑。一示例性的選擇性乾蝕刻製程可以包括六氟化硫(SF6)、氫(H2)、氨(NH3)、氟化氫(HF)、四氟化碳(CF4)、氬(Ar)或其混合物。在第5圖所示的一些實施例中，在方框108的蝕刻製程不是完全非等向性的，且深凹穴216底切(undercut)襯層214。因此，深凹穴216的形狀不同於接面溝槽212J的形狀。在一些情況下，深凹穴216最寬部分的寬度大於接面溝槽212J(包括襯層214)的寬度。深凹穴216設置在溝槽212或在形成深凹穴216之前接面溝槽212J的底表面水平的下方。因此，深凹穴216設置在基板202中較深的位置。
參照第1、6和7圖，方法100包括方框110，在方框110中，形成隔離部件在深凹穴216和溝槽212中。在方框110形成的隔離部件可以包括溝槽212中的隔離部件218、接面溝槽212J中的接面隔離部件218J和深凹穴216中的深隔離部件220。隔離部件218和接面隔離部件218J可以統稱為淺溝槽隔離(shallow trench isolation,STI)。在形成這些隔離部件的一示例製程中，沉積介電材料在工件200上，並用介電材料填充溝槽212、深凹穴216和接面溝槽212J。在一些實施例中，介電材料可以包括氧化矽、氮化矽、氧氮化矽(silicon oxynitride)、氧碳化矽(silicon oxycarbide)、碳氮化矽(silicon carbonitride)、氧碳氮化矽(silicon oxycarbonitride)或其組合。在各種示例中，在方框110處，沉積介電材料可以藉由化學氣相沉積(CVD)製程、次大氣壓化學氣相沉積(subatmospheric CVD,SACVD)製程、流動式化學氣相沉積(flowable CVD,FCVD)製程、原子層沉積(ALD)製程、旋轉塗佈(spin-on coating)及/或其他合適的製程。然後，薄化且平坦化沉積的介電材料，例如藉由化學機械拋光(chemical mechanical polishing,CMP)製程，直到露出頂犧牲層206T，如第6圖所示。在一些實施例中，襯層214和隔離部件的介電材料的成分可能相似，其邊界用虛線標記。為了便於說明，在隨後的附圖中可以省略襯層214和隔離部件之間的邊界。參照第7圖，進一步凹蝕平坦化的介電材料和襯層214，藉由乾蝕刻製程、濕蝕刻製程及/或其組合，形成隔離部件218、接面隔離部件218J以及深隔離部件220的最終結構。如第7圖所示，鰭狀結構211的頂部211T上升到隔離部件218或接面隔離部件218J的上方，而基部211B或其大部分被隔離部件218或接面隔離部件218J包圍。如第7圖所示，深隔離部件220設置在基部211B的水平下方，且可以底切(undercut)與井接面2020相鄰的基部211B。即為，深隔離部件的一部分可以在相鄰的基部211B下方延伸。在形成隔離部件218和接面隔離部件218J之後，頂部211T被介電鰭溝槽222和接面介電鰭溝槽222J分開。接面介電鰭溝槽222J設置在井接面2020正上方。
參照第1、8、9、10和11圖。方法100包括方框112，在方框112中，形成介電鰭。在第11圖所示的實施例中，在方框112處，形成介電鰭230在介電鰭溝槽222中，且形成接面介電鰭230J在接面介電鰭溝槽222J中。第8、9、10和11圖繪示出形成介電鰭的示例製程。參考第8圖，第一層224和第二層226保形地沉積在工件200上，包括在介電鰭溝槽222和接面介電鰭溝槽222J中。保形地沉積第一層224可以使用化學氣相沉積(CVD)、原子層沉積(ALD)或合適的方法。第一層224襯在介電鰭溝槽222和接面介電鰭溝槽222J的側壁和底表面。接著保形地沉積第二層226在第一層224上，使用化學氣相沉積(CVD)、高密度電漿化學氣相沉積(high density plasma,HDPCVD)及/或其他合適的製程。在一些情況下，第二層226的介電常數小於第一層224的介電常數。第一層224可以包括矽、 氮化矽、碳化矽、碳氮化矽(silicon carbonitride)、氧碳氮化矽(silicon oxycarbonitride)、氧化鋁、氮化鋁、氧氮化鋁(aluminum oxynitride)、氧化鋯、氮化鋯、氧化鋁鋯(zirconium aluminum oxide)、氧化鉿或合適的介電材料。在一實施例中，第一層224包括碳氮化矽(silicon carbonitride)。第二層226可以包括氧化矽、碳化矽、氧氮化矽(silicon oxynitride)、氧碳氮化矽(silicon oxycarbonitride)或合適的介電材料。在一實施例中，第二層226包括氧化矽。在一些實施例中，如第8圖所示，由於寬度差異，第二層226完全填充介電鰭溝槽222，但不完全填充接面介電鰭溝槽222J。
參照第9圖，回蝕保形沉積的第一層224和第二層226，露出頂犧牲層206T且去除接面介電鰭溝槽222J中的第一層224和第二層226。在一些實施例中，回蝕第一層224和第二層226的乾蝕刻製程中，可以在使用氧氣、氮氣、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其他合適的氣體及/或電漿及/或其組合。在一些實施方式中，回蝕可包括針對第二層226的第一階段和針對第一層224的第二階段。如第9圖所示，在回蝕結束時，接面隔離部件218J露出在接面介電鰭溝槽222J中。
現在參考第10圖，在露出接面介電鰭溝槽222J的情況下，沉積被覆層232在工件200上方，包括在接面介電鰭溝槽222J的側壁上方。在一些實施例中，被覆層232可以具有類似於犧牲層206或頂犧牲層206T的組成。在一示例中，被覆層232可以由矽鍺(SiGe)形成。它們的共同組成允許在隨後的製程中選擇性且同時去除犧牲層206和被覆層232。在一些實施例中，可以保形且磊晶生長被覆層232，使用氣相磊晶(VPE)或分子束磊晶(molecular beam epitaxy,MBE)。 如第10圖所示，被覆層232選擇性地設置在接面介電鰭溝槽222J中露出的側壁表面上。取決於被覆層232選擇性生長的程度，可以執行回蝕製程以露出接面隔離部件218J。仍然參考第10圖，第三層234和第四層236保形地沉積在接面介電鰭溝槽222J中。第三層234的組成和形成可以類似於第一層224的組成和形成。第四層236可以包括氧化矽或含氧化矽的介電材料。在一些實施例中，沉積第四層236可以使用化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDPCVD)或流動式化學氣相沉積(FCVD)。在一實施例中，沉積第四層236可以使用流動式化學氣相沉積(FCVD)。在沉積第三層234和第四層236之後，平坦化工件200使用化學機械拋光(CMP)製程，露出頂犧牲層206T。
參考第11圖，在平坦化之後，選擇性地回蝕第一層224、第二層226、第三層234和第四層236，以形成凹槽，且沉積帽層(helmet layer)240在這樣的凹槽中。在一些實施例中，執行選擇性回蝕可以使用乾蝕刻製程，包括氧氣、氮氣、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其他合適的氣體及/或電漿及/或其組合。帽層(helmet layer)240可以包括氮化矽、碳化矽、碳氮化矽(silicon carbonitride)、氧碳氮化矽(silicon oxycarbonitride)、氧化鋁、氮化鋁、氧氮化鋁(aluminum oxynitride)、氧化鋯、氮化鋯、鋯氧化鋁、氧化鉿或合適的介電材料。在一些實施例中，沉積帽層(helmet layer)240可以使用化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDPCVD)或合適的沉積技術。在沉積帽層(helmet layer)240之後，使用化學機械拋光(CMP)製程平坦化工件200以去除被覆層232和頂犧牲層206T上的多餘帽層(helmet layer)240。此時，大致上形成介電鰭230和接面介電鰭230J。每個介電 鰭230包括第一層224、在第一層224上方的第二層226以及在第一層224和第二層226上方的帽層(helmet layer)240。接面介電鰭230J包括第三層234、第四層236和位於第三層234和第四層236上方的帽層(helmet layer)240。每個介電鰭230設置在隔離部件218正上方。接面介電鰭230J設置在接面隔離部件218J正上方，而接面隔離部件218J設置在深隔離部件220上以及在井接面2020上方。
參照第1和12圖，方法100包括方框114。在方框114中，去除鰭狀結構211中的頂犧牲層206T。在方框114，蝕刻工件200以選擇性地去除被覆層232和頂犧牲層206T的一部分，露出最頂的通道層208，基本上不損壞介電鰭230和接面介電鰭230J的帽層(helmet layer)240。因為頂犧牲層206T和被覆層232由矽鍺(SiGe)形成，所以在方框114的蝕刻製程可以對矽鍺(SiGe)具有選擇性。在一些情況下，蝕刻被覆層232和頂犧牲層206T可以使用選擇性濕蝕刻製程，包括氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2)或其組合。如第12圖所示，在去除頂犧牲層206T和蝕刻被覆層232之後，介電鰭230和接面介電鰭230J上升到最頂的通道層208上方。
參照第1、13和14圖，方法100包括方框116，在方框116中，形成虛設閘極堆疊250在鰭狀結構211的通道區域上方。在一些實施例中，採用閘極替換製程(gate replacement process)(或閘極後製製程，gate-last process)，其中虛設閘極堆疊250作為功能閘極結構的佔位件(placeholder)。其他製程和配置也是可能的。如第13圖所示，虛設閘極堆疊250包括虛設介電層242、虛設電極244，設置在虛設介電層242上方。出於圖案化的目的，閘極頂硬遮罩248沉積在虛設閘極堆疊250上方。閘極頂硬遮罩248可以是多層的，包括氮化矽遮罩層246和氧化矽遮罩層247，在氮化矽遮罩層246上方。位於設置閘極堆疊250下方 的鰭狀結構211的區域可以被稱為通道區域。鰭狀結構211中的每個通道區域夾設在兩個源極/汲極區域之間以形成源極/汲極。在一示例製程中，藉由化學氣相沉積(CVD)，毯覆沉積虛設介電層242在工件200上方。隨後，毯覆沉積用於虛設電極244的材料層在虛設介電層242上。然後，使用微影製程圖案化虛設介電層242和用於虛設電極244的材料層，形成虛設閘極堆疊250。在一些實施例中，虛設介電層242可以包括氧化矽，虛設電極244可以包括多晶矽(polysilicon)。
參考第14圖。在方框116中，形成至少一個的閘極間隔物252沿著虛設閘極堆疊250的側壁。至少一個的閘極間隔物252可以包括兩個或更多個閘極間隔物層。可以選擇至少一個的閘極間隔物252的介電材料，以允許選擇性地去除虛設閘極堆疊250。合適的介電材料可以包括氮化矽、氧碳化矽(silicon oxycarbide)、碳氮化矽(silicon carbonitride)、氧化矽、氧碳化矽(silicon oxycarbide)、碳化矽、氧氮化矽(silicon oxynitride)及/或其組合。在一示例製程中，至少一個的閘極間隔物252可以保形沉積在工件200上，使用化學氣相沉積(CVD)、次大氣壓化學氣相沉積(SACVD)或原子層沉積(ALD)。
參照第1和14圖。方法100包括方框118，在方框118中，凹蝕鰭狀結構211的源極/汲極區域以形成源極/汲極凹槽254。虛設閘極堆疊250和至少一個的閘極間隔物252作為蝕刻遮罩，非等向性蝕刻工件200以形成源極/汲極凹槽254(或源極/汲極溝槽254)在鰭狀結構211的源極/汲極區域上方。在如第14圖所示的一些實施例中，在方框118處的操作可以基本上去除源極/汲極區域中的鰭狀結構211的頂部212T。在一些其他替代實施例中，源極/汲極溝槽254可以延伸到基部211B中。在方框118處的非等向性蝕刻可以包括乾蝕刻製程。舉例來說，乾蝕刻製程可以實施氫、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、 含氯氣體(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其他合適的氣體及/或電漿及/或其組合。
參照第1、15和16圖，方法100包括方框120，在方框120中形成內部間隔部件258。參照第15圖，在方框120處，首先選擇性地且部分地凹蝕在源極/汲極溝槽254中露出的犧牲層206，以形成內部間隔凹槽，然而大致上不蝕刻露出的通道層208。因為被覆層232和犧牲層206享有相似的成分，所以在方框120處也可以蝕刻被覆層232。在通道層208主要由矽(Si)組成、犧牲層206主要由矽鍺(SiGe)組成且被覆層232主要由矽鍺(SiGe)組成的實施例中，選擇性和部分凹蝕犧牲層206和被覆層232可以包括SiGe氧化製程與隨後的SiGe氧去除。在該實施例中，SiGe氧化製程可以包括使用臭氧。在一些其他實施例中，選擇性凹蝕可以包括選擇性等向蝕刻製程(例如選擇性乾蝕刻製程或選擇性濕蝕刻製程)，犧牲層206和被覆層232凹蝕的程度由蝕刻製程的持續時間控制。選擇性乾蝕刻製程可以包括使用一種或多種氟基的(fluorine-based)蝕刻劑，例如氟氣或氫氟碳化合物(hydrofluorocarbon)。選擇性濕蝕刻製程可以包括氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2)或其組合，例如APM蝕刻，包括氫氧化銨-過氧化氫-水混和物(ammonia hydroxide-hydrogen peroxide-water mixture)。在形成內部間隔凹槽之後，接著使用化學氣相沉積(CVD)或原子層沉積(ALD)保形沉積內部間隔材料層在工件200上，包括在內部間隔凹槽上方和之中以及由被覆層232的去除部分留下的空間。內部間隔材料可以包括氮化矽、氧碳氮化矽(silicon oxycarbonitride)、碳氮化矽(silicon carbonitride)、氧化矽、氧碳化矽(silicon oxycarbide)、碳化矽或氧氮化矽(silicon oxynitride)。在沉積內部間隔材料層之後，如第16圖所示，回蝕內部間隔材料層以形成內部 間隔部件258。
參照第1和17圖，方法100包括方框122。在方框122中，形成n型源極/汲極部件260N和p型源極/汲極部件260P。n型源極/汲極部件260N和p型源極/汲極部件260P選擇性地且磊晶沉積在源極/汲極溝槽254中的通道層208和基板202露出的半導體表面上。可以依序地沉積n型源極/汲極部件260N和p型源極/汲極部件260P使用例如氣相磊晶(VPE)、超高真空化學氣相沉積(UHV-CVD)、分子束磊晶(MBE)及/或其他合適的製程。在一些實施例中，沉積第一遮罩層，例如底部抗反射塗(BARC)層，以選擇性地露出在p井區202P上方的源極/汲極溝槽254，然後沉積p型源極/汲極部件260P在n井區202N上方露出的通道層208和基板202上方。在藉由灰化(ashing)或剝離(stripping)去除第一遮罩層之後，沉積第二遮罩層，例如BARC層，以選擇性地露出n井區上方的源極/汲極溝槽，然後沉積n型源極/汲極部件260N在p井區202P上方露出的通道層和基板202上方。接著，去除第二遮罩層。可以交換形成p型源極/汲極部件260P和n型源極/汲極部件的順序。n型源極/汲極部件260N可以包括矽(Si)摻雜n型摻雜劑，例如磷(P)或砷(As)。p型源極/汲極部件260P可以包括矽鍺(SiGe)摻雜p型摻雜劑，例如硼(B)或鎵(Ga)。可以執行與沉積源極/汲極部件原位(in-situ)的摻雜，也可以異位(ex-situ)使用佈植製程(例如接面佈值製程(junction implant process))。
仍然參照第1和17圖，方法100包括方框124，在方框124處沉積接觸蝕刻停止層(contact etch stop layer,CESL)262和層間介電(interlayer dielectric,ILD)層264。在一些實施例中，在沉積接觸蝕刻停止層(CESL)262之前，選擇性地回蝕介電鰭230和接面介電鰭230J的帽層(helmet layer)240。在一些情況 下，可以選擇性地蝕刻掉(etch away)帽層(helmet layer)240，使用緩衝氫氟酸(buffered hydrofluoric acid,BHF)或稀氫氟酸(diluted hydrofluoric acid,DHF)。在去除帽層(helmet layer)240之後，首先保形地沉積接觸蝕刻停止層(CESL)262在工件200上，然後毯覆沉積層間介電(ILD)層264在接觸蝕刻停止層(CESL)262上。接觸蝕刻停止層(CESL)262可以包括氮化矽、氧化矽、氧氮化矽(silicon oxynitride)及/或本領域已知的其他材料。沉積接觸蝕刻停止層(CESL)262可以使用原子層沉積(ALD)、電漿化學氣相沉積(PECVD)製程及/或其他合適的沉積或氧化製程。在一些實施例中，層間介電(ILD)層264包括例如四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、未摻雜矽酸玻璃或摻雜氧化矽例如硼磷矽酸玻璃(borophosphosilicate glass,BPSG)、熔融矽酸玻璃(FSG)，磷矽酸玻璃(PSG)、硼摻雜矽酸玻璃(boron doped silicon glass,BSG)及/或其他合適的介電材料。沉積層間介電(ILD)層264可以藉由旋轉塗佈(spin-on coating)、流動式化學氣相沉積(FCVD)製程或其他合適的沉積技術。在一些實施例中，在形成層間介電(ILD)層264之後，可以對工件200進行退火以改善層間介電(ILD)層264的完整性。為了去除多餘的材料並露出虛設閘極堆疊250的虛設電極244的頂表面，可以對工件200執行平坦化製程(例如化學機械拋光(CMP)製程)以提供平坦的頂表面。虛設電極244的頂表面在平坦的頂表面上露出。
參照第1、18、19和20圖，方法100包括方框126。在方框126中，虛設閘極堆疊250被接合(joint)閘極結構270代替。方框126處的操作包括去除虛設閘極堆疊250(如第18圖所示)、選擇性地去除通道區域中的犧牲層206以釋放通道構件2080(如第19圖所示)以及形成接合(joint)閘極結構270以包繞 每個通道構件2080(如第20圖所示)。參照第18圖，在方框124結束時露出的虛設閘極堆疊250藉由選擇性蝕刻製程從工件200去除。選擇性蝕刻製程可以是選擇性濕蝕刻製程、選擇性乾蝕刻製程或其組合。在所描述的實施例中，選擇性蝕刻製程選擇性地去除虛設介電層242和虛設電極244，而基本上不損壞帽層(helmet layer)240和至少一個的閘極間隔物252。虛設閘極堆疊250的去除導致閘極溝槽266在通道區域上方。
在去除虛設閘極堆疊250之後，通道區域中的通道層208、犧牲層206和被覆層232在閘極溝槽266中露出。參照第19圖，可以選擇性地去除在通道層208和被覆層232之間露出的犧牲層206，以釋放通道層208作為通道構件2080。在通道構件2080類似於片或奈米片的實施例中，通道構件釋放製程也可以被稱為片形成製程。不同於一些多橋通道(MBC)電晶體的通道構件，通道構件2080從介電鰭230的側壁橫向延伸。如第19圖所示，在釋放通道構件之後，通道構件2080與接面介電鰭230J間隔開。通道構件2080沿著Z方向垂直堆疊。選擇性去除犧牲層206和被覆層232可以實施藉由選擇性乾蝕刻、選擇性濕蝕刻或其他選擇性蝕刻製程。在一些實施例中，選擇性濕蝕刻包括氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2)或其組合(例如APM蝕刻，包括氫氧化氨-過氧化氫-水混合物)。在一些替代實施例中，選擇性去除包括矽鍺的氧化與隨後矽鍺氧化物的去除。舉例來說，可以藉由臭氧清洗(ozone clean)提供氧化，然後去除氧化矽鍺藉由蝕刻劑例如NH4OH。在去除通道區域中的犧牲層206和被覆層232之後，在閘極溝槽266中露出介電鰭230、接面介電鰭230J、通道構件2080、基部211B的頂表面、內部間隔部件258以及接面隔離部件218J。
參照第20圖，接著沉積接合(joint)閘極結構270在工件上方以包 繞在每個通道構件2080周圍。接合(joint)閘極結構270可以包括界面層267，在通道構件2080和基板202上、閘極介電層268，在界面層267上方，以及閘極電極層269，在閘極介電層268上方。在一些實施例中，界面層267包括氧化矽，可以作為預清潔製程(pre-clean process)的結果而形成。一示例性的預清潔製程(pre-clean process)可以包括使用RCA SC-1(氨、過氧化氫和水)及/或RCA SC-2(鹽酸、過氧化氫和水)。預清潔製程(pre-clean process)氧化通道構件2080和基板202的露出表面以形成界面層267。然後，沉積閘極介電層268在界面層267上，使用原子層沉積(ALD)、化學氣相沉積(CVD)及/或其他合適的方法。閘極介電層268可以包括高介電常數(high-k)介電材料。如本文所使用，高介電常數(high-k)介電材料包括具有高介電常數的介電材料，例如，其介電常數高於熱氧化矽(thermal silicon oxide)的介電常數(~3.9)。在一實施例中，閘極介電層268可以包括氧化鉿。或者，閘極介電層268可以包括其他高介電常數(high-k)介電質，例如氧化鈦(TiO2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta2O5)、矽酸鉿(HfSiO4)、氧化鋯(ZrO2)、氧化矽鋯(ZrSiO2)、氧化鑭(La2O3)、氧化鋁(Al2O3)、氧化鋯(ZrO)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3；STO)、鈦酸鋇(BaTiO3；BTO)、氧化鋇鋯(BaZrO)、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化矽鋁(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO 3；BST)氮化矽(SiN)、氧氮化矽(SiON)、其組合或其他合適的材料。在形成或沉積界面層267和閘極介電層268之後，沉積閘極電極層269在閘極介電層268上方。閘極電極層269可以是多層結構，包括至少一個的功函數層和金屬填充層。舉例來說，至少一個的功函數層可以包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鋁鈦(TiAlN)，氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、 碳化鋁鉭(TaAlC)、氮碳化鉭(TaCN)或碳化鉭(TaC)。金屬填充層可以包括鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、氮矽化鉭(TaSiN)、銅(Cu)、其他難熔金屬或其他合適的金屬材料或其組合。在各種實施例中，形成閘極電極層269可以藉由原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電子束蒸鍍或其他合適的製程。如第20圖所示，接合(joint)閘極結構270纏繞在每個通道構件2080周圍。值得注意的是，當通道構件2080與介電鰭230接觸時，接合(joint)閘極結構270不在介電鰭230和通道構件2080之間延伸。
參照第1、21和22圖，方法100包括方框128。在方框128中，執行進一步的製程。這種進一步的製程可以包括例如平坦化接合(joint)閘極結構270、回蝕接合(joint)閘極結構270、沉積金屬蓋層272，沉積自對準蓋(self-aligned cap,SAC)層274以及形成閘極切割(gate cut)部件276。參照第21圖，可以對工件200執行化學機械拋光(CMP)製程，例如平坦化製程，直到去除帽層(helmet layer)240且接合(joint)閘極結構270被介電鰭230和接面介電鰭230J隔開為止。在第21圖中，平坦化將接合(joint)閘極結構270區分為第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3和第四閘極結構270-4。第一閘極結構270-1和第二閘極結構270-2被介電鰭230分開。第二閘極結構270-2和第三閘極結構270-2被接面介電鰭230J分開。第三閘極結構270-3和第四閘極結構270-4被介電鰭230分開。
為了騰出空間給金屬蓋層272，可以選擇性回蝕第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3和第四閘極結構270-4。舉例來說，閘極結構的選擇性蝕刻可以包括選擇性濕蝕刻製程，使用硝酸、鹽酸、硫 酸、氫氧化銨、過氧化氫或其組合。然後，沉積金屬蓋層272在第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3和第四閘極結構270-4上方。在一些實施例中，金屬蓋層272可以包括鈦(Ti)、氮化鈦(TiN)、氮化鉭(TaN)、鎢(W)、釕(Ru)、鈷(Co)或鎳(Ni)，且可以藉由使用物理氣相沉積(PVD)、化學氣相沉積(CVD)或金屬有機化學氣相沉積(metal organic chemical vapor deposition,MOCVD)沉積。在一實施例中，金屬蓋層272包括鎢(W)且藉由物理氣相沉積(PVD)沉積。在一些藉由金屬有機化學氣相沉積(MOCVD)沉積金屬蓋層272的替代實施例中，沉積金屬蓋層272可以選擇性沉積在第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3、第四閘極結構270-4上。在沉積金屬蓋層272之後，沉積自對準蓋(SAC)層274在工件200上方藉由化學氣相沉積(CVD)、電漿化學氣相沉積(PECVD)或合適的沉積製程。自對準蓋(SAC)層274可以包括氧化矽、氮化矽、碳化矽、碳氮化矽(silicon carbonitride)、氧氮化矽(silicon oxynitride)、氧碳氮化矽(silicon oxycarbonitride)、氧化鋁、氮化鋁、氧氮化鋁(aluminum oxynitride)、氧化鋯、氮化鋯、氧化鋁鋯(zirconium aluminum oxide)、氧化鉿或合適的介電材料。接著執行微影製程和蝕刻製程以蝕刻沉積的自對準蓋(SAC)層274，形成閘極切割(gate cut)開口以露出介電鰭230和接面介電鰭230J的頂表面。之後，沉積介電材料且對其平坦化藉由化學機械拋光(CMP)製程，以形成閘極切割(gate cut)部件276在閘極切割(gate cut)開口中。沉積用於閘極切割(gate cut)部件276的介電材料可以使用高密度電漿化學氣相沉積(HDPCVD)、化學氣相沉積(CVD)、原子層沉積(ALD)或合適的沉積技術。在一些情況下，閘極切割(gate cut)部件276可以包括氧化矽、氮化矽、碳化矽、碳氮化矽(silicon carbonitride)、氧氮化矽(silicon oxynitride)、 氧碳氮化矽(silicon oxycarbonitride)、氧化鋁、氮化鋁、氧氮化鋁(aluminum oxynitride)、氧化鋯、氮化鋯、氧化鋁鋯(zirconium aluminum oxide)、氧化鉿或合適的介電材料。在一些實施例中，閘極切割(gate cut)部件276和自對準蓋(SAC)層274可以具有不同的成分以引進蝕刻選擇性。
第23圖繪示出第21圖中半導體裝置200通道區域的局部放大剖面圖。每個第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3和第四閘極結構270-4包繞在每個垂直堆疊的通道構件2080周圍。第一閘極結構270-1和第二閘極結構270-2被介電鰭230分開。第二閘極結構270-2和第三閘極結構270-3被接面介電鰭230J分開。第三閘極結構270-3和第四閘極結構270-4被介電鰭230分開。通道構件2080下方的基部211B被隔離部件218和接面隔離部件218J以及介電鰭230和接面介電鰭230J的下部分開。當沿Y方向觀察時，深隔離部件220可具有凸起(bulge)形狀。在一些實施例中，深隔離部件220底切(undercut)第二閘極結構270-2和第三閘極結構270-3包繞的通道構件2080，如虛線所示。深隔離部件220也底切基部211B在井接面2020的兩側。在一些情況下，深隔離部件220可具有沿Z方向的第一高度H1，約10nm至約100nm之間和沿X方向的第一寬度W1，約5nm至約50nm之間。接面隔離部件218J可以比隔離部件218寬。在一些情況下，隔離部件218可以具有第二寬度W2，約10nm至約20nm之間，且接面隔離部件218J可以具有第三寬度W3，約20nm至約30nm之間。在一實施例中，第一寬度W1大於第三寬度W3。在該實施例中，第一寬度W1在約25nm至約50nm之間。隔離部件218和接面隔離部件218J可以具有第二高度H2，約1nm至約20nm之間。深隔離部件220和接面隔離部件218J是p井區202P和n井區202N之間的邊界，協同工作以減少橫跨井接面2020的塊體漏電流(bulk leakage)。
仍然參考第23圖，第一閘極結構270-1控制設置在p井區202P上方的第一n型多橋通道(MBC)電晶體302。第一n型多橋通道(MBC)電晶體302的通道構件2080在兩個n型源極/汲極部件260N之間延伸。第二閘極結構270-2控制設置在井區202P上方的第二n型多橋通道(MBC)電晶體304。第二n型多橋通道(MBC)電晶體304的通道構件2080在兩個n型源極/汲極部件260N之間延伸。第三閘極結構270-3控制設置在n井區202N上方的第一p型多橋通道(MBC)電晶體306。第一p型多橋通道(MBC)電晶體306的通道構件2080在兩個p型源極/汲極部件260P之間延伸。第四閘極結構270-4控制設置在n井區202N上方的第二p型多橋通道(MBC)電晶體308。第二p型多橋通道(MBC)電晶體308的通道構件2080在兩個p型源極/汲極部件260P之間延伸。當沿Y方向觀察時，每個第一閘極結構270-1、第二閘極結構270-2、第三閘極結構270-3以及第四閘極結構270-4包括叉狀(fork-like)或魚骨狀(fishbone-like)結構。基於此，第一n型多橋通道(MBC)電晶體302、第二n型多橋通道(MBC)電晶體304、第一p型多橋通道(MBC)電晶體306和第二p型多橋通道(MBC)電晶體308可以被稱為叉片式電晶體或魚骨式電晶體。
基於以上討論，可以看出本揭露提供相對於現有技術的優點。儘管應理解其他實施例可以提供額外的優點，在本文中不必討論所有優點，且所有實施例都不需要特定的優點。舉例來說，魚骨式或叉片式電晶體下方鄰接的n井區和p井區被接面隔離部件和位於接面隔離部件下方的深隔離部件分開。深隔離部件可以具有與接面隔離部件不同的形狀。深隔離部件與接面隔離部件協同工作，可防止橫跨井接面的塊體漏電流(bulk leakage)。
在一示例性的面向，本揭露提供了半導體裝置的實施例。此半導 體裝置包括基板，包括p型井或n型井；第一基部，在p型井上方；第二基部，在n型井上方；多個第一通道構件，在第一基部上方；多個第二通道構件，在第二基部上方；隔離部件，設置在第一基部和第二基部之間；以及深隔離結構，設置在隔離部件下方的基板中。
在一些實施例中，隔離部件和深隔離結構延伸穿過p型井和n型井之間的接面。在一些實施例中，深隔離結構包括氧化矽、氮化矽、氧氮化矽(silicon oxynitride)、氧碳化矽(silicon oxycarbide)、碳氮化矽(silicon carbonitride)或氧碳氮化矽(silicon oxycarbonitride)。在一些實施例中，隔離部件的形狀不同於深隔離結構的形狀。在一些實施例中，半導體裝置更包括：第一閘極結構，包繞每個第一通道構件；第二閘極結構，包繞每個第二通道構件；以及第一介電鰭，設置在第一閘極結構和第二閘極結構之間。在一些實施例中，第一介電鰭設置在隔離部件上。在一些實施例中，第一閘極結構的第一部分在第一介電鰭和第一閘極結構之間延伸。在一些實施例中，半導體裝置更包括：第二介電鰭，與多個第一通道構件的側壁接觸。在一些實施例中，第一閘極結構的第二部分在第一介電鰭和第一基部之間延伸。在一些實施例中，半導體裝置更包括：第二介電鰭，與第一基部接觸。
在另一示例性的面向，本揭露提供了半導體裝置的實施例。此半導體裝置包括：基板，包括p型井或n型井；第一基部，在p型井上方；第二基部，在n型井上方；第一n型磊晶部件，在第一基部上方；第一p型磊晶部件，在第二基部上方；第一隔離部件，設置在第一基部和第二基部之間；以及深隔離結構，設置在第一隔離部件正下方的基板中。
在一些實施例中，半導體裝置更包括：第一介電鰭，設置在第一 隔離部件上，其中第一介電鰭夾設在第一n型磊晶部件和第一p型磊晶部件之間，其中第一介電鰭的寬度小於第一隔離部件的寬度。在一些實施例中，第一隔離部件的形狀不同於深隔離結構的形狀。在一些實施例中，半導體裝置更包括：第三基部，在p型井上方；第二n型磊晶部件，在第三基部上方；以及第二隔離部件，設置在第一基部和第三基部之間，第一隔離部件的寬度大於第二隔離部件的寬度。在一些實施例中，半導體裝置更包括：第二介電鰭，設置在第二隔離部件上方，其中第二介電鰭夾設在第一n型磊晶部件和第二n型磊晶部件之間，其中第二介電鰭的寬度與第二隔離部件的寬度基本相同。
在又另一例性的面向，本揭露關於一種半導體裝置的形成方法。此半導體裝置的形成方法包括：接收工件，工件包括第一鰭狀結構，在基板的p型井區域上方；以及第二鰭狀結構，在基板的n型井區域上方，第一鰭狀結構和第二鰭狀結構被接面溝槽間隔開；將接面溝槽進一步延伸到基板中以形成深凹穴；形成深隔離部件在深凹穴中，以及隔離部件在接面溝槽中；以及形成介電鰭在隔離部件上，使得介電鰭設置在第一鰭狀結構和第二鰭狀結構之間。
在一些實施例中，半導體裝置的形成方法更包括：在延伸接面溝槽之前，沿著接面溝槽的側壁形成襯層。在一些實施例中，深隔離部件和隔離部件的形成包括：沉積介電材料在深凹穴和接面溝槽中；以及回蝕襯層和介電材料，以露出第一鰭狀結構和第二鰭狀結構的側壁。在一些實施例中，半導體裝置的形成方法更包括：在形成介電鰭之前，沉積半導體被覆層在第一鰭狀結構和第二鰭狀結構的側壁上。在一些實施例中，在形成介電鰭之後，介電鰭藉由半導體被覆層與第一鰭狀結構和第二鰭狀結構間隔開。
以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通 常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，可輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的製程和結構並無悖離本發明的精神與範圍，且可在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
200:工件、裝置
202:基板
202P:p型井區域
202N:n型井區域
211B:基部
218:隔離部件
218J:接面隔離部件
220:深隔離部件
230,230J:介電鰭
270-1,270-2,270-3,270-4:閘極結構
272,274:蓋層
276:閘極切割部件
2020:井接面
2080:通道構件
302,304,306,308:多橋通道電晶體
H1,H2:高度
W1,W2,W3:寬度

Claims (15)

  1. 一種半導體裝置，包括：一基板，包括一p型井或一n型井；一第一基部，在該p型井上方；一第二基部，在該n型井上方；複數個第一通道構件，在該第一基部上方；複數個第二通道構件，在該第二基部上方；一隔離部件，設置在該第一基部和該第二基部之間；以及一深隔離結構，設置在該隔離部件下方的該基板中，其中該深隔離結構的最寬寬度大於該隔離部件的最寬寬度。
  2. 如請求項1之半導體裝置，其中該隔離部件和該深隔離結構延伸穿過該p型井和該n型井之間的接面。
  3. 如請求項1之半導體裝置，其中該深隔離結構包括氧化矽、氮化矽、氧氮化矽(silicon oxynitride)、氧碳化矽(silicon oxycarbide)、碳氮化矽(silicon carbonitride)或氧碳氮化矽(silicon oxycarbonitride)。
  4. 如請求項1之半導體裝置，其中該隔離部件的形狀不同於該深隔離結構的形狀。
  5. 如請求項1-4中任一項之半導體裝置，更包括：一第一閘極結構，包繞每個第一通道構件；一第二閘極結構，包繞每個第二通道構件；以及一第一介電鰭，設置在該第一閘極結構和該第二閘極結構之間。
  6. 如請求項5之半導體裝置，其中該第一介電鰭設置在該隔離部件 上。
  7. 如請求項5之半導體裝置，其中該第一閘極結構的一第一部分在該第一介電鰭和該第一閘極結構之間延伸；且該半導體裝置更包括：一第二介電鰭，與該些第一通道構件的側壁接觸。
  8. 如請求項5之半導體裝置，其中該第一閘極結構的一第二部分在該第一介電鰭和該第一基部之間延伸；且該半導體裝置更包括：一第二介電鰭，與該第一基部接觸。
  9. 一種半導體裝置，包括：一基板，包括一p型井或一n型井；一第一基部，在該p型井上方；一第二基部，在該n型井上方；一第一n型磊晶部件，在該第一基部上方；一第一p型磊晶部件，在該第二基部上方；一第一隔離部件，設置在該第一基部和該第二基部之間；以及一深隔離結構，設置在該第一隔離部件正下方的該基板中，其中該深隔離結構的最寬寬度大於該隔離部件的最寬寬度。
  10. 如請求項9之半導體裝置，更包括：一第一介電鰭，設置在該第一隔離部件上，其中該第一介電鰭夾設在該第一n型磊晶部件和該第一p型磊晶部件之間，其中該第一介電鰭的寬度小於該第一隔離部件的寬度。
  11. 如請求項9之半導體裝置，更包括：一第三基部，在該p型井上方； 一第二n型磊晶部件，在該第三基部上方；以及一第二隔離部件，設置在該第一基部和該第三基部之間，其中該第一隔離部件的寬度大於該第二隔離部件的寬度。
  12. 如請求項11之半導體裝置，更包括：一第二介電鰭，設置在該第二隔離部件上方，其中該第二介電鰭夾設在該第一n型磊晶部件和該第二n型磊晶部件之間，其中該第二介電鰭的寬度與該第二隔離部件的寬度基本相同。
  13. 一種半導體裝置的形成方法，包括：接收一工件，該工件包括一第一鰭狀結構，在一基板的一p型井區域上方；以及一第二鰭狀結構，在一基板的一n型井區域上方，該第一鰭狀結構和該第二鰭狀結構被一接面溝槽間隔開；將該接面溝槽進一步延伸到該基板中以形成一深凹穴；形成一深隔離部件在該深凹穴中，以及一隔離部件在該接面溝槽中；以及形成一介電鰭在該隔離部件上，使得該介電鰭設置在該第一鰭狀結構和該第二鰭狀結構之間。
  14. 如請求項13之半導體裝置的形成方法，更包括：在延伸接面溝槽之前，沿著該接面溝槽的側壁形成一襯層，且其中該深隔離部件和該隔離部件的形成包括：沉積一介電材料在該深凹穴和該接面溝槽中；以及回蝕該襯層和該介電材料，以露出該第一鰭狀結構和該第二鰭狀結構的側壁。
  15. 如請求項14之半導體裝置的形成方法，更包括：在形成該介電鰭之前，沉積一半導體被覆層在該第一鰭狀結構和該第二鰭狀結構的側壁上，且在形成該介電鰭之後，該介電鰭藉由該半導體被覆層與該第一鰭狀結構和該第二鰭狀結構間隔開。
TW110128302A 2020-10-28 2021-08-02 半導體裝置及其形成方法 TWI783606B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063106724P 2020-10-28 2020-10-28
US63/106,724 2020-10-28
US17/142,970 2021-01-06
US17/142,970 US11462612B2 (en) 2020-10-28 2021-01-06 Semiconductor device structure

Publications (2)

Publication Number Publication Date
TW202217977A TW202217977A (zh) 2022-05-01
TWI783606B true TWI783606B (zh) 2022-11-11

Family

ID=80283069

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110128302A TWI783606B (zh) 2020-10-28 2021-08-02 半導體裝置及其形成方法

Country Status (5)

Country Link
US (3) US11462612B2 (zh)
KR (1) KR102552525B1 (zh)
CN (1) CN114078847A (zh)
DE (1) DE102021100333A1 (zh)
TW (1) TWI783606B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11817504B2 (en) * 2021-01-26 2023-11-14 Taiwan Semiconductor Manufacturing Company, Ltd Isolation structures and methods of forming the same in field-effect transistors
EP4300563A1 (en) * 2022-06-29 2024-01-03 Huawei Technologies Co., Ltd. A multi-gate hybrid-channel field effect transistor
US20240038867A1 (en) * 2022-07-29 2024-02-01 International Business Machines Corporation Isolation pillar structures for stacked device structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261792A1 (en) * 2011-04-17 2012-10-18 International Business Machines Corporation Soi device with dti and sti
US20140315371A1 (en) * 2013-04-17 2014-10-23 International Business Machines Corporation Methods of forming isolation regions for bulk finfet semiconductor devices
TW201926552A (zh) * 2017-11-21 2019-07-01 台灣積體電路製造股份有限公司 半導體結構和形成半導體裝置的方法
TWI688991B (zh) * 2018-03-07 2020-03-21 美商格芯（美國）集成電路科技有限公司 接觸結構
TW202038331A (zh) * 2018-11-29 2020-10-16 台灣積體電路製造股份有限公司 積體電路裝置及其製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7573108B2 (en) * 2006-05-12 2009-08-11 Micron Technology, Inc Non-planar transistor and techniques for fabricating the same
WO2016176248A1 (en) * 2015-04-29 2016-11-03 Zeno Semiconductor, Inc. A mosfet and memory cell having improved drain current through back bias application
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US10553683B2 (en) * 2015-04-29 2020-02-04 Zeno Semiconductor, Inc. MOSFET and memory cell having improved drain current through back bias application
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US11164746B2 (en) 2018-06-26 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and a semiconductor device
US11062963B2 (en) 2018-08-15 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and process of integrated circuit having latch-up suppression
US11038036B2 (en) * 2018-09-26 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Separate epitaxy layers for nanowire stack GAA device
US11411090B2 (en) 2018-09-27 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structures for gate-all-around devices and methods of forming the same
US10790184B2 (en) 2018-09-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation with multi-step structure for FinFET device and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120261792A1 (en) * 2011-04-17 2012-10-18 International Business Machines Corporation Soi device with dti and sti
US20140315371A1 (en) * 2013-04-17 2014-10-23 International Business Machines Corporation Methods of forming isolation regions for bulk finfet semiconductor devices
TW201926552A (zh) * 2017-11-21 2019-07-01 台灣積體電路製造股份有限公司 半導體結構和形成半導體裝置的方法
TWI688991B (zh) * 2018-03-07 2020-03-21 美商格芯（美國）集成電路科技有限公司 接觸結構
TW202038331A (zh) * 2018-11-29 2020-10-16 台灣積體電路製造股份有限公司 積體電路裝置及其製造方法

Also Published As

Publication number Publication date
CN114078847A (zh) 2022-02-22
KR20220056773A (ko) 2022-05-06
US20240096942A1 (en) 2024-03-21
KR102552525B1 (ko) 2023-07-05
US11855138B2 (en) 2023-12-26
US11462612B2 (en) 2022-10-04
US20220130955A1 (en) 2022-04-28
US20220367617A1 (en) 2022-11-17
DE102021100333A1 (de) 2022-04-28
TW202217977A (zh) 2022-05-01

Similar Documents

Publication Publication Date Title
US11948987B2 (en) Self-aligned backside source contact structure
US12107169B2 (en) Contact structure for stacked multi-gate device
TWI783606B (zh) 半導體裝置及其形成方法
US11996410B2 (en) Gap-insulated semiconductor device
US11916072B2 (en) Gate isolation structure
US20220045051A1 (en) Gate Isolation Structure
US20220367463A1 (en) Reduction of gate-drain capacitance
US20240243178A1 (en) Self-aligned backside source contact structure
US20240194767A1 (en) Dielectric isolation structure for multi-gate transistors
CN221102089U (zh) 半导体结构
US12080603B2 (en) Active region cut process
US11735665B2 (en) Dielectric fin structure
TWI843395B (zh) 半導體結構及其形成方法