CN114078847A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN114078847A
CN114078847A CN202110544551.4A CN202110544551A CN114078847A CN 114078847 A CN114078847 A CN 114078847A CN 202110544551 A CN202110544551 A CN 202110544551A CN 114078847 A CN114078847 A CN 114078847A
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layer
base
fin
isolation
junction
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郑嵘健
朱熙甯
陈冠霖
江国诚
王志豪
程冠伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了半导体结构及其制造方法。根据本发明的示例性半导体结构包括具有p型阱或n型阱的衬底、位于p型阱上方的第一基部、位于n型阱上方的第二基部、位于第一基部上方的第一多个沟道构件、位于第二基部上方的第二多个沟道构件、设置在第一基部和第二基部之间的隔离部件以及设置在隔离部件的下面的衬底中的深隔离结构。

Description

半导体结构及其制造方法
技术领域
本申请的实施例涉及半导体结构及其制造方法。
背景技术
半导体集成电路(IC)工业经历了指数增长。IC材料和设计的技术进步已经产生了多代IC，其中，每代都具有比上一代更小且更复杂的电路。在IC演进过程中，功能密度(即，每芯片面积中互连器件的数量)通常已经增加，而几何尺寸(即，可以使用制造工艺产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过增加生产效率和降低相关成本来提供益处。这种按比例缩小还增加了处理和制造IC的复杂性，
例如，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极金属氧化物半导体场效应晶体管(多栅极MOSFET或多栅极器件)，以通过增加栅极-沟道耦合、降低截止状态电流以及降低短沟道效应(SCE)来改善栅极控制。多栅极器件通常是指具有栅极结构或其部分的器件，将该器件设置在沟道区的多于一侧的上方。类鳍式场效应晶体管(FinFET)和多桥沟道(MBC)晶体管是多栅极器件的实例，多栅极器件已成为高性能和低泄漏应用的流行的且有前景的候选者。FinFET具有在多于一侧上由栅极包裹的升高的沟道(例如，栅极包裹从衬底延伸的半导体材料的“鳍”的顶部和侧壁)。MBC晶体管的栅极结构可以部分或全部环绕沟道区延伸，以在两侧或更多侧上提供对沟道区的访问。因为它的栅极结构围绕沟道区，MBC晶体管也可以称为围绕栅极晶体管(SGT)或全环栅(GAA)晶体管。
尽管具有片状沟道构件的MBC晶体管通常提供优异的栅极控制和驱动电流，它们较宽的片状沟道构件可能增加器件宽度。这种增加的器件宽度可能使它们在诸如存储器应用的高封装密度应用中较少的吸引力。在形成隔离结构以隔离不同器件区域中，改善MBC晶体管封装密度的措施可能面临挑战。尽管现有的半导体器件通常足以满足它们预期目的，但是它们不是在所有方面都已完全令人满意。
发明内容
本申请的一些实施例提供了一种半导体结构，包括：衬底，包括p型阱或n型阱；第一基部，位于所述p型阱上方；第二基部，位于所述n型阱上方；第一多个沟道构件，位于所述第一基部上方；第二多个沟道构件，位于所述第二基部上方；隔离部件，设置在所述第一基部和所述第二基部之间；以及深隔离结构，设置在所述隔离部件的下面的所述衬底中。
本申请的另一些实施例提供了一种半导体结构，包括：衬底，包括p型阱或n型阱；第一基部，位于所述p型阱上方；第二基部，位于所述n型阱上方；第一n型外延部件，位于所述第一基部上方；第一p型外延部件，位于所述第二基部上方；第一隔离部件，设置在所述第一基部与所述第二基部之间；以及深隔离结构，设置在所述第一隔离部件的正下面的所述衬底中。
本申请的又一些实施例提供了一种制造半导体结构的方法，包括：接收工件，所述工件包括位于衬底的p型阱区上方的第一鳍状结构和位于所述衬底的n型阱区上方的第二鳍状结构，所述第一鳍状结构和所述第二鳍状结构由结沟槽间隔开；将所述结沟槽进一步延伸至所述衬底中以形成深凹穴；在所述深凹穴中形成深隔离部件并且在所述结沟槽中形成隔离部件；以及在所述隔离部件上形成介电鳍，从而使得将所述介电鳍设置在所述第一鳍状结构和所述第二鳍状结构之间。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制，仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的一个或多个方面的用于形成半导体器件的方法的流程图。
图2至图23示出了根据本发明的一个或多个方面的在图1的方法的各个制造阶段期间的工件的局部立体图或截面图
具体实施方式
以下公开内容提供了许多用于实现所提供的主题的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考字符和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
为了便于描述，在此可以使用诸如“在…之下”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
此外，当用“约”、“近似”等描述数值或数值的范围时，考虑到如本领域普通技术人员所理解的在制造期间固有地产生的变化，该术语旨在包括在合理范围内的数值。例如，基于与制造具有与数值相关联的特征的部件相关联的已知制造公差，数值的数值范围涵盖了包括所描述数值的合理范围，诸如在所描述数值的+/-10％以内。例如，厚度为“约5nm”的材料层可涵盖的尺寸范围为4.25nm至5.75nm，其中本领域的普通技术人员已知与沉积材料层相关的制造公差为+/-15％。更进一步，本发明可以在各个实例中重复参考标号和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
本发明通常是关于降低块体泄漏的隔离结构，并且更具体地是关于设置在阱结上的深隔离结构。
为了改善驱动电流以满足设计需求，MBC晶体管可以包括薄且宽的纳米级沟道构件。这种MBC晶体管也可以称为纳米片晶体管。尽管纳米片晶体管能够提供令人满意的驱动电流和沟道控制，它们较宽的纳米片沟道构件可能使其进一步降低单元尺寸成为挑战。在一些示例性结构中，可以实行鱼骨结构或叉片结构以降低单元尺寸。在鱼骨结构或叉片结构中，沟道构件的相邻堆叠件可以由介电鳍(或混合鳍)分离开。由于沟道构件的堆叠件的一端与介电鳍接触，环绕包裹沟道构件的堆叠件的栅极结构不在沟道构件和介电鳍之间延伸。每个介电鳍设置在诸如浅沟槽隔离(STI)部件的隔离部件上。STI部件也可以设置在n型阱和p型阱之间的结上以降低块体泄漏。
本发明提供了设置在n型器件下方的p型阱和p型器件下方的n型阱之间的阱结处的深隔离结构。在一些实施例中，深隔离结构的形成包括沿着阱结的凹口的形成。凹口可以底切n型器件和p型器件的有源区。在至少一些实施例中，n型器件和p型器件可以是鱼骨或叉片晶体管。深隔离结构可以更好地阻挡n型阱和p型阱之间的块体泄漏路径。
现在将参考附图更详细地描述本发明的各个方面。图1示出了形成半导体器件的方法100的流程图。方法100仅是实例，并不旨在将本发明限制为方法100中明确示出的内容。对于方法的额外的实施例，可以在方法100之前、期间和之后提供额外的步骤，并且可以替换、消除或移动所描述的一些步骤。为了简单起见，本文没有详细描述所有步骤。下面结合图1至图23描述方法100，其示出了根据方法100的实施例的在制造的不同阶段的工件200的局部截面图。因为半导体器件将由工件200形成，根据上下文需要，可以将工件200称为半导体器件200。尽管在附图中示出了包括鱼骨或叉片晶体管的实施例，但是本发明不限于此，并且可应用至诸如MBC晶体管或FinFET的其它多栅极器件。在贯穿图2至图23中，X方向、Y方向和Z方向彼此垂直并且一致地使用X方向、Y方向和Z方向。另外，在整个本发明中，类似的参考标号用于表示类似的部件。
参考图1和图2，方法100包括块102，在块102中接收工件200。如图2所示，工件200包括衬底202和设置在衬底202上的堆叠件204。在一个实施例中，衬底202可以是硅(Si)衬底。在一些其它实施例中，衬底202可以包括诸如锗(Ge)、硅锗(SiGe)或III-V半导体材料的其它半导体材料。示例性III-V半导体材料可以包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、磷化镓铟(GaInP)和砷化铟镓(InGaAs)。衬底202可以包括多个n型阱区和多个p型阱区。在所描绘的实施例中，衬底202包括p型阱区202P(或p阱202P)和n型阱区202N(或n阱202N)。如图2所示，p阱202P和n阱202N沿着阱结2020彼此接合。p阱202P可以掺杂有p型掺杂剂(即，硼(B))并且n阱202N可以掺杂有n型掺杂剂(即，磷(P)或砷(As))。可以使用离子注入或热扩散来形成p阱202P和n阱202N。
仍然参考图2，堆叠件204可以包括与多个牺牲层206交错的多个沟道层208。沟道层208和牺牲层206可以具有不同的半导体组成。在一些实施方式中，沟道层208由硅(Si)形成，并且牺牲层206由硅锗(SiGe)形成。在这些实施方式中，牺牲层206中的额外的锗含量允许牺牲层206的选择性去除或凹进，而不会实质性损坏沟道层208。在图2所呈现的一些实施例中，工件200还包括设置在堆叠件204上的顶部牺牲层206T。顶部牺牲层206T比其它牺牲层206厚，并且用于保护堆叠件204在制造工艺器件不受损坏。可以使用外延工艺来沉积顶部牺牲层206T、牺牲层206和沟道层208。可以使用CVD沉积技术(例如，气相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)和/或其它合适的工艺来外延沉积堆叠件204。顺次交替沉积牺牲层206和沟道层208，以形成堆叠件204。图2示出了交替且垂直地布置的三(3)层牺牲层206的和三(3)层沟道层208，这仅出于示出的目的，并不旨在限制权利要求中具体记载的内容。层的数量取决于用于半导体器件200的沟道构件期望的数量。在一些实施例中，沟道层208的数量在1和6之间。
参考图1和图3，方法100包括块104，在块104中图案化堆叠件204和衬底202以形成由沟槽212或结沟槽212J分隔开的鳍状结构211。为了图案化堆叠件204和衬底202，在顶部牺牲层206T上方沉积第一硬掩模层210。然后图案化第一硬掩模层210以作为蚀刻掩模，以图案化顶部牺牲层206、堆叠件204和衬底202的部分。在一些实施例中，可以使用CVD、等离子体增强CVD(PECVD)、原子层沉积(ALD)、等离子体增强ALD(PEALD)或合适的沉积方法来沉积第一硬掩模层210。第一硬掩模层210可以是单层或多层。当第一硬掩模层210是多层时，第一硬掩模层210可以包括垫氧化物和垫氮化物层。在可选的实施例中，第一硬掩模层210可以包括硅(Si)。可以使用包括双图案化或多图案化工艺的合适的工艺图案化鳍状结构211。通常，双图案化或多图案化工艺将光刻和自对准工艺结合，允许创建具有例如间距小于使用单个直接直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成材料层并且使用光刻工艺图案化材料层。使用自对准工艺在图案化的材料层旁边形成间隔件。然后去除材料层，并且然后可以使用剩余的间隔件或芯轴来图案化第一硬掩模层210，并且然后可以将图案化的第一硬掩模层210用作蚀刻掩模以蚀刻堆叠件204和衬底202，以形成鳍状结构211。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其它合适的工艺。
如图3所示，每个鳍状结构211包括由衬底202的部分形成的基部211B和由堆叠件204形成的顶部211T。顶部211T设置在基部211B的上方。鳍状结构211从衬底202沿着Y方向纵向地延伸，并且沿着Z方向垂直地延伸。沿着X方向，鳍状结构211由沟槽212和结沟槽212J分隔开。与沟槽212相比，结沟槽212J设置在阱结2020上并沿着阱结2020。在图3呈现的一些实施例中，结沟槽212J沿着X方向比沟槽212宽以提供更大的间隔。如图3所示，结沟槽212J限定第一间隔S1，并且沟槽212限定第二间隔S2。第一间隔S1大于第二间隔S2。在一些示例中，第一间隔S1在约20nm与约30nm之间，并且第二间隔S2在约10nm与约20nm之间。较宽的结沟槽212J允许将阱结2020的任一侧上的有源区，诸如鳍状结构211，进一步间隔开以降低块体泄漏。
参考图1和图4，方法100包括块106，在块106中沿着鳍状结构211的侧壁形成衬垫214。衬垫214用于保护鳍状结构211的侧壁在块108(将在下面描述)期间不受损坏。在形成衬垫214的示例性工艺中，通过原子层沉积(ALD)、化学气相沉积(CVD)或低压CVD(LPCVD)来在工件200上方，包括在沟槽212和结沟槽212J上方，共形地沉积介电材料。用于衬垫214的介电材料可以包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或它们的组合。然后，各向异性地回蚀刻沉积的介电材料以形成衬垫214。在一些实施例中，回蚀刻可以包括干蚀刻工艺，干蚀刻工艺使用一种或多种诸如四氟化碳(CF4)、六氟化硫(SF6)、或三氟化氮(NF3)的含氟气体。如图4所示，因为结沟槽212J中的第一间隔S1较大，去除了结沟槽212J的底面上的介电材料以暴露衬底202。即，衬垫214仅衬在结沟槽212J的侧壁。沟槽212的较小的第二间隔S2防止介电材料从其底表面去除。
参照图1和图5，方法100包括块108，在块108中将结沟槽212J延伸至衬底202中以形成深凹穴216。在沟槽212由衬垫214保护，并且衬底202从结沟槽212J的底面暴露情况下，在块108处的操作蚀刻暴露的衬底202至结沟槽212J之下。暴露的衬底202的蚀刻将结沟槽212J向下延伸至衬底202中以形成深凹穴216。也可以将深凹穴216称为凹口。可以使用趋于各向异性的干蚀刻工艺或趋于各向同性的湿蚀刻工艺来执行块108处的蚀刻。示例性的选择性湿蚀刻工艺可以包括使用乙二胺邻苯二酚(EDP)、四甲基氢氧化铵(TMAH)、硝酸(HNO3)、氢氟酸(HF)、氨(NH3)、氟化铵(NH4F)或合适的湿蚀刻剂。示例性选择性干蚀刻工艺可以包括六氟化硫(SF6)、氢(H2)、氨(NH3)、氟化氢(HF)、四氟化碳(CF4)、氩(Ar)或它们的混合物。在图5所呈现的一些实施例中，在块108处的蚀刻工艺不是完全各向异性的，并且深凹穴216底切衬垫214。结果，深凹穴216的形状与结沟槽212J的形状不同。在一些示例中，深凹穴216的最宽部分的宽度大于结沟槽212J(包括衬垫214)的宽度。在形成深凹穴216之前，将深凹穴216设置在沟槽212或结沟槽212J的底面的下面的水平。相应地，将深凹穴216更深的设置在衬底202中。
参考图1、图6和图7，方法100包括块110，在块110中，在深凹穴216和沟槽212中形成隔离部件。在块110处形成的隔离部件可以包括位于沟槽212中的隔离部件218和位于结沟槽212J中的结隔离部件218J和位于深凹穴216中的深隔离部件220。可以将隔离部件218和结隔离部件218J统称为浅沟槽隔离(STI)部件。在形成这些隔离部件的示例性工艺中，在工件200上方沉积介电材料，用介电材料填充沟槽212、深凹穴216和结沟槽212J。在一些实施例中，介电材料可以包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或它们的组合。在各个实例中，在块110处，可以通过CVD工艺、次常压CVD(SACVD)工艺、可流动CVD(FCVD)工艺、ALD工艺、旋涂和/或其它合适的工艺来沉积介电材料。然后，例如通过化学机械抛光(CMP)工艺来减薄并平坦化沉积的介电材料，直到暴露出顶部牺牲层206T，如图6所示。在一些实施例中，衬垫214和用于隔离部件的介电材料的组成可以是相似的，并且它们的边界用虚线标记。为了便于说明，在随后的附图中可以省略衬垫214和隔离部件之间的边界。参考图7，通过干蚀刻工艺、湿蚀刻工艺和/或它们的组合来进一步凹进平坦化的介电材料和衬垫214，以形成隔离部件218、结隔离部件218J、以及深隔离部件220的最终结构。如图7所示，鳍状结构211的顶部211T升高到隔离部件218或结隔离部件218J之上，同时基部211B或它们的大部分由隔离部件218或结隔离部件218J围绕。如图7所示，深隔离部件220设置在基部211B的水平面的下面，并且可以低切与阱结2020相邻的基部211B。即，深隔离部件的部分可以在该相邻的基部211B下方延伸。在形成隔离部件218和结隔离部件218J之后，顶部211T由介电鳍沟槽222和结介电鳍沟槽222J分隔开。结介电鳍沟槽222J设置在阱结2020的正上方。
参考图1、图8、图9、图10和图11，方法100包括块112，在块112处形成介电鳍。在图11描绘的实施例中，在块112处，在介电鳍沟槽222中形成介电鳍230，以及在结介电鳍沟槽222J中形成结介电鳍230J。在图8、图9、图10和图11中示出了形成介电鳍的示例性工艺。参考图8，在工件200上方，包括在介电鳍沟槽222和结介电鳍沟槽222J中，共形地沉积第一层224和第二层226。可以使用CVD、ALD或合适的方法共形地沉积第一层224。第一层224衬在介电鳍沟槽222和结介电鳍沟槽222J的侧壁和底面。然后使用CVD、高密度等离子体CVD(HDPCVD)和/或其它合适的工艺在第一层224上方共形地沉积第二层226。在一些示例中，第二层226的介电常数小于第一层224的介电常数。第一层224硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氧化铝、氮化铝、氮氧化铝、氧化锆、氮化锆、氧化锆铝，氧化铪或合适的介电材料。在一个实施例中，第一层224包括碳氮化硅。第二层226可以包括氧化硅、碳化硅、氮氧化硅、碳氮氧化硅或合适的介电材料。在一实施例中，第二层226包括氧化硅。在图8所呈现的一些实施例中，由于宽度差异，第二层226完全填充介电鳍沟槽222，但是不完全填充结介电鳍沟槽222J。
参照图9，回蚀刻共形沉积的第一层224和第二层226，以暴露顶部牺牲层206T，并去除位于结介电鳍沟槽222J中的第一层224和第二层226。在一些实施例中，可以在干蚀刻工艺中回蚀刻第一层224和第二层226，干蚀刻工艺使用氧、氮、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBr3)、含碘气体、其它合适的气体和/或等离子体、和/或它们的组合。在一些实施方式中，回蚀刻可以包括针对第二层226的第一阶段和针对第一层224的第二阶段。如图9所示，在回蚀刻结束时，在结介电鳍沟槽222J中暴露结隔离部件218J。
现在参考图10，在暴露结介电鳍沟槽222J的情况下，在工件200上方，包括在结介电鳍沟槽222J的侧壁上方，沉积包覆层232。在一些实施例中，包覆层232可以具有与牺牲层206或顶部牺牲层206T相似的组成。在一个实例中，包覆层232可以由硅锗(SiGe)形成。它们的共同组成允许在随后的工艺中选择性且同时去除牺牲层206和包覆层232。在一些实施例中，可以使用气相外延(VPE)或分子束外延(MBE)来共形地且外延生长包覆层232。如图10所示，将包覆层232选择性地设置在结介电鳍沟槽222J中的暴露的侧壁表面上。取决于包覆层232的选择性生长的程度，可以执行回蚀刻工艺以暴露结隔离部件218J。仍然参考图10，第三层234和第四层236共形地沉积在结介电鳍沟槽222J中。第三层234的组成和形成可以与第一层224的组成和形成相似。第四层236可以包括氧化硅或含介电材料的氧化硅。在一些实施例中，可以使用CVD、HDPCVD或可流动CVD(FCVD)来沉积第四层236。在一个实施例中，可以使用FCVD来沉积第四层236。在沉积第三层234和第四层236之后，使用化学机械抛光(CMP)工艺来平坦化工件200以暴露出顶部牺牲层206T。
参考图11。在平坦化之后，选择性回蚀刻第一层224、第二层226、第三层234、和第四层236以形成凹槽，并且在这些凹槽中沉积帽层240。在一些实施例中，可以使用干蚀刻工艺来执行选择性回蚀刻，干蚀刻工艺可以包括氧、氮、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBr3)、含碘气体、其它合适的气体和/或等离子体、和/或它们的组合。帽层240可以包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氧化铝、氮化铝、氮氧化铝、氧化锆、氮化锆、氧化锆铝，氧化铪或合适的介电材料。在一些实施例中，可以使用CVD、HDPCVD或合适的沉积技术来沉积帽层240。在沉积帽层240之后，使用CMP工艺平坦化工件200以去除位于包覆层232和顶部牺牲层206T上的多余的帽层240。在此时，介电鳍230和结介电鳍230J基本形成。每个介电鳍230包括第一层224、位于第一层224上方的第二层226以及位于第一层224和第二层226上方的帽层240。结介电鳍230J包括第三层234、第四层236和位于第三层234和第四层236上方的帽层240。每个介电鳍230设置在隔离部件218正上方。结介电鳍230J设置在结隔离部件218J正上方，结隔离部件218J设置在阱结2020上方的深隔离部件220上。
参考图1和图12，方法100包括块114，在块114中去除鳍状结构211中的顶部牺牲层206T。在块114处，蚀刻工件200以选择性地去除包覆层232的部分和顶部牺牲层206T以暴露最顶沟道层208，基本上不损坏介电鳍230和结介电鳍230J的帽层240。因为顶部牺牲层206T和包覆层232由硅锗(SiGe)形成，在块114处的蚀刻工艺可以对硅锗(SiGe)是选择性的。在一些示例中，可以使用选择性湿蚀刻工艺来蚀刻包覆层232和顶部牺牲层206T，选择性湿蚀刻工艺包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或它们的组合。如图12所示，在去除顶部牺牲层206T并且蚀刻包覆层232之后，介电鳍230和结介电鳍230J上升到最顶沟道层208之上。
参考图1、图13和图14，方法100包括块116，在块116中在鳍状结构211的沟道区上方形成伪栅极堆叠件250。在一些实施例中，采用栅极替换工艺(或后栅极工艺)，其中伪栅极堆叠件250作为用于功能栅极结构的占位符。其它工艺和配置是可能的。如图13所示，伪栅极堆叠件250包括伪介电层242，设置在伪介电层242上方的伪电极244。用于图案化的目的，在伪栅极堆叠件250上方沉积栅极顶部硬掩模248。栅极顶部硬掩模248可以是多层的，并且包括氮化硅掩模层246和位于氮化硅掩模层246上方的氧化硅掩模层247。可以将伪栅极堆叠件250下面的鳍状结构211的区域称为沟道区。鳍状结构211中的每个沟道区夹在用于源极/漏极形成的两个源极/漏极区之间。在示例性工艺中，通过CVD在工件200上方毯式沉积伪介电层242。然后，在伪介电层242上方毯式沉积用于伪电极244的材料层。然后，使用光刻工艺图案化伪介电层242和用于伪电极244的材料层，以形成伪栅极堆叠件250。在一些实施例中，伪介电层242可以包括氧化硅，并且伪电极244可以包括多晶硅(poly硅)。
参考图14。在块116处，沿着伪栅极堆叠件250的侧壁形成至少一个栅极间隔件252。至少一个栅极间隔件252可以包括两个或更多个栅极间隔件层。可以选择用于至少一个栅极间隔件252的介电材料，以允许伪栅极堆叠件250的选择性去除。合适的介电材料可以包括氮化硅、碳氮氧化硅、碳氮化硅、氧化硅、碳氧化硅、碳化硅、氮氧化硅、和/或它们的组合。在示例性工艺中，可以使用CVD、次常压CVD(SACVD)、或ALD在工件200上方共形地沉积至少一个栅极间隔件252。
参考图1和图14，方法100包括块118，在块118中凹进鳍状结构211的源极/漏极区以形成源极/漏极凹槽254。在伪栅极堆叠件250和至少一个栅极间隔件252作为蚀刻掩模的情况下，各向异性蚀刻工件200，以在鳍状结构211的源极/漏极区上方形成源极/漏极凹槽254(或源极/漏极沟槽254)。如图14中示出的实施例中，在块118处的操作可以基本去除源极/漏极区中的鳍状结构211的顶部212T。在一些其它可选的实施例中，源极/漏极沟槽254可以延伸至基部211B中。在块118处的各向异性蚀刻可以包括干蚀刻工艺。例如，干蚀刻工艺可以实施氢、含氟气体(例如CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBr3)、含碘气体、其它合适的气体和/或等离子体、和/或它们的组合。
参考图1、图15和图16，方法100包括块120，在块120中形成内部间隔件部件258。参考图15，在块120处，首先选择性地且部分地凹进暴露在源极/漏极沟槽254中的牺牲层206，以形成内部间隔件凹槽，同时基本未蚀刻暴露的沟道层208。因为包覆层232和牺牲层206共享相似的组成，也可以在块120处蚀刻包覆层232。在沟道层208实质上由硅(Si)组成的实施例中，牺牲层206实质上由硅锗(SiGe)组成，并且包覆层232实质上由硅锗(SiGe)组成，牺牲层206和包覆层232的选择性地和部分地凹进可以包括SiGe氧化工艺，接着SiGe氧化物去除。在那个实施例中，SiGe氧化工艺可以包括使用臭氧。在一些其它实施例中，选择性凹进可以包括选择性各向同性蚀刻工艺(例如，选择性干蚀刻工艺或选择性湿蚀刻工艺)，并且牺牲层206和包覆层232凹进的程度由蚀刻工艺的持续时间控制。选择性干蚀刻工艺可以包括使用一种或多种诸如氟气体或氢氟碳化合物(hydrofluorocarbons)的氟基蚀刻剂。选择性湿蚀刻工艺可以包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或它们的组合(例如，包括氢氧化氨-过氧化氢-水混合物的APM蚀刻)。在形成内部间隔件凹槽之后，然后使用CVD或ALD将内部间隔件材料层共形地沉积在工件200上方，包括在内部间隔件凹槽上方和之中以及由包覆层232的去除部分留下的间隔上方和之中。内部间隔件材料可以包括氮化硅、碳氮氧化硅、碳氮化硅、氧化硅、碳氧化硅，碳化硅或氮氧化硅。在沉积内部间隔件材料层之后，回蚀刻内部间隔件材料层以形成内部间隔件部件258，如图16所示。
参考图1和图17，方法100包括块122，在块122中形成n型源极/漏极部件260N和p型源极/漏极部件260P。在源极/漏极沟槽254中的衬底202和沟道层208的暴露的半导体表面上选择性地并且外延沉积n型源极/漏极部件260N和p型源极/漏极部件260P。可以使用诸如气相外延(VPE)、超高真空CVD(UHV-CVD)、分子束外延(MBE)、和/或其它合适的工艺的外延工艺来顺序地沉积n型源极/漏极部件260N和p型源极/漏极部件260P。在一些实施例中，沉积诸如BARC层的第一掩模层，以选择性地暴露位于p阱202P上方的源极/漏极沟槽254，并且然后在n阱202N上方的暴露的沟道层208和衬底202上方沉积p型源极/漏极部件260P。在通过灰化或剥离去除第一掩模层之后，沉积诸如BARC层的第二掩模层，以选择性地暴露位于n阱上方的源极/漏极沟槽，并且然后在p阱202P上方的衬底202和暴露的沟道层上方沉积n型源极/漏极部件260N。然后去除第二掩模层。p型源极/漏极部件260P和n型源极/漏极部件的形成顺序可以切换。n型源极/漏极部件260N可以包括掺杂有诸如磷(P)或砷(As)的n型掺杂剂的硅(Si)。p型源极/漏极部件260P可以包括掺杂有诸如硼(B)或镓(Ga)的p型掺杂剂的硅锗(SiGe)。可以在它们沉积时原位执行源极/漏极部件的掺杂，或者使用诸如结注入工艺的注入工艺非原位执行源极/漏极部件的掺杂。
仍然参考图1和图17，方法100包括块124，在块124中沉积接触蚀刻停止层(CESL)262和层间介电(ILD)层264。在一些实施例中，在沉积CESL262之前，选择性回蚀刻介电鳍230和结介电鳍230J的帽层240。在一些示例中，可以使用缓冲氢氟酸(BHF)或稀氢氟酸(DHF)来选择性蚀刻掉帽层240。在去除帽层240之后，首先在工件200上方共形地沉积CESL262，并且然后在CESL 262上方毯式沉积ILD层264。CESL 262可以包括氮化硅、氧化硅、氮氧化硅和/或本领域已知的其它材料。可以使用ALD、等离子体增强化学气相沉积(PECVD)工艺和/或其它合适的沉积或氧化工艺来沉积CESL 262。在一些实施例中，ILD层264包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG)的掺杂的氧化硅、和/或其它合适的介电材料。可以通过旋涂、FCVD工艺或其它合适的沉积技术来沉积ILD层264。在一些实施例中，在形成ILD层264之后，可以将工件200退火以改善ILD层264的完整性。为了去除多余的材料并且暴露伪栅极堆叠件250的伪电极244的顶面，可以对工件200执行平坦化工艺(诸如，化学机械抛光(CMP)工艺)，以提供平坦的顶面。伪电极244的顶面在该平坦的顶面上暴露。
参考图1、图18、图19和图20，方法100包括块126，在块126中，用结合栅极结构替换伪栅极堆叠件250。在块126处的操作包括去除伪栅极堆叠件250(图18所示)、选择性去除沟道区中的牺牲层206以释放沟道构件2080(图19所示)，以及形成结合栅极结构270以环绕包裹每个沟道构件2080(图20所示)。参考图18，通过选择性刻蚀工艺从工件200去除在块124结束时暴露的伪栅极堆叠件250。选择性刻蚀工艺可以是选择性湿蚀刻工艺、选择性干蚀刻工艺或它们的组合。在所描绘的实施例中，选择性蚀刻工艺选择性地去除伪介电层242和伪电极244，而基本上不损坏帽层240和至少一个栅极间隔件252。去除伪栅极堆叠件250产生了位于沟道区上方的栅极沟槽266。
在去除伪栅极堆叠件250之后，沟道区中的沟道层208、牺牲层206和包覆层232暴露在栅极沟槽266中。参考图19，可以选择性地去除位于沟道层208之间的暴露的牺牲层206和包覆层232，以释放沟道层208作为沟道构件2080。在所描绘的实施例中，其中，沟道构件2080像片或纳米片，也可以将沟道构件释放工艺称为片形成工艺。与某些MBC晶体管的沟道构件不同，沟道构件2080从介电鳍230的侧壁横向延伸。如图19所示，在它们的释放之后，沟道构件2080与结介电鳍230J间隔开。沟道构件2080沿着Z方向垂直地堆叠。可以通过选择性干蚀刻，选择性湿蚀刻或其它选择性蚀刻工艺来实施牺牲层206和包覆层232的选择性去除。在一些实施例中，选择性湿蚀刻包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或它们的组合(例如，包括氢氧化氨-过氧化氢-水混合物的APM蚀刻)。在一些可选的实施例中，选择性去除包括硅锗氧化，接着是硅锗氧化物去除。例如，可以通过臭氧清洁来提供氧化，并且然后通过诸如NH4OH的蚀刻剂去除硅锗氧化物。在去除沟道区中的牺牲层206和包覆层232的情况下，介电鳍230、结介电鳍230J、沟道构件2080、基部211B的顶面、内部间隔件部件258以及结隔离部件218J暴露在栅极沟槽266中。
参考图20，然后在工件上方沉积结合栅极结构270以环绕包裹每个沟道构件2080。结合栅极结构270可以包括位于沟道构件2080和衬底202上的界面层267、位于界面层267上方的栅极介电层268和位于栅极介电层268上方的栅电极层269。在一些实施例中，界面层267包括氧化硅并且可以由于预清洁工艺而形成。示例性的预清洁工艺可以包括使用RCASC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。预清洁工艺将沟道构件2080和衬底202的暴露表面氧化以形成界面层267。然后，使用ALD、CVD和/或其它合适的方法在界面层267上方沉积栅极介电层268。栅极介电层268可以包括高K介电材料。如本文所用，高k介电材料包括具有高介电常数的介电材料，例如，大于热氧化硅的介电常数
Figure BDA0003073104610000141
在一个实施例中，栅极介电层268可以包括氧化铪。可选的，栅极介电层268可以包括其它高K电介质，诸如氧化钛(TiO2)、氧化铪锆(HfZrO)、氧化钽(Ta2O5)、氧化铪硅(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、它们的组合、或其它合适的材料。在形成或沉积界面层267和栅极介电层268之后，在栅极介电层268上方沉积栅电极层269。栅电极层269可以是包括至少一个功函层和金属填充层的多层结构。作为示例，至少一个功函层可以包括氮化钛(TiN)、钛铝(TiAl)、氮化铝钛(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)或碳化钽(TaC)。金属填充层可以包括铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、氮化钽硅(TaSiN)、铜(Cu)、其它难熔金属或其它合适的金属材料或它们的组合。在各个实施例中，可以通过ALD、PVD、CVD、电子束蒸发或其它合适的工艺来形成栅电极层269。如图20所示，结合栅极结构270环绕包裹每个沟道构件2080。值得注意的是，因为沟道构件2080与介电鳍230接触，结合栅极结构270不在介电鳍230和沟道构件2080之间延伸。
参考图1、图21和图22，方法100包括块128，在块128中执行进一步的工艺。这些进一步工艺可以包括例如，结合栅极结构270的平坦化、结合栅极结构270的回蚀刻、金属覆盖层272的沉积、自对准覆盖(SAC)层274的沉积以及栅极切割部件276的形成。参考图21，可以对工件200执行诸如CMP工艺的平坦化工艺，直到去除帽层240并且结合栅极结构270由介电鳍230和结介电鳍230J分离。在图21中，平坦化将结合栅极结构270分离为第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3以及第四栅极结构270-4。第一栅极结构270-1和第二栅极结构270-2由介电鳍230分隔开。第二栅极结构270-2和第三栅极结构270-2由结介电鳍230J分隔开。第三栅极结构270-3和第四栅极结构270-4由介电鳍230分隔开。
为了制造用于金属覆盖层272的空间，可以选择性地回蚀刻第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3和第四栅极结构270-4。例如，栅极结构的选择性蚀刻可以包括选择性湿蚀刻工艺，该选择性湿蚀刻工艺使用硝酸、盐酸、硫酸、氢氧化铵、过氧化氢或它们的组合。然后，在第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3和第四栅极结构270-4上方沉积金属覆盖层272。在一些实施例中，金属覆盖层272可以包括钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、钨(W)、钌(Ru)、钴(Co)或镍(Ni)，并且可以使用PVD、CVD或金属有机化学气相沉积(MOCVD)来沉积金属覆盖层272。在一个实施例中，金属覆盖层272包括钨(W)并且通过PVD沉积。在通过MOCVD沉积金属覆盖层272的一些可选的实施例中，金属覆盖层272的沉积可以在第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3和第四栅极结构270-4上选择性沉积。在沉积金属覆盖层272之后，通过CVD、PECVD或合适的沉积工艺在工件200上方沉积SAC层274。SAC层274可以包括氧化硅、氮化硅、碳化硅、碳氮化硅、氮氧化硅、碳氮氧化硅、氧化铝、氮化铝、氮氧化铝、氧化锆、氮化锆、氧化锆铝，氧化铪或合适的介电材料。然后执行光刻工艺和蚀刻工艺以蚀刻沉积的SAC层274以形成栅极切割开口以暴露介电鳍230和结介电鳍230J的顶面。此后，沉积介电材料并通过CMP工艺平坦化介电材料，以在栅极切割开口中形成栅极切割部件276。可以使用HDPCVD、CVD、ALD或合适的沉积技术来沉积用于栅极切割部件276的介电材料。在一些示例中，栅极切割部件276可以包括氧化硅、氮化硅、碳化硅、碳氮化硅、氮氧化硅、碳氮氧化硅、氧化铝、氮化铝、氮氧化铝、氧化锆、氮化锆、氧化锆铝，氧化铪或合适的介电材料。在一些实施例中，栅极切割部件276和SAC层274可以具有不同的组成以引入蚀刻选择性。
图23中示出了图21中的半导体器件200的沟道区的放大局部截面图。第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3和第四栅极结构270-4中的每个环绕包裹沟道构件2080的垂直堆叠件中的每个。第一栅极结构270-1和第二栅极结构270-2由介电鳍230分隔开。第二栅极结构270-2和第三栅极结构270-3由结介电鳍230J分隔开。第三栅极结构270-3和第四栅极结构270-4由介电鳍230分隔开。位于沟道构件2080下方的基部211B由隔离部件218和结隔离部件218J以及介电鳍230和结介电鳍230J的下部分隔开。当沿着Y方向观看时，深隔离部件220可以具有凸起形状。在一些实施例中，如虚线所示，深隔离部件220底切由第二栅极结构270-2和第三栅极结构270-3环绕包裹的沟道构件2080。深隔离部件220还低切位于阱结2020的两侧上的基部211B。在一些示例中，深隔离部件220可以具有沿着Z方向在约10nm与约100nm之间的第一高度H1和沿着X方向在约5nm与约50nm之间的第一宽度W1。结隔离部件218J可以比隔离部件218宽。在一些示例中，隔离部件218可以具有在约10nm与约20nm之间的第二宽度W2，并且结隔离部件218J可以具有在约20nm与约30nm之间的第三宽度W3。在一个实施例中，第一宽度W1大于第三宽度W3。在该实施例中，第一宽度W1在约25nm与约50nm之间。隔离部件218和结隔离部件218J可以具有在约1nm与约20nm之间的第二高度H2。深隔离部件220和结隔离部件218J协同作用以降低跨越阱结2020的块体泄漏，该阱结2020是p阱202P和n阱202N之间的边界。
仍然参考图23，第一栅极结构270-1控制设置在p阱202P上方的第一n型MBC晶体管302。第一n型MBC晶体管302的沟道构件2080在两个n型源极/漏极部件260N之间延伸。第二栅极结构270-2控制设置在p阱202P上方的第二n型MBC晶体管304。第二n型MBC晶体管304的沟道构件2080在两个n型源极/漏极部件260N之间延伸。第三栅极结构270-3控制设置在n阱202N上方的第一p型MBC晶体管306。第一p型MBC晶体管306的沟道构件2080在两个p型源极/漏极部件260P之间延伸。第四栅极结构270-4控制设置在n阱202N上方的第二p型MBC晶体管308。第二p型MBC晶体管308的沟道构件2080在两个p型源极/漏极部件260P之间延伸。当沿着Y方向观看时，第一栅极结构270-1、第二栅极结构270-2、第三栅极结构270-3和第四栅极结构270-4中的每个包括类叉或类鱼骨结构。因为这个原因，第一n型MBC晶体管302、第二n型MBC晶体管304、第一p型MBC晶体管306和第二p型MBC晶体管308可以称为叉片晶体管或鱼骨晶体管。
基于以上讨论，可以看出本发明提供的优势。然而，应当理解，其它实施例可以提供额外的优势，并且在本文中不需要公开所有优势，并且没有特定的优势对于所有实施例都是需要的。例如，位于鱼骨或叉片晶体管下方的邻接的n阱和p阱由结隔离部件和设置在结隔离部件的下面的深隔离部件分隔开。深隔离部件可以具有与结隔离部件不同的形状。深隔离部件与结隔离部件协同作用，以防止跨越阱结的块体泄漏。
在一个方面，本发明提供了半导体结构的实施例，该半导体结构包括具有p型阱或n型阱的衬底，位于p型阱上方的第一基部，位于n型阱上方的第二基部，位于第一基部上方的第一多个沟道构件，位于第二基部上方的第二多个沟道构件，设置在第一基部和第二基部之间的隔离部件以及设置在隔离部件的下面的衬底中的深隔离结构。
在一些实施例中，隔离部件和深隔离结构延伸穿过p型阱和n型阱之间的结。在一些实施方式中，深隔离结构包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。在一些示例中，隔离部件的形状与深隔离结构的形状不同。在一些实施例中，半导体结构可以还包括：环绕包裹每个第一多个沟道构件的第一栅极结构；环绕包裹每个第二多个沟道构件的第二栅极结构；以及设置在第一栅极结构和第二栅极结构之间的第一介电鳍。在一些示例中，第一介电鳍设置在隔离部件上。在一些实施例中，第一栅极结构的第一部分在第一介电鳍和第一栅极结构之间延伸。在一些实施方式中，半导体结构可以还包括与第一多个沟道构件的侧壁接触的第二介电鳍。在一些实施方式中，第一栅极结构的第二部分在第一介电鳍和第一基部之间延伸。在一些示例中，半导体结构可以还包括与第一基部接触的第二介电鳍。
在另一方面，本发明提供了半导体结构的实施例，该半导体结构包括具有p型阱或n型阱的衬底，位于p型阱上方的第一基部，位于n型阱上方的第二基部，位于第一基部上方的第一n型外延部件，位于第二基部上方的第一p型外延部件，设置在第一基部与第二基部之间的第一隔离部件，以及设置在第一隔离部件的正下面的衬底中的深隔离结构。
在一些实施例中，半导体结构可以还包括设置在第一隔离部件上的第一介电鳍。第一介电鳍夹在第一n型外延部件和第一p型外延部件之间，并且第一介电鳍的宽度小于第一隔离部件的宽度。在一些实施例中，第一隔离部件的形状与深隔离结构的形状不同。在一些示例中，半导体结构可以还包括位于p型阱上方的第三基部，位于第三基部上方的第二n型外延部件，以及设置在第一基部和第三基部之间的第二隔离部件。第一隔离部件的宽度大于第二隔离部件的宽度。在一些示例中，半导体结构可以还包括设置在第二隔离部件上方的第二介电鳍。第二介电鳍夹在第一n型外延部件和第二n型外延部件之间，并且第二介电鳍的宽度与第二隔离部件的宽度基本相同。
在又一方面，本发明提供了方法的实施例，该方法包括：接收工件，工件包括位于衬底的p型阱区上方的第一鳍状结构和位于衬底的n型阱区上方的第二鳍状结构，第一鳍状结构和第二鳍状结构由结沟槽间隔开，将结沟槽进一步延伸至衬底中以形成深凹穴，在深凹穴中形成深隔离部件并且在结沟槽中形成隔离部件，以及在隔离部件上形成介电鳍，从而使得将介电鳍设置在第一鳍状结构和第二鳍状结构之间。
在一些实施例中，方法可以还包括在延伸结沟槽之前，沿着结沟槽的侧壁形成衬垫。在一些实施方式中，形成深隔离部件和隔离部件包括在深凹穴和结沟槽中沉积介电材料并且回蚀刻衬垫和介电材料以暴露第一鳍状结构和第二鳍状结构的侧壁。在一些示例中，方法可以还包括在形成介电鳍之前，在第一鳍状结构和第二鳍状结构的侧壁上方沉积半导体包覆层。在一些示例中，在形成介电鳍之后，介电鳍通过半导体包覆层与第一鳍状结构和第二鳍状结构间隔开。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
衬底，包括p型阱或n型阱；
第一基部，位于所述p型阱上方；
第二基部，位于所述n型阱上方；
第一多个沟道构件，位于所述第一基部上方；
第二多个沟道构件，位于所述第二基部上方；
隔离部件，设置在所述第一基部和所述第二基部之间；以及
深隔离结构，设置在所述隔离部件的下面的所述衬底中。
2.根据权利要求1所述的半导体结构，其中，所述隔离部件和所述深隔离结构延伸穿过所述p型阱和所述n型阱之间的结。
3.根据权利要求1所述的半导体结构，其中，所述深隔离结构包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
4.根据权利要求1所述的半导体结构，其中，所述隔离部件的形状与所述深隔离结构的形状不同。
5.根据权利要求1所述的半导体结构，还包括：
第一栅极结构，环绕包裹每个所述第一多个沟道构件；
第二栅极结构，环绕包裹每个所述第二多个沟道构件；以及
第一介电鳍，设置在所述第一栅极结构和所述第二栅极结构之间。
6.根据权利要求5所述的半导体结构，其中，所述第一介电鳍设置在所述隔离部件上。
7.根据权利要求5所述的半导体结构，其中，所述第一栅极结构的第一部分在所述第一介电鳍和所述第一栅极结构之间延伸。
8.根据权利要求7所述的半导体结构，还包括：
第二介电鳍，与所述第一多个沟道构件的侧壁接触。
9.一种半导体结构，包括：
衬底，包括p型阱或n型阱；
第一基部，位于所述p型阱上方；
第二基部，位于所述n型阱上方；
第一n型外延部件，位于所述第一基部上方；
第一p型外延部件，位于所述第二基部上方；
第一隔离部件，设置在所述第一基部与所述第二基部之间；以及
深隔离结构，设置在所述第一隔离部件的正下面的所述衬底中。
10.一种制造半导体结构的方法，包括：
接收工件，所述工件包括位于衬底的p型阱区上方的第一鳍状结构和位于所述衬底的n型阱区上方的第二鳍状结构，所述第一鳍状结构和所述第二鳍状结构由结沟槽间隔开；
将所述结沟槽进一步延伸至所述衬底中以形成深凹穴；
在所述深凹穴中形成深隔离部件并且在所述结沟槽中形成隔离部件；以及
在所述隔离部件上形成介电鳍，从而使得将所述介电鳍设置在所述第一鳍状结构和所述第二鳍状结构之间。
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Publication number Priority date Publication date Assignee Title
US11817504B2 (en) * 2021-01-26 2023-11-14 Taiwan Semiconductor Manufacturing Company, Ltd Isolation structures and methods of forming the same in field-effect transistors
EP4300563A1 (en) * 2022-06-29 2024-01-03 Huawei Technologies Co., Ltd. A multi-gate hybrid-channel field effect transistor
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Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7573108B2 (en) * 2006-05-12 2009-08-11 Micron Technology, Inc Non-planar transistor and techniques for fabricating the same
US8525292B2 (en) * 2011-04-17 2013-09-03 International Business Machines Corporation SOI device with DTI and STI
US20140315371A1 (en) 2013-04-17 2014-10-23 International Business Machines Corporation Methods of forming isolation regions for bulk finfet semiconductor devices
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US10553683B2 (en) * 2015-04-29 2020-02-04 Zeno Semiconductor, Inc. MOSFET and memory cell having improved drain current through back bias application
CN107592943B (zh) * 2015-04-29 2022-07-15 芝诺半导体有限公司 提高漏极电流的mosfet和存储单元
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US10546937B2 (en) 2017-11-21 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for noise isolation in semiconductor devices
US10593599B2 (en) 2018-03-07 2020-03-17 Globalfoundries Inc. Contact structures
US11164746B2 (en) 2018-06-26 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and a semiconductor device
US11062963B2 (en) 2018-08-15 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and process of integrated circuit having latch-up suppression
US11038036B2 (en) * 2018-09-26 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Separate epitaxy layers for nanowire stack GAA device
US11411090B2 (en) 2018-09-27 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structures for gate-all-around devices and methods of forming the same
US10790184B2 (en) 2018-09-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation with multi-step structure for FinFET device and method of forming the same
TWI732335B (zh) 2018-11-29 2021-07-01 台灣積體電路製造股份有限公司 積體電路裝置及其製造方法

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